TRF1223 www.ti.com SLWS166A – APRIL 2005 – REVISED JULY 2005 3.3-GHz TO 3.8-GHZ 1-W Power Amplifier FEATURES • • • • • • • • 1 W P-1dB Linear, 30-dB Gain Transmitter Operates Over the 3300-MHz to 3800-MHz Range Two TTL Controlled, 1-bit, 16-dB Gain Steps for 32 dB of Total Gain Control Superior Linearity (+45 dBm IP3) Over the Entire Frequency Range Auto-Bias Design With PA Enable Temperature Compensated Directional Coupler Detector Low Power Bias Mode Internally Matched 50-Ω Input and Output VNEG VPOS VDD Power Supply Power Amp / Attenuator PACNT LP Driver Amplifier Pre-Amp RFI RFO DETN DETP PAGAIN1 PAGAIN0 DESCRIPTION The TRF1223 is a highly integrated linear transmitter / power amplifier (PA) MMIC. The chip has two 16-dB gain steps that provide a total of 32-dB gain control via 1-bit TTL control signals. The chip also integrates a TTL mute function that turns off the amplifiers for power critical or TDD applications. A temperature compensated detector is included for output power monitor or ALC applications. The chip has a P1dB of +30 dBm and a third order intercept of +45 dBm. The TRF1223 is designed to function as a part of Texas Instruments complete 3.5-GHz chip set. The TRF1223 is the output power amplifier or a driver amplifier for higher power applications. The linear nature of the transmitter makes it ideal for complex modulations schemes such as high order QAM or OFDM. KEY SPECIFICATIONS • • • • • • OP1dB = +30 dBm Output IP3 = +45 dBm, Typical Gain = 30 dB, Typical Gain Flatness over Transmit Band ±2 dB Frequency Range = 3300 MHz to 3800 MHz ±0.5-dB Detected Output Voltage vs Temperature BLOCK DIAGRAM The detailed block diagram and the pin-out of the ASIC are shown in Figure 1. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005, Texas Instruments Incorporated TRF1223 www.ti.com LP PACNT VADJ3 VADJ2 VPOS VNEG VADJ1 SLWS166A – APRIL 2005 – REVISED JULY 2005 VDD1 VDD2 Power Supply VDD3A VDD3B Switched Attn Power Amp / Attenuator Driver Amp Switched Attn Pre-Amp RFI RFO DETN PAGAIN0 PAGAIN1 DETP Figure 1. Detailed Block Diagram of TRF1223 ELECTROSTATIC DISCHARGE NOTE The TRF1223 contain Class 1 devices. The following electrostatic discharge (ESD) precautions are recommended: • Protective outer garments • Handling in ESD safeguarded work area • Transporting in ESD shielded containers • Frequent monitoring and testing all ESD protection equipment • Treating the TRF1223 as extremely sensitive to ESD PINOUT TABLE Table 1. Pin Out of TRF1223 (1) (1) 2 PIN # PIN NAME I/O TYPE DESCRIPTION 1 VDD1 I Power Stage 1 dc drain supply power. The dc current through this pin is typically 5% of IDD. 2 VADJ1 I Analog No connection required for normal operation. May be used to adjust FET1 bias. DO NOT GROUND THIS PIN OR CONNECT TO ANY OTHER PIN. 3 GND - - Ground 4 RFI I Analog RF input to power amplifier, dc blocked internally 5 RFI I Analog RF input to power amplifier, dc blocked internally 6 VNEG I Power Negative power supply –5 V. Used to set gate voltage. This voltage must be sequenced with VDD. See (1). 7 VPOS I Power Positive power supply for bias circuits. Bias is +5 V. Used to set gate bias and logic input level. Proper sequencing: In order to avoid permanent damage to the power amplifier, the supply voltages must be sequenced. The proper power up sequence is VNEG, then VPOS,and then VDD. The proper power down sequence is remove VDD, then VPOS, and then VNEG. TRF1223 www.ti.com SLWS166A – APRIL 2005 – REVISED JULY 2005 Table 1. Pin Out of TRF1223 (continued) PIN # PIN NAME I/O TYPE DESCRIPTION 8 PAGAIN0 I Digital First 16-dB attenuator gain control. Logic high is high gain and logic low is low gain. 9 PAGAIN1 I Digital Second 16-dB gain control. Logic high is high gain and logic low is low gain. 10 VADJ2 I Analog No connection required for normal operation. May be used to adjust FET2 bias. DO NOT GROUND THIS PIN OR CONNECT TO ANY OTHER PIN. 11-14 GND - - 15 VADJ3 I Analog No connection required for normal operation. May be used to adjust FET3 bias DO NOT GROUND THIS PIN OR CONNECT TO ANY OTHER PIN. 16 LP I Digital Low power mode: Active high. Low power mode is lower dc and POUT mode. 17 PACNT I Digital Power amplifier enable, High is PA on, logic low is PA off (low current) 18 VDD3B I Power Stage 3 dc-drain supply power. This pin is internally dc connected to pin 23 (VDD3A). Bias must be provided to both pins for optimal performance. The total dc-current through these two pins is typically 70% of IDD. 19 GND - - 20 RFO O Analog RF output, internal dc block 21 RFO O Analog RF output, internal dc block 22 VDD3A - - 23 DETP I Power Stage 3 dc-rain supply power. This pin is internally dc connected to pin 18 (VDD3B). Bias must be provided to both pins for optimal performance. The total dc-current through these two pins is typically 70% of IDD. 24 DETN O Analog Detector output, positive. Voltage will be 0.5 V with/without RF output 25 GND O Analog Detector output, negative. Voltage is 0.5 V with no RF and decreases with increasing RF output power. 26-31 GND - - 32 VDD2 I Power Stage 2 dc-drain supply power. The dc current through this pin is typically 25% of IDD. Back - - Back of package has a metal base which must be grounded for thermal and RF performance. Ground Ground Ground Ground SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS PARAMETER TEST CONDITION VDD VPOS DC supply voltage VNEG MAX 0 8 V 0 5.5 V -5.5 I DD Current consumption Pin RF input power Tj Junction temperature Pd Power dissipation 0 1300 Digital input pins -0.3 Θjc Thermal resistance junction to case (1) Tstg Storage temperature Top Operating temperature Maximum case temperature derate for PCB thermal resistance Lead temperature 40 sec maximum (1) MIN UNIT V Ma 20 dBm 175 °C 6.5 W 5.5 20 °C/W -40 105 °C -40 85 °C 220 °C Thermal resistance is junction to case assuming thermal pad with 25 thermal vias under package metal base. See the recommended layout Figure 7 and application note RA1005 for more detail. 3 TRF1223 www.ti.com SLWS166A – APRIL 2005 – REVISED JULY 2005 DC CHARACTERISTICS PARAMETER VDD VDD supply voltage CONDITIONS MIN -40°C, PACNTRL = High, VDD = 5 V, LP = Low TYP MAX 5 7 UNIT V 875 IDD VDD supply current high power 25°C, PACNTRL = High, VDD = 5 V, LP = Low 925 mA 950 475 IDD VDD supply current low power 85°C, PACNTRL = High, VDD = 5 V, LP = Low VNEG Negative supply voltage -40°C, PACNTRL = High, VDD = 5 V, LP = High, 25°C INEG Negative supply current 25°C, PACNTRL = High, VDD = 5 V, LP = High, 25°C VPOS Positive supply digital voltage 85°C, PACNTRL = High, VDD = 5 V, LP = High, 25°C IPOS Positive supply digital current VIH Input high voltage VIL 550 mA 600 -5.25 -5 -4.75 15 25 5 5.25 35 50 mA 5 V Input low voltage 0.8 V IIH Input high current 300 µA IIL Input low current -50 µA 4.75 2.5 V mA V POWER AMPLIFIER CHARACTERISTICS Unless otherwise stated: VDD = 5 VS, IDD = 1050 mA, VPOS = 5 V, VNEG = -5 V, PAGAIN0 = 1, PAGAIN1 = 1, PACNT = 1, T = 25°C PARAMETER TEST CONDITIONS MIN TYP 3300 MAX UNIT 3800 MHz 32.5 dB F Frequency G Gain σG Standard deviation part-to-part gain At a single frequency, full gain GHG Gain flatness full band F = 3300 MHz to 3800 MHz GNB Gain flatness / 2 MHz OP-1dB Output power at 1-dB compression High power bias mode OP-1dB Output power at 1-dB compression Low power bias mode OIP3 Output third order intercept point High power bias mode OIP3 Output third order intercept point Low power bias mode Vdet Detector voltage output, differential (DETP-DETN) At POUT = 27 ±0.75 dBm, F = 3300 MHz to 3800 MHz at 25°C Detector accuracy vs temperature F = 3550 MHz, -30 to 75°C, Gain step size 1st step PAGAIN0 = Low, PAGAIN1 = High 13 16 19 dB Gain step size 2nd step PAGAIN0 = Low, PAGAIN1 = Low 26 32 38 dB 1 5 26 tSTEP Gain step response time PON/OFF On to Off Power ratio Max gain-to-gain with PACNT = Low NFHG Noise figure, max gain PAGAIN0 = High, PAGAIN1 = High NFLG Noise figure min gain PAGAIN0 = Low, PAGAIN1 = Low S12 Reverse isolation S11 Input return loss Z = 50 Ω S22 Output return loss Z = 50 Ω 4 30 0.3 4 30 43 dB 6 dB 31 dBm 27 dBm 48 dBm 38 dBm 150 mV ±0.5 dB 35 µs dB 6 30 -10 dB 0.2 7 dB 20 dB dB -12 dB -8 dB TRF1223 www.ti.com SLWS166A – APRIL 2005 – REVISED JULY 2005 TYPICAL PERFORMANCE All data was taken on parts mounted on PCBs using the pad layout specified in Figure 7 and the filled via process illustrated in Figure 8. 1.8 ATTEN = 10 dB RL = −8 dB RBW = 3 kHz VBW = 3 kHz SWP = 6.02 sec. RC1223B Detector Output 3.5 GHz 1.6 Voltage Dector − V 1.4 1.2 1 0.8 TA = 25C 0.6 TA = −40C 0.4 0.2 0 TA = 85C 0 Figure 2. Pulse Droop 5 10 15 20 25 PO − Output Power − dBm 30 35 Figure 3. Detector vs Temperature 1.8 RC1223B Detector Output 1.6 TA = 25C 3.8 GHz 1.4 Voltage Dector − V 3.3 GHz 1.2 1 3.5 GHz 0.8 0.6 0.4 0.2 0 0 5 10 20 25 15 PO − Output Power − dBm 30 35 Figure 4. Detector Output vs Frequency 5 TRF1223 www.ti.com SLWS166A – APRIL 2005 – REVISED JULY 2005 APPLICATION INFORMATION 6 TRF1223 www.ti.com SLWS166A – APRIL 2005 – REVISED JULY 2005 APPLICATION INFORMATION (continued) A typical application schematic is shown in Figure 5 and a mechanical drawing of the package outline (LPCC Quad 5 mm x 5 mm, 32-pin) is shown in Figure 6. The recommended PCB Layout mask is shown in Figure 7 below, along with recommendations on the board material Table 2 and construction Figure 8. VDD .01 µF 28 27 26 25 DETN 29 GND 30 GND 31 GND VDD2 32 Vdet GND 100 pF GND 1 µF GND 10 µF* BASE 1 VDD1 DETP 24 100 pF .01 µF 2 VADJ1 VDD3A 23 100 pF 3 GND GND 22 4 RFI RFO RFI RFO VNEG GND VPOS VDD3B PAGAIN0 PACNT .01 µF 21 RFI RFI RFO 5 20 VNEG 6 9 10 11 12 18 100 pF 13 14 .01 µF 17 LP VADJ3 GND Place 100 pF Capacitors Close to Package Pins. GND 8 GND .01 µF GND 1 µF 7 100 pF VADJ2 VPOS .01 µF PAGAIN1 1 µF 19 100 pF 15 16 *100 pF Maybe Required for High Speed Pulse Application PACNT 1 kΩ ** LP 1 kΩ ** PAGAIN1 1 kΩ ** PAGAIN0 **1 kΩ Resistors on Digital Inputs are required to Prevent Possible Device Damage Due to ESD and/or Over Voltage 1 kΩ ** Figure 5. Recommended TRF1223 Application Schematic Figure 6. Package Drawing Table 2. PCB Recommendations Board Material FR4 Board Material Core Thickness 10 mil Copper Thickness (starting) 1 oz Prepreg Thickness 8 mil Recommended Number of Layers 4 Via Plating Thickness 0.5 oz 7 TRF1223 www.ti.com SLWS166A – APRIL 2005 – REVISED JULY 2005 Table 2. PCB Recommendations (continued) Final Plate White immersion tin Final Board Thickness 33 to 37 mil Additional Copper Ground and via Holes at Customer Discreation 0.20 TYP PIN 1 3.50 0.75 TYP 0.50 TYP 3.80 0.75 TYP DIA 0.38 0.60 TYP TYP 0.25 TYP 3.50 SOLDER MASK: NO SOLDERMASK UNDER CHIP, ON LEAD PADS OR ON GROUND CONNECTIONS. 25 VIA HOLES, MIN, EACH 0.38 mm. DIMENSIONS in mm Figure 7. Recommended Pad Layout 8 TRF1223 www.ti.com SLWS166A – APRIL 2005 – REVISED JULY 2005 Dia 15 Mil 1 oz Copper + 1/2 oz Copper Plated Upper and Lower Surfaces 10 Mil Core FR4 1 oz Copper 8 Mil Prepreg 35 Mil 1 oz Copper 10 Mil Core FR4 DuPont CB 100 Conductive Via Plug 1/2 oz Copper Plated Figure 8. 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