SP7656 PowerBlox 3A, 29V Non-Synchronous Buck Converter FEATURES Wide Input Voltage Range 4.5V – 29V 3 Amps Continuous 4 Amps Peak Output Current Internal Compensation Input Feedforward Control improves Transient and Regulation 600kHz Constant Frequency Operation Low 0.6V Reference Voltage High output setpoint accuracy of 1% Internal Soft Start Small SO8-EP Thermally Enhanced Package Adjustable Overcurrent Protection Lead Free, RoHS Compliant Package DESCRIPTION The SP7656 is a PWM controlled step down (buck) voltage mode regulator co-packaged with a PChannel FET. It operates from 4.5V to 29V making it suitable for 5V, 12V and 24V applications. The programmable overcurrent protection is based on internal FET resistance sensing and allows setting the overcurrent protection value up to a 300mV threshold (measured between VIN-LX). The SP7656 is packaged in a thermally enhanced 8-pin SO8 package making it one of the smallest converters available capable of operating from 5, 9, 12, 18 and 24VDC supplies. TYPICAL APPLICATION CIRCUIT 11/07/08 SP7656 PowerBlox Copyright 2008 EXAR Corporation 1 ABSOLUTE MAXIMUM RATINGS These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. PVIN….............................................................. -0.3V to 30V SVIN…………………………………………..….. -0.3V to 30V Lx………………………….……………………….…-2V to 30V ISET…………………………….……………………-2V to 30V FB……………..................................................-0.3V to 5.5V Storage Temperature..…….……………..…-65 C to 150 C Junction Temperature..................................-40C to 125C Lead Temperature (Soldering, 10 sec)......…………..300 C ELECTRICAL SPECIFICATIONS Specifications are for TAMB=TJ=25C, and those denoted by ♦ apply over the full operating range, -40C< Tj <85C. Unless otherwise specified: VIN =4.5V to 29V, CIN = 4.7F. PARAMETER ♦ MIN TYP MAX UNITS UVLO Turn-On Threshold 4.2 4.35 4.5 V 0C< Tj <85C UVLO Turn-Off Threshold 4.0 4.15 4.3 V 0C< Tj <85C UVLO Hysteresis Operating Input Voltage Range Operating Input Voltage Range Operating VCC Current Reference Voltage Accuracy Reference Voltage Accuracy Reference Voltage Reference Voltage Switching Frequency Minimum ON-Pulse Duration Minimum Duty Cycle Maximum Duty Cycle SVIN - VDR voltage difference 0.2 V 4.5 29 V 7 29 V 3 mA 0.3 0C< Tj <85C ♦ VFB=1.2V 5.5 % % V V kHz ns % % V Overcurrent Threshold 270 300 330 mV Measure SVIN - ISET ISET pin Input Current OFF interval during hiccup 25 30 100 35 µA ms VISET = SVIN Soft start time 3 5 9 ms 0.8 1.0 100 1.2 V mV SHDN Threshold SHDN Threshold Hysteresis P-Channel FET ON Resistance P-Channel FET Source leakage 0.588 510 0.5 0.5 0.6 0.6 600 40 CONDITIONS 100 4.5 2 0.612 690 100 0 ♦ ♦ *See Duty Cycle restriction- applications section ♦ ♦ Measure SVIN – VDR, SVIN>7V VFB=0.58V, measure between VIN=4.5V and first GATE pulse Apply voltage to FB mΩ 60 3 ♦ 5 µA 11/07/08 SP7656 PowerBlox Copyright 2008 EXAR Corporation 2 PIN DESCRIPTION PIN # PIN NAME DESCRIPTION 1 FB Regulator feedback input. Connect to a resistive voltage-divider network to set the output voltage. This pin can be also used for ON/OFF control. If this pin is pulled above 1V the controller resets internal soft start circuit. 2 GND Ground pin. 3 VDR Power supply for the internal driver. This voltage is internally regulated to about 5V below VIN. Place a 0.1uF decoupling capacitor between VDR and Vin as close as possible to the IC. 4,5 PVIN Internal P-Channel FET Source. Connect to input voltage. 6 SVIN Input power supply for the controller. Place input decoupling capacitor as close as possible to this pin. Connect to input voltage. 7,9 LX 8 ISET Internal P-Channel FET Drain. Connect to the output inductor. This pin is used as a current limit input for the internal current limit comparator. Connect to LX through an optional resistor. Internal threshold is pre-set to 300mV nominal and can be decreased by changing the external resistor based on the following formula: VTRSHLD = 300mV – 30uA * R. Where R≤3kΩ CONVERTER BLOCK DIAGRAM 5V SVIN VDR Oscillator Vin - 5V LDO PVIN VIN 5V Internal LDO I = k x VIN FAULT VREF PWM Latch Reset Dominant FET GATE S + FB - Internal P-FET R + LX R VDR PWM Comparator Error Amplifier Power PAD FAULT FAULT 200ms delay FAULT Register S + UVLO ISET - ENBL 4-Bit counter Overcurrent Comparator 30uA VIN - 0.3V GND + 1V - R POR R Set Dominant 11/07/08 SP7656 PowerBlox Copyright 2008 EXAR Corporation 3 SP7656 General Overview: f DBPOLE The SP7656 PowerBlox is a fixed frequency, voltage mode, non-synchronous PWM controller co-packaged with a P-Channel FET. SP7656 is optimized for minimum component, small form factor and cost effectiveness. It has been designed for single-supply operation ranging from 4.5V to 29V. SP7656 has Type-2 internal compensation for use with Electrolytic/Tantalum output capacitors. For ceramic capacitors Type-3 compensation can be implemented by simply adding an R and C between output and Feedback. 1 2 L COUT Creating a Type-3 compensation Network The above condition requires the ESR zero to be at a lower frequency than the double-pole from the LC filter. If this condition is not met, Type-3 compensation should be used and can be accomplished by placing a series RC combination in parallel with R1 as shown below. The value of CZ can be calculated as follows and RZ selected from table 1. A precision 0.6V reference, present on the positive terminal of the internal error amplifier, permits programming of the output voltage down to 0.6V via the FB pin. The output of the Error Amplifier is internally compared to a feed-forward (VIN/5 peak-to-peak) ramp and generates the PWM control. CZ LC R1 fESRZERO/fDBPOLE RZ 1X 2X 3X 5X >= 10X Timing is governed by an internal oscillator that sets the PWM frequency at 600kHz. SP7656 contains useful protection features. Over-current protection is based on the internal MOSFET Rds(on) and is programmable via a resistor placed between ISET and LX node. Under-Voltage Lock-Out (UVLO) ensures that the controller starts functioning only when sufficient voltage exists for powering IC’s internal circuitry. 50K 40K 30K 10K 2K Table1- RZ Selection Vout SP7656 CP1 2pF RZ SP7656 Loop Compensation CZ CZ2 The SP7656 includes Type-2 internal compensation components for loop compensation. External compensation components are not required for systems with tantalum or aluminum electrolytic output capacitors with sufficiently high ESR. Use the condition below as a guideline to determine whether or not the internal compensation is sufficient for your design. Type-2 internal compensation is sufficient if the following condition is met: 130pF RZ2 200k R1 200k, 1% FB + Vref =0.6V R2 Error Amplif ier Figure 1- RZ and CZ in conjunction with internal compensation components form a Type-3 compensation f ESRZERO f DBPOLE where: f ESRZERO 1 2 RESR COUT 11/07/08 SP7656 PowerBlox Copyright 2008 EXAR Corporation 4 the maximum value of Rs should be limited to 3kΩ. Overcurrent Protection Using the ON/OFF Function via VFB The feedback pin serves a dual role of On/Off control. The MOSFET driver is disabled when a voltage greater than 1V is applied at FB pin. Maximum voltage rating of this pin is 5.5V. The controlling signal should be applied through a small signal diode to FB pin. Please note that an optional 10k bleeding resistor across the output helps keep the output capacitor discharged under no load condition. Programming the Output Voltage To program the output voltage, calculate R2 using the following equation: Figure 2 – Overcurrent Protection Circuit The overcurrent protection circuit functions by monitoring the voltage across the internal PChannel FET. When this voltage exceeds 0.3V (nominal), the overcurrent comparator triggers and the controller enters hiccup mode. Since the FET has nominal Rds(on) of 0.06Ω, assuming no temperature rise, the overcurrent will trigger at Iocp = 0.3V/0.06Ω=5A. To program a lower overcurrent use a resistor Rs between ISET and LX pins. Calculate Rs from: Rs R2 200k Vout 1 0.6 0.6 is used as it is the reference voltage of the SP7656. 200k is a fixed-value and is the top resistor in the output set point resistor pair. In addition to being part of the voltage divider, it is part of the compensation network. R1 of the output voltage divider should always be 200kΩ. 0.3 1.15 Iocp 0.06 Kt 30uA Soft Start Where: - 1.15 is a multiplier to calculate peak current - Iocp is the desired overcurrent protection, - 0.06Ω is nominal FET Rsd(on) at 25°C - Kt is a multiplier that calculates increase in Rds(on) for a given temperature Soft Start is preset internally to 5ms (nominal). Internal Soft Start eliminates the need for the external capacitor CSS that is commonly used to program this function. Kt is 1.0 and 1.4 for the FET operating at 25°C and 150°C respectively. This accounts for 40% increase in FET Rds(on) as temperature is increased from 25°C to 150°C. Select the input capacitor for Voltage, Capacitance, ripple current, ESR and ESL. Voltage rating is nominally selected to be approximately twice the input voltage. The RMS value of input capacitor current, assuming a low inductor ripple current (IRIP), can be calculated from: Input Capacitance Selection Example: Calculate Rs for Iocp of 3.5A. FET operating temperature is 88°C. Rs 0.3 1.15 3.5 A 0.06 1.2 30uA Icin Iout D (1 D) Rs=340Ω In general total input voltage ripple should be maintained below 1.5% of VIN (not to exceed 180mV). Input voltage ripple has three components: ESR and ESL cause a step voltage drop upon turn on of the MOSFET. During the on time Using the above equation there is good agreement between calculated and test results for Rs up to 3k. For Rs larger than 3k test results are lower than those predicted by the Rs equation due to circuit parasitics. Therefore 11/07/08 SP7656 PowerBlox Copyright 2008 EXAR Corporation 5 the capacitor discharges linearly as it supplies IOUT-Iin. The contribution to Input voltage ripple by each term can be calculated from: V , Cin provides a satisfactory method for calculating COUT. Select ESR such that output voltage ripple (VRIP) specification is met. There are two components to the output ripple voltage: The first component arises from charge transferred to and from COUT during each cycle. The second component is due to inductor ripple current flowing through the output capacitor’s ESR. It can be calculated from: Iout Vout (Vin Vout) fs Cin Vin 2 V , ESR ESR Iout 0.5 Irip V , ESL ESL Iout 0.5 Irip Vrip Irip Trise Where Trise is the rise time of current through Capacitor. The total input voltage ripple is sum of the above: 1 ESR 8 Cout fs 2 2 Where: IRIP is inductor ripple current fs is switching frequency COUT is output capacitor calculated above Note that a smaller inductor results in a higher inductor ripple current, therefore requiring a larger COUT and/or lower ESR in order to meet the output voltage ripple requirement. Output Capacitor Selection Select the output capacitor for voltage rating, capacitance and Equivalent Series Resistance (ESR). Schottky Rectifier Selection Nominally the voltage rating is selected to be twice as large as the output voltage. Select the capacitance to satisfy the specification for output voltage overshoot/undershoot caused by current step load. A steady-state output current IOUT corresponds to inductor stored 2 energy of ½ L IOUT . Select the Schottky based on the voltage rating VR, Forward voltage Vf, and thermal resistance Rthja. For a low duty cycle application the Schottky is conducting most of the time and its conduction losses are the largest component of losses in the converter. Conduction losses can be estimated from: A sudden decrease in IOUT forces the energy surplus in L to be absorbed by COUT. This causes an overshoot in output voltage that is corrected by the power switch reducing in duty cycle. Use the following equation to calculate COUT: Vout Pc Vf Iout 1 Vin where: Vf is diode forward voltage at IOUT I 2 2 I12 Cout L 2 2 Vos Vout The AC losses from the switching capacitance of a Schottky are negligible and can be ignored. Where: L is the output inductance I2 is the step load high current I1 is the step load low current Vos is output voltage including overshoot VOUT is steady state output voltage Output voltage undershoot calculation is more complicated. Test results for SP7656 buck circuits show that undershoot is approximately equal to overshoot. Therefore above equation 11/07/08 SP7656 PowerBlox Copyright 2008 EXAR Corporation 6 Inductor Selection Layout Suggestions Select the Inductor for inductance L and saturation current ISAT. Make sure to select an inductor with ISAT higher than the programmed overcurrent level. i) Place the input capacitor(s) as close as possible to the 7656 IC. ii) Create a pad under the IC that connects the power pad (pin 9) to the inductor. Duplicate this pad through the pcb layers if present, and on the bottom side of the PCB. Use multiple vias to connect these layers to aid in heat dissipation. Do not oversize this pad - since the LX node is subjected to very high dv/dt voltages, the stray capacitance formed between these islands and the surrounding circuitry will tend to couple switching noise iii) Connect the Schottky diode cathode as close as possible to the LX node and inductor input side. Connect the anode to a large diameter trace or a copper area that connects the input ground to the output ground. iv) The output capacitors should be placed as close to the load as possible. Use short wide copper regions to connect output capacitors to load to avoid inductance and resistances. v) Keep other sensitive circuits and traces away from the LX node in particular and away from the power supply completely if possible. The inductance can be calculated from: Vout L Vin Vout Vin 1 f 1 Irip where: VIN is converter input voltage VOUT is converter output voltage f is the switching frequency (300kHz) IRIP is inductor peak-to-peak current ripple (nominally set to 30% of IOUT) Keep in mind that a higher inductor ripple current results in a smaller inductance – and smaller inductor. A smaller inductor has the advantages of small size, low DC equivalent resistance DCR, high saturation current and allows the use of a lower output capacitance to meet a given step load transient. A higher inductor ripple current level also has disadvantages. It increases the output voltage ripple and increases the current at which converter enters Discontinuous Conduction Mode. The output current at which converter enters DCM is ½ of IRIP. Note that a negative current step load that drives the converter into DCM will result in a large output voltage transient. Therefore the lowest current for a step load should be larger than ½ of IRIP. Restriction on high duty cycle operation The SP7656 is optimized to provide superior performance for low duty cycle applications. For applications with output voltages below 9V, the device will operate normally at the expected 600kHz switching frequency for conversions with less than 50% duty cycle. For applications with output voltages below 9V and greater than 50% duty cycle, the device will enter into a pulse skipping mode. This is due to the FB voltage to internal ramp voltage ratio of the device, and is an intended behavior from an architecture optimized for superior performance in low duty cycle conversion applications and results in a small increase in output ripple voltage for any given circuit. For output voltages above 9V, the device will operate at a constant 600kHz switching frequency across the specified duty cycle range up to 100%. Diode Cin Cout 7656 Lout For more detail on the SP7656 layout see the SP7656EVB (Evaluation Board) Manual available on our web site. Each layer is shown in detail as well as a complete bill of materials and performance characterization. 11/07/08 SP7656 PowerBlox Copyright 2008 EXAR Corporation 7 Application Information Figure 2- Typical application circuit E ffic ie n c y v s Io u t (12Vo u t) 100 100 90 95 E ffic ienc y (% ) E ffic ien c y (%) E ffic ie n c y v s Io u t (3.3Vo u t) 80 70 V in= 12V 60 V in= 24V 50 90 85 80 75 V in= 14V V in= 24V V in= 29V 70 65 40 60 0.0 1.0 2.0 3.0 4.0 0.0 1.0 Io u t (A) 2.0 3.0 4.0 Io u t (A) Figure 3- Efficiency, Natural convection at Vout=3.3V, Ta= 25°C Figure 4- Efficiency Natural convection at Vout=12V, Ta= 25°C, LX Vin Output Ripple Vout Inductor Ripple Current 2A/div Iout 2A/div Figure 5- Output Ripple Vout=3.3V, Ta= 25°C Figure 6- Start-up Vout=3.3V, Ta= 25°C 11/07/08 SP7656 PowerBlox Copyright 2008 EXAR Corporation 8 ___________________________________________ PACKAGE: 8-pin HSOICN 11/07/08 SP7656 PowerBlox Copyright 2008 EXAR Corporation 9 Ordering Information Part Number Temperature Range Package SP7656EN2-L………………………….- 40°C to 125°C…………………(Lead Free) 8-pin HSOICN SP7656EN2-L/TR……………………..- 40°C to 125°C………………….(Lead Free) 8-pin HSOICN /TR = Tape and Reel Pack Quantity for Tape and Reel is 2500 Revision History DATE February 2008 REVISION July 2008 DESCRIPTION A - Original Release B - Block Diagram Update to include FET Formatting changes For further assistance: Email: EXAR Technical Documentation: [email protected] http://www.exar.com/TechDoc/default.aspx? Exar Corporation Headquarters and Sales Office 48720 Kato Road Fremont, CA 94538 main: 510-668-7000 fax: 510-668-7030 EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. 11/07/08 SP7656 PowerBlox Copyright 2008 EXAR Corporation 10