74ACT11652
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS087A – APRIL 1993 – REVISED APRIL 1996
D
D
D
D
D
D
Independent Registers and Enables for A
and B Buses
Multiplexed Real-Time and Stored Data
Flow-Through Architecture Optimizes
PCB Layout
Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
EPICt (Enhanced-Performance Implanted
CMOS) 1-mm Process
500-mA Typical Latch-Up Immunity at
125°C
DW PACKAGE
(TOP VIEW)
GAB
A1
A2
A3
A4
GND
GND
GND
GND
A5
A6
A7
A8
GBA
description
This device consists of bus transceiver circuits,
D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the
data bus or from the internal storage registers.
Enable GAB and GBA are provided to control the
transceiver functions. SAB and SBA control pins
are provided to select whether real-time or stored
data is transferred. The circuitry used for select
control eliminates the typical decoding glitch that
occurs in a multiplexer during the transition
between stored and real-time data. A low input
level selects real-time data, and a high selects
stored data. Figure 1 illustrates the four
fundamental bus-management functions that can
be performed with the octal bus transceivers and
registers.
1
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
CAB
SAB
B1
B2
B3
B4
VCC
VCC
B5
B6
B7
B8
CBA
SBA
Data on the A or B data bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the
appropriate clock pins (CAB or CBA), regardless of the select or enable control pins. When SAB and SBA are
in the real-time transfer mode, it is also possible to store data without using the internal D-type flip-flops by
simultaneously enabling GAB and GBA. In this configuration, each output reinforces its input. Thus, when all
other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains at its last
state.
The 74ACT11652 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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• DALLAS, TEXAS 75265
1
74ACT11652
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
L
CAB
CBA
SAB
SBA
GAB
L
X
X
X
L
H
GAB
GBA
CAB
CBA
SAB
X
L
H
↑
X
X
X
↑
L
H
↑
↑
GBA
CAB
CBA
SAB
SBA
H
X
X
L
X
REAL-TIME TRANSFER BUS A TO BUS B
BUS A
BUS B
BUS A
REAL-TIME TRANSFER BUS B TO BUS A
SBA
GAB
GBA
CAB
CBA
SAB
SBA
X
X
L
L
H or L
H or L
X
H
X
X
X
X
STORAGE FROM A AND/OR B
TRANSFER STORED DATA TO A AND/OR B
Figure 1. Bus Transfer Diagram
2
BUS B
BUS A
GBA
BUS B
GAB
BUS B
BUS A
SCAS087A – APRIL 1993 – REVISED APRIL 1996
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
74ACT11652
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS087A – APRIL 1993 – REVISED APRIL 1996
FUNCTION TABLE
DATA I/O†
INPUTS
GAB
GBA
CAB
CBA
SAB
SBA
L
H
H or L
H or L
X
X
L
H
↑
↑
X
X
X
H
↑
H or L
H
H
↑
↑
X
X‡
L
X
H or L
↑
X
L
L
↑
↑
X
X
X‡
L
L
X
X
X
L
L
L
X
H or L
X
H
H
H
X
X
L
X
H
H
H or L
X
H
X
H
L
H or L
H or L
H
OPERATION OR FUNCTION
A1–A8
B1–B8
Input
Input
X
Input
Unspecified†
Store A, hold B
X
Input
Unspecified†
Output
Store A in both registers
Input
Hold A, store B
Output
Input
Store B in both registers
Output
Input
Input
Output
H
Output
Isolation
Store A and B data
Real-time B data to A bus
Stored B data to A bus
Real-time A data to B bus
Stored A data to B bus
Stored A data to B bus and
stored B data to A bus
Output
† The data-output functions may be enabled or disabled by various signals at the GAB or GBA inputs. Data-input functions are always enabled,
i.e., data at the bus terminals is stored on every low-to-high transition on the clock inputs.
‡ Select control = L: clocks can occur simultaneously. Select control = H: clocks must be staggered to load both registers.
logic symbol§
14
GBA
1
GBA
16
CBA
15
SBA
28
CAB
27
SAB
A1
2
EN1 [BA]
EN2 [AB]
C4
G5
C6
G7
1
6D
A2
A3
A4
A5
A6
A7
A8
3
26
≥1
1
5
5
7
7
4D
1
≥1
B1
2
25
B2
4
24
5
23
10
20
11
19
12
18
13
17
B3
B4
B5
B6
B7
B8
§ This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
74ACT11652
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS087A – APRIL 1993 – REVISED APRIL 1996
logic diagram (positive logic)
GBA 14
GAB
1
16
CBA
15
SBA
28
CAB
27
SAB
One of Eight
Channels
A1
1D
C1
2
26
B1
1D
C1
To Seven Other Channels
absolute maximum rating over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA
Maximum power dissipation at TA = 55°C (in still air) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
recommended operating conditions (see Note 3)
MAX
4.5
5.5
Supply voltage
VIL
VI
Low-level input voltage
Input voltage
0
VO
IOH
Output voltage
0
IOL
∆t/∆V
Low-level output current
High-level input voltage
2
High-level output current
Input transition rise or fall rate
TA
Operating free-air temperature
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
4
MIN
VCC
VIH
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
V
V
0.8
V
VCC
VCC
V
–24
mA
V
24
mA
0
10
ns/V
–40
85
°C
74ACT11652
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS087A – APRIL 1993 – REVISED APRIL 1996
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
4.5 V
IOH = – 50 mA
VOH
IOH = – 24 mA
IOH = – 75 mA{
IOZ
II
GAB or GBA
ICC
DICC§
IOL = 75 mA{
VO = VCC or GND
VI = VCC or GND
VI = VCC or GND,
One input at 3.4 V,
Ci
GAB or GBA
Co
A or B ports
MIN
4.4
4.4
5.5 V
5.4
5.4
4.5 V
3.94
3.8
5.5 V
4.94
MAX
V
4.8
0.1
0.1
5.5 V
0.1
0.1
4.5 V
0.36
0.44
5.5 V
0.36
0.44
5.5 V
IO = 0
Other inputs at GND or VCC
VI = VCC or GND
VO = VCC or GND
UNIT
3.85
4.5 V
IOL = 24 mA
A or B ports‡
TA = 25°C
TYP
MAX
5.5 V
IOL = 50 mA
VOL
MIN
V
1.65
±5
mA
±0.1
±1
mA
8
80
mA
0.9
1
mA
5.5 V
±0.5
5.5 V
5.5 V
5.5 V
5V
4.5
pF
5V
12
pF
† Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
‡ For I/O ports, the parameter IOZ includes the input leakage current.
§ This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 2)
TA = 25°C
MIN
MAX
PARAMETER
fclock
tw
Clock frequency
0
tsu
th
Setup time, A before CLK↑ or B before CBA↑
Pulse duration, CAB or CBA high or low
Hold time, A after CAB↑ or B after CBA↑
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
105
MIN
MAX
UNIT
0
105
MHz
4.8
4.8
ns
4
4
ns
2.5
2.5
ns
5
74ACT11652
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS087A – APRIL 1993 – REVISED APRIL 1996
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 2)
PARAMETER
fmax
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
FROM
(INPUT)
TO
(OUTPUT)
MIN
TA = 25°C
TYP
MAX
105
A or B
B or A
CBA or CAB
A or B
SBA or SAB†
with A or B high
A or B
SBA or SAB†
with A or B low
A or B
GBA
A
GBA
A
GAB
B
GAB
B
MIN
MAX
105
UNIT
MHz
3.8
7
9.9
3.8
11.1
3.4
6.7
10.7
3.4
11.6
5.4
8.4
11.8
5.4
13.1
6.1
9.4
13.1
6.1
14.4
2.8
6.2
10.1
2.8
11
5.5
8.7
12.1
5.5
13.3
4.9
7.8
11
4.9
12.2
3.9
7.5
11.6
3.9
12.6
3.3
7.2
11.4
3.3
12.6
4.1
7.8
12.6
4.1
13.8
5.2
7.2
9.3
5.2
9.9
4.8
6.7
8.6
4.8
9.3
5.1
9.1
13.4
5.1
15.2
5.8
9.7
14.2
5.8
16.1
3.4
6.8
9.7
3.4
10.3
3.1
6
8.8
3.1
9.3
ns
ns
ns
ns
ns
ns
ns
ns
† These parameters are measured with the internal output state of the storage register opposite that of the bus input.
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd
d
6
Power dissipation capacitance per transceiver
POST OFFICE BOX 655303
TEST CONDITIONS
Outputs enabled
Outputs disabled
• DALLAS, TEXAS 75265
CL = 50 pF,
pF
f = 1 MHz
TYP
59
14
UNIT
pF
74ACT11652
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS087A – APRIL 1993 – REVISED APRIL 1996
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
500 Ω
LOAD CIRCUIT
3V
1.5 V
Timing Input
0V
tw
tsu
3V
Input
1.5 V
th
1.5 V
3V
1.5 V
1.5 V
Data Input
0V
0V
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
Output
Control
(low-level
enabling)
3V
1.5 V
Input
1.5 V
0V
tPHL
tPLH
In-Phase
Output
50% VCC
50% VCC
0V
tPZL
VOH
50% VCC
VOL
Output
Waveform 2
S1 at GND
(see Note B)
[ VCC
tPLZ
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLH
tPHL
Out-of-Phase
Output
VOH
50% VCC
VOL
3V
1.5 V
1.5 V
50% VCC
VOL
tPHZ
tPZH
VOLTAGE WAVEFORMS
20% VCC
50% VCC
80% VCC
VOH
[0V
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 2. Load Circuit and Voltage Waveforms
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7
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