LM3447 www.ti.com SNOSC65 A – APRIL 2012 – REVISED MAY 2012 Phase Dimmable, Primary Side Power Regulated PFC Flyback Controller for LED Lighting Check for Samples: LM3447 FEATURES DESCRIPTION • The LM3447 is a versatile power factor correction (PFC) controller designed to meet the performance requirements of residential and commercial phase-cut dimmer compatible LED lamp drivers. The device incorporates a phase decoder circuit and an adjustable hold current circuit to provide smooth, flicker free dimming operation. A proprietary primary side control technique based on input voltage feedforward is used to regulate the input power drawn by the LED driver and to achieve line regulation over a wide range of input voltage. Valley switching operation is implemented to minimize switching loss and reduce EMI. An internal thermal foldback circuit is provided to protects the LEDs from damage based on the temperature sensed by a single external NTC resistor. Additional features include LED open circuit and short circuit protection, cycle-by-cycle FET over-current protection, burst mode fault operation using an internal 812ms fault timer and internal thermal shutdown. 1 • • • • • • • • • Integrated Phase Angle Decode – Leading and Trailing Edge Compatible – Over 50:1 Dimming Range Power Factor Correction with Low Total Harmonic Distortion Primary Side Control Using Input Voltage Feedforward Technique Input Power Regulation Scheme with Improved Line Regulation Constant Power Operation of LEDs to Compensate for Forward Voltage Variations Over Temperature and Lifetime Fixed Frequency Discontinuous Conduction Mode Operation Valley Switching Operation to Achieve High Efficiency and Low EMI Efficient TRIAC Hold Current Management Thermal Foldback Function for LED Protection LED Open Circuit and Short Circuit Protection APPLICATIONS • • • The LM3447 is ideal for implementing dimmable, isolated single stage LED lamp drivers where simplicity, low-component count and small solution size are of primary importance. This device is currently available in a TSSOP 14-pin package. Dimmable A19, R20, PAR30/38 LED Lamps Recessed LED Downlights and Pendant Lights Industrial and Commercial Solid State Lighting TYPICAL APPLICATION DIAGRAM + + – – LM3447 VAC BIAS TSNS HOLD FLT1 AUX FLT2 VCC FF GATE INV ISNS COMP GND 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012, Texas Instruments Incorporated LM3447 SNOSC65 A – APRIL 2012 – REVISED MAY 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) (1) (2) TEMPERATURE RANGE (TJ) PACKAGE (2) PINS PACKAGE DRAWING ORDERABLE DEVICE NUMBER LM3447MT Tube 94 –40°C to 125°C TSSOP 14 MTC14 LM3447MTE Tape and Reel 250 LM3447MTX Tape and Reel 2500 TRANSPORT MEDIA QUANTITY For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. ABSOLUTE MAXIMUM RATINGS (1) All voltages are with respect to GND, –40°C < TJ = TA < 125°C, all currents are positive into and negative out of the specified terminal (unless otherwise noted) VALUE Supply voltage Input voltage range Output voltage range VCC (2) HOLD (3) V 6 V TSNS, FLT1, FLT2, FF, INV, COMP, ISNS, AUX –0.3 6 V GATE (2) (Pulse < 20ns) –1.5 19 V (4) Storage temperature range (5) TSTG –65 Soldering, 10s (2) (3) 2 10 mA 165 °C 150 °C 260 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. VCC is internally limited to approximately 18.9V. See ELECTRICAL CHARACTERISTICS table. HOLD current is limited by the internal power dissipation of the device. Voltage on VAC and BIAS is internally clamped. The clamp level varies with operating conditions. In normal use, VAC and BIAS are current fed with the voltage internally limited. Maximum junction temperature is internally limited. PACKAGE DISSIPATION RATINGS (1) (1) V 22 TJ (5) (5) 22 –0.3 IBIAS (2) (3) (4) –0.3 –0.3 Junction temperature (1) MAX VAC (4) Continuous input current Lead temperature UNIT MIN (2) PACKAGE θJA, THERMAL IMPEDANCE JUNCTION TO AMBIENT,NO AIRFLOW (°C/W) TA = 25°C POWER RATING (mW) TA = 70°C POWER RATING (mW) TA = 85°C POWER RATING (mW) TSSOP–14 (MTC) 155 (1) 645 (3) 355 (3) 258 (3) Tested per JEDEC EIA/JESD51-1. Thermal resistance is a function of board construction and layout. Air flow reduces thermal resistance. This number is included only as a general guideline; see TI document (SPRA953) device Package Thermal Metrics. Thermal resistance to the circuit board is lower. Measured with standard single-sided PCB construction. Board temperature, TB, measured approximately 1 cm from the lead to board interface. This number is provided only as a general guideline. Maximum junction temperature, TJ, equal to 125°C Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: LM3447 LM3447 www.ti.com SNOSC65 A – APRIL 2012 – REVISED MAY 2012 RECOMMENDED OPERATING CONDITIONS (1) over operating free-air temperature range (unless otherwise noted) VCC Input Voltage IBIAS BIAS current from a high impedance source IVAC VAC current from a high impedance source TJ Operating junction temperature (1) MIN TYP MAX 7.5 14 17.5 V 500 μA 500 μA 125 °C –40 25 UNIT For specified performance limits and associated test conditions, see the Electrical Characteristics table. ELECTROSTATIC DISCHARGE (ESD) PROTECTION Human Body Model (HBM) Field Induced Charged Device Model (FICDM) MAX UNIT 2 kV 750 V ELECTRICAL CHARACTERISTICS Unless otherwise specified –40°C < TJ = TA < 125°C, VCC = 14V, VTSNS = 1.75V, VFLT2 = 1.75V, VAUX = 0.5V, VINV = 0V, SP IVAC = 100μA, IBIAS = 100μA, CVCC = 10μF, CCOMP = 0.047μF, RHLD = 10kΩ. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Rising threshold 9.5 10.5 11.5 V Falling threshold 6.8 7.5 8.3 V Rising threshold 17.7 18.89 20.1 V Falling threshold 17.5 18.72 19.9 V INPUT SUPPLY (VCC) VCC(UVLO) Hysteresis VCC(OVP) 3 Hysteresis IVCC V 175 mV Startup current VCC = 6.7V, VINV = 0 V 180 μA Standby current VINV = 1.75V, VAUX = 1 V 1.6 mA Switching current CGATE = 1 nF 3.3 mA INPUT VOLTAGE FEEDFORWARD and ANGLE DETECTION (VAC, FF) VAC(CLAMP) VAC clamp voltage 1.24 V IVAC(ANGLE) Dimmer angle detect threshold Sweep IVAC 66 μA IVAC(HOLD) HOLD FET turn-on threshold Sweep IVAC, VFLT2 = 0 V 95 μA IFF Feedforward source current VGATE = VCC, IVAC = 100 µA 10 μA DIMMING DECODER CIRCUIT (FLT1, FLT2) FLT1(HIGH) FLT1 voltage high FLT1 open 1.67 1.75 1.83 V FLT2(MIN) Minimum dimming decode voltage VFLT2 falling 263 290 315 mV G(DECODE) Decode gain, VINV/VFLT2 FLT2HOLD(EN) HOLD circuit enable threshold VFLT2 falling 1 V FLT2HOLD(DIS) HOLD circuit disable threshold VFLT2 rising 1.2 V HOLD MOSFET on-resistance IVAC = 50 μA, VFLT2 = 1 V 24 Ω 0.877 HOLD CIRCUIT (HOLD) RDS(ON) PRE-REGULATOR GATE BIAS CIRCUIT (BIAS) BIAS(HIGH) BIAS high voltage clamp VCC < VCC(UVLO) 16.1 17.7 19.3 V BIAS(LOW) BIAS low voltage clamp VCC > VCC(UVLO) 12.3 13.5 14.7 V Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: LM3447 3 LM3447 SNOSC65 A – APRIL 2012 – REVISED MAY 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Unless otherwise specified –40°C < TJ = TA < 125°C, VCC = 14V, VTSNS = 1.75V, VFLT2 = 1.75V, VAUX = 0.5V, VINV = 0V, SP IVAC = 100μA, IBIAS = 100μA, CVCC = 10μF, CCOMP = 0.047μF, RHLD = 10kΩ. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 275 305 mV CURRENT SENSE COMPARATOR (ISNS) ISNS(TH) Current limit threshold RISNS(LEB) ISNS pull down impedance 239 1.13 kΩ tISNS(LEB) Leading edge blanking time 170 ns ERROR AMPLIFIER (INV, COMP) VREF Reference voltage VFLT2 = 1.5 V, VTSNS = 1.75 V IINV(BIAS) Input bias current VINV = VREF GM Transconductance VCOMP = VREF Current source capacity VINV = 0 V Current sink capacity VINV = 2V COMP(LOW) Minimum PWM ramp voltage IVAC = 110 μA, VINV = 1 V D(MAX) Maximum duty cycle IVAC = 110 μA, VINV = 0 V ICOMP 0.95 1 V nA 100 μmho 77 50 1.05 45 104 μA 77 μA 280 mV 76.5% VALLEY DETECT CIRCUIT (AUX) AUX(OVP) Overvoltage protection tAUX(LEB) AUX leading edge blanking VAUX rising IAUX(SOURCE) AUX source current VAUX = –0.3 V tAUX(TO) Valley detect timeout VAUX = 1 V 1.67 1.75 1.83 V 1.84 μs 207 μA 4 μs PWM OSCILLATOR AND FAULT TIMER tOSC Oscillator period tFAULT Fault timer 13.9 14.5 15.1 812 μs ms THERMAL FOLDBACK (TSNS) TSNS(OC) Open circuit voltage TSNS(TH) Thermal foldback threshold VTSNS falling RTSNS (1) Internal pull-up resistor TJ = 25°C 1.67 1.75 1.83 0.955 1 1.045 V V 7.09 7.88 8.67 kΩ THERMAL SHUTDOWN TSD(TH) (2) TSD(HYS) (2) (1) (2) 4 Thermal shutdown temperature Thermal shutdown hysteresis 165 °C 25 °C Resistance varies with junction temperature and has typical temperature coefficient of 25ppm/°C. Device performance at or near thermal shutdown temperature is not specified or assured. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: LM3447 LM3447 www.ti.com SNOSC65 A – APRIL 2012 – REVISED MAY 2012 DEVICE INFORMATION FUNCTIONAL BLOCK DIAGRAM 13 HOLD VAC 1 FF 5 FLT2 Input Voltage Sense and Feedforward Control Angle Decoding Circuit 4 ENHOLD Hold Enable FET Turn-on Logic Angle Detection Circuit ENHOLD Hold Enable Thermal Shutdown 3 Internal Regulators FLT1 11 VCC 1.75V Reference Generator 7.88k DISABLE VCC UVLO / OVP UVLO TSNS 2 INV 6 ENHOLD Hold Enable VREF + Error Amplifier COMP OVP Thermal Foldback PWM Comparator 7 Q R Q Logic and Control + 2.5V 280mV S 10 GATE + LEB ISNS 275mV 14 BIAS Triggered Ramp Generator 3.5V 9 13.5V Fault Timer 1.75V Valley Detection Circuit AUX 12 OVP 4.2V UVLO 8 LEB + 1.75V GND AUX OVP Comparator Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: LM3447 5 LM3447 SNOSC65 A – APRIL 2012 – REVISED MAY 2012 www.ti.com PIN CONFIGURATION TSSOP-14 PACKAGE (Top View) VAC 1 14 BIAS TSNS 2 13 HOLD FLT1 3 12 AUX FLT2 4 11 VCC FF 5 10 GATE INV 6 9 ISNS COMP 7 8 GND PIN FUNCTIONS NO. 6 NAME I/O DESCRIPTION 1 VAC I The current at this pin sets the input power level during normal operation. Connect through a resistor to rectified input line voltage. 2 TSNS I To implement thermal foldback, connect this pin to an external negative temperature coefficient (NTC) resistor. 3 FLT1 O This pin is the output of angle sense comparator. Connect a series resistor from this pin to a capacitor to ground to establish the low pass filter bandwidth. 4 FLT2 I Connect this pin to the output of low pass filter from FLT1 pin to enable dimming. This pin is an input to the internal dim decoder circuitry. For non-dimming applications connect this pin to TSNS. 5 FF O Connect a parallel resistor and capacitor from this pin to ground to filter twice the line frequency ripple. This is the output of the input voltage feedforward circuitry. 6 INV I This pin is the input of the internal Gm error amplifier. To implement primary side power regulation, connect this to the FF. To implement secondary side current regulation, connect this pin to the output of opto-isolator circuit. 7 COMP 8 GND 9 ISNS I Connect to the source of the switching MOSEFT and a resistor ground to sense transistor current. Overcurrent protection is engaged when the voltage exceeds 275mV threshold. 10 GATE O This output provides the gate drive for the power switching MOSEFT. 11 VCC 12 AUX 13 HOLD Connect to a holding resistor from the drain of the pre-regulator to this pin. The pin draws current during the zero crossings of the rectified input line voltage. 14 BIAS Connect to external pre-regulator transistor to enable startup. When VCC is below UVLO threshold the pin is clamped to 17.7V. After VCC crosses UVLO threshold the pin is clamped to 13.5V. I/O Output of the Gm error amplifier. Connect a capacitor to ground set desired integral loop compensation bandwidth. Ground return This is the input to the internal pre-regulator. Connect a bypass capacitor to ground. This pin enables and disables general functions of the LM3447 using the UVLO feature. Device enters overvoltage protection mode when the voltage is >18.9V. I This pin is used to sense the auxiliary winding voltage and perform valley switching operation. Overvoltage protection is engaged when the voltage exceeds the threshold of 1.75V during off time. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: LM3447 LM3447 www.ti.com SNOSC65 A – APRIL 2012 – REVISED MAY 2012 TYPICAL CHARACTERISTICS Unless otherwise stated, –40°C ≤ TA = TJ ≤ +125°C, VVCC = 14 V, VTSNS = 1.75V, VFLT2 = 1.75V, VAUX = 0.5V, VINV = 0V, IVAC = 100 μA, IBIAS = 100μA, CVCC = 10 μF, CCOMP = 0.047 μF 13 19.2 12 19.1 UVLO Rising 19 OVP Rising 10 VCC (V) VCC (V) 11 9 UVLO Falling 8 18.9 18.8 18.7 7 18.6 6 5 −40 −25 −10 5 20 35 50 65 Temperature (°C) 80 95 18.5 −40 −25 −10 110 125 20 35 50 65 Temperature (°C) 80 95 110 125 G002 Figure 2. VCC OVP vs. Junction Temperature 4 67.2 VCC Rising VCC Falling 3.5 66.8 3 IVAC(ANGLE) (µA) Bias Current (mA) 5 G001 Figure 1. VCC UVLO vs. Junction Temperature 2.5 2 1.5 66.4 66 65.6 65.2 1 64.8 0.5 0 OVP Falling 0 2 4 6 8 10 12 VCC (V) 14 16 18 64.4 −40 −25 −10 20 G004 Figure 3. Operational IVCC vs. VCC Voltage 5 20 35 50 65 Temperature (°C) 80 95 110 125 G005 Figure 4. Dimmer Angle Detect Threshold Current vs. Junction Temperature 96.2 −5 −10 95.8 −15 −20 IFF (µA) IVAC(HOLD) (µA) 95.4 95 94.6 −25 −30 −35 −40 94.2 −45 93.8 93.4 −40 −25 −10 −50 5 20 35 50 65 Temperature (°C) 80 95 110 125 −55 50 G006 Figure 5. Hold MOSFET Turn-on Threshold Current vs. Junction Temperature 100 150 200 250 300 350 400 450 500 550 IVAC (µA) G007 Figure 6. Feedforward Source Current (IFF) vs. VAC Current (IVAC) Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: LM3447 7 LM3447 SNOSC65 A – APRIL 2012 – REVISED MAY 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) Unless otherwise stated, –40°C ≤ TA = TJ ≤ +125°C, VVCC = 14 V, VTSNS = 1.75V, VFLT2 = 1.75V, VAUX = 0.5V, VINV = 0V, IVAC = 100 μA, IBIAS = 100μA, CVCC = 10 μF, CCOMP = 0.047 μF 20 275.6 19 275.4 BIAS High 275.2 ISNS(TH) (mV) VBIAS (V) 18 17 16 15 274.8 274.6 BIAS Low 14 275 274.4 13 12 −40 −25 −10 5 20 35 50 65 Temperature (°C) 80 95 274.2 −40 −25 −10 110 125 1.003 1.753 1.002 1.752 1.001 1.751 1.000 0.999 0.997 1.747 80 95 1.746 −40 −25 −10 110 125 110 125 G009 20 35 50 65 Temperature (°C) 80 95 110 125 G011 Figure 10. AUX OVP vs. Junction Temperature 14.7 1.753 14.65 1.752 1.751 TSNS(OC) (V) 14.6 tOSC (µs) 5 G010 Figure 9. VREF vs. Junction Temperature 14.55 14.5 1.75 1.749 1.748 14.45 1.747 14.4 −40 −25 −10 5 20 35 50 65 Temperature (°C) 80 95 110 125 1.746 −40 −25 −10 G012 Figure 11. Oscillator Period vs. Junction Temperature 8 95 1.749 1.748 20 35 50 65 Temperature (°C) 80 1.75 0.998 5 20 35 50 65 Temperature (°C) Figure 8. Current Limit Threshold vs. Junction Temperature AUX(OVP) (V) VREF (V) Figure 7. BIAS Clamp Voltage vs. Junction Temperature 0.996 −40 −25 −10 5 G008 5 20 35 50 65 Temperature (°C) 80 95 110 125 G013 Figure 12. TSNS Open Circuit Voltage vs. Junction Temperature Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: LM3447 LM3447 www.ti.com SNOSC65 A – APRIL 2012 – REVISED MAY 2012 TYPICAL CHARACTERISTICS (continued) Unless otherwise stated, –40°C ≤ TA = TJ ≤ +125°C, VVCC = 14 V, VTSNS = 1.75V, VFLT2 = 1.75V, VAUX = 0.5V, VINV = 0V, 1.002 7.98 1.0015 7.96 1.001 7.94 1.0005 7.92 RTSNS (kΩ) TSNS(TH) (V) IVAC = 100 μA, IBIAS = 100μA, CVCC = 10 μF, CCOMP = 0.047 μF 1 0.9995 7.9 7.88 0.999 7.86 0.9985 7.84 0.998 −40 −25 −10 5 20 35 50 65 Temperature (°C) 80 95 7.82 −40 −25 −10 110 125 5 20 35 50 65 Temperature (°C) G014 Figure 13. Thermal Foldback Thershold vs. Junction Temperature 80 95 110 125 G015 Figure 14. TSNS Internal Pull-up Resistor vs. Junction Temperature 120 18 115 15 Number of Units GM (µmho) 110 105 100 95 12 9 6 90 3 85 5 20 35 50 65 Temperature (°C) 80 95 0 110 125 9.6 9.635 9.67 9.705 9.74 9.775 9.81 9.845 9.88 9.915 9.95 9.985 10.02 10.055 10.09 10.125 10.16 10.195 10.23 10.265 10.3 80 −40 −25 −10 G016 Feedforward Source Current (µA) Figure 15. GM vs. Junction Temperature G017 Figure 16. Feedforward Source Current (IFF) Variation (IVAC=100µA, Temperautre = 25°C) Feedforward Source Current (µA) −9.98 −9.985 −9.99 −9.995 −10 −10.005 −10.01 −10.015 −10.02 −40 −25 −10 5 20 35 50 65 Temperature (°C) 80 95 110 125 G018 Figure 17. Feedforward Source Current (IFF) vs. Junction Temperature Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: LM3447 9 LM3447 SNOSC65 A – APRIL 2012 – REVISED MAY 2012 www.ti.com n:1 + RBS CPFC RAC PRI NP QPASS SEC NS – + – RO CBULK RHLD1 LM3447 VAC TSNS BIAS CFLT RAUX1 HOLD RHLD2 RNTC FLT1 AUX FLT2 VCC AUX NA RFLT FF GATE INV ISNS COMP GND RAUX2 QSW CFF CY1 RFF CVCC CCOMP RSN Figure 18. Typical Primary Side Power Regulated Flyback LED Driver APPLICATION INFORMATION DESCRIPTION LM3447 is an AC-DC power factor correction (PFC) controller for phase-cut dimmer compatible LED lighting applications. The device incorporates an innovative primary side input power regulation technique for controlling the LED light output over a wide input AC voltage and ambient temperature range. Operating LEDs with constant power allows the controller to compensates for the LED forward voltage variations caused by temperature modulation and LED aging. This also provides improved lamp lumen output maintenance and higher luminous efficacy. Smooth, flicker free LED dimming is performed by varying the power regulation set-point based on the dimmer phase angle. The device includes internal angle detection and decoding circuitry to accurately interpret the phase angle from a forward phase (leading edge) and reverse phase (trailing edge) based dimmers Power factor correction (PFC) with low input current total harmonic distortion (THD) is maintained by forcing discontinuous conduction mode (DCM) using a trimmed internal oscillator and valley detect circuitry. These features, along with LED open circuit and short circuit protection, LED thermal foldback and cycle-by-cycle FET overcurrent protection, make the LM3447 an ideal device for implementing a compact single stage isolated Flyback AC-DC LED driver for 5–30W power output range. In addition, it is also possible to configure LM3447 with minor modifications to control SEPIC and Cúk based dimmable AC-DC PFC LED drivers. In this datasheet, a discussion of the LM3447 functionality is presented using a typical Flyback LED driver circuit, as shown in Figure 18. 10 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: LM3447 LM3447 www.ti.com SNOSC65 A – APRIL 2012 – REVISED MAY 2012 VCC BIAS SUPPLY AND START-UP VREC(t) Rectified AC Line VREC PRI NP RBS + CPFC QPASS ± 17.7V 13.5V RHLD1 DZBS VBIAS VCC 10.5V 7.5V 14 RDAMP LM3447 BIAS VCC UVLO 13.5V VCC VCOMP CVCC 4.2V CCOMP 7 UVLO PWM COMP xxxxxxx xxxxxxx 11 GND AUX NA VGATE 8 VOUT GATE + 10 t0 (a) t1 t2 t3 (b) t4 time Figure 19. (a) Bias Circuit and (b) Typical Startup Waveforms The LM3447 is designed to achieve instant turn-on using an external linear regulator circuit, shown in Figure 19 (a). The start-up sequence is internally controlled by the BIAS voltage and VCC undervoltage lockout (UVLO) circuit and is illustrated in Figure 19 (b). The BIAS input is a low current voltage clamp circuit that provides a reference to the linear pass transistor, QPASS. The clamp circuit current is set by connecting resistor, RBS, between the input rectified AC voltage, VREC and BIAS. When power is applied, the BIAS voltage set to 17.7V and the capacitor, CVCC is rapidly charged by transistor QPASS. Resistor RHLD1 is used to limit the maximum allowable current, based on the safe operating area (SOA) rating of the transistor. The LM3447 starts operating when VCC exceeds the UVLO rising threshold of 10.5V, after which the BIAS voltage is reduced to 13.5V. The GATE drive output is enabled when the COMP voltage exceeds the minimum internal PWM ramp threshold of 280mV. As the output voltage, VOUT, increases, the bootstrap circuit based on an auxiliary winding of the transformer is energized and begins delivering power to the device. At any time, if VCC falls below 7.5V the device enters a UVLO state forcing BIAS to step back to 17.7V to initiate a new start-up sequence. The switching of BIAS voltage between two thresholds, 17.7V to 13.5V, is performed in association with a large VCC UVLO hysteresis of 3V to allow for a larger variation in auxiliary output voltage. The key waveforms illustrating the bias circuit operation and start-up sequence under dimming are shown in Figure 20. The impact of phase-cut dimming on BIAS, VOUT and VCC behavior is highlighted. The chopping of the input voltage by an external dimmer causes the output voltage, VOUT, to vary along with LED current. As VCC voltage tracks the output voltage, VOUT, it too fluctuates based on the dimming command. At low dimming levels, UVLO is engaged as VCC falls below 7.5V and the BIAS switches to 17.7V, initiating a start-up sequence. The BIAS behavior interacts with the external dimmer circuit, causing the device to enter into a re-start condition, where VCC fluctuates between UVLO high and low thresholds. With this mode of operation, the LM3447 is capable of providing quick response to any changes in the dimming command. In the case where the external dimmer is switched off, VCC is discharged and all of the device operation is ceased. A new start-up cycle is initiated, when the dimmer is switched on and the device responds in the manner illustrated in Figure 19 (b). Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: LM3447 11 LM3447 SNOSC65 A – APRIL 2012 – REVISED MAY 2012 www.ti.com VREC VBIAS 17.7V 13.5V VCC 10.5V 7.5V VOUT t0 t1 t2 t3 t4 t5 time Figure 20. Typical Waveforms and Start-up Sequence Under Dimming Conditions The value of capacitor CVCC is critical design parameter as it determines VCC ripple voltage during dimming operation. A X7R ceramic capacitor with value ranging from 22μF to 47μF and 25V voltage rating is recommended for CVCC as trade-off between size and performance in space constraint applications. At low dimming levels, large VCC voltage ripple and QPASS threshold voltage variations can intefere with smooth dimming performance. An external zener doide, DZBS, can be placed in series with BIAS to boost VCC voltage and eliminate any observable dimming discontinuities. A low power zener diode ( 200mW) with reverse breakdown voltage ranging from 1.8V to 4.5V is recommended for most dimming application. VCC OVERVOLTAGE PROTECTION LM3447 FAULT TIMER (812ms) VCC OVP VCC 11 CVCC LOGIC & CONTROL R Q S Q RDAMP 8 GND AUX NA GATE 10 Figure 21. VCC Overvoltage Protection Circuit The LM3447 has a built-in overvoltage protection (OVP) mode to protect VCC from exceeding its ABS MAX rating under fault conditions. The VCC voltage is monitored by a comparator with a rising threshold of 18.9V and 175mV of hysteresis. Upon detecting an overvoltage condition, GATE is pulled low for duration of 812ms, determined by the internal fault timer. On clearance of the fault, the timer is disabled and normal device operation resumes. An optional damping resistor, RDAMP in series with the auxiliary winding can be used to prevent transformer leakage current from peak charging CVCC and false triggering the OVP circuit. Based on the magnitude of leakage inductance a resistor of 10Ω to 47Ω should provide proper damping. 12 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: LM3447 LM3447 www.ti.com SNOSC65 A – APRIL 2012 – REVISED MAY 2012 POWER FACTOR CORRECTION VREC VSW IP IP t t IP(PK) IIN(AC) t IS t IS(PK) t TL 2TL DTS D2TS TS (a) Over line period, TL 2TS 3TS t (b) Over switching period, TS Figure 22. DCM Flyback PFC Waveforms Power factor correction is performed by operating the Flyback converter in discontinuous conduction mode (DCM). In this mode, the peak primary current, IP(PK) is given by v in (t) v (t) IP(PK) = REC DTS = DTS , for LM LM (1) vin (t) = VIN(PK) sin( 2p t), TL (2) where vIN(t) is the input voltage, vREC = ||vin|| is the rectified input voltage, LM is the transformer magnetizing inductance referred to the primary winding, D is the duty cycle, TS is the switching period and TL is the line period. For a fixed switching frequency controller, if duty cycle D, is held constant over a line cycle, then the peak primary current, IP(PK), varies in proportion to input voltage, vIN(t), as shown in Figure 22 (a). The resulting input current, IIN, is obtained by averaging the area under primary current, IP, shown in Figure 22 (b), 1 vin (t) 2 iin (t) = Average (IP ) = D TS , TS 2 LM (3) is sinusoidal and in-phase with input voltage, vIN(t). As a result, the DCM Flyback converter behaves much like a resistor and exhibits a power factor close to unity. The input power, PIN(AVG) drawn by the Flyback PFC is derived by averaging the product of input voltage, vin(t) and input current, iin(t), over half line cycle TL/2, TL PIN (AVG) 2 = TL TL 2 ò 2 vin (t) ´ iin (t)dt = TL 0 PIN(AVG) = 1 4 2 ò 2 2 1 VIN (PK)D TS 2 2p sin ( t)dt; 2 LM TL (4) 0 2 2 VIN(PK)D TS LM = 2 VIN(RMS) æ 2L ö M ç ÷ ç D2T ÷ è Sø = 2 VIN(RMS) Re ; Re = 2LM D 2TS , (5) The low frequency behavior of the DCM Flyback is defined by an effective resistance, Re. The expression for average input power is given by Equation 5 and is based on Re and the input RMS voltage VIN(RMS). For a single stage Flyback PFC driver, the output power, POUT, delivered to the LED load is a function of the converter efficiency, ηFLY, and is given by POUT = ηFLYPIN. (6) The average LED current through the string with forward voltage drop VLED = VOUT is Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: LM3447 13 LM3447 SNOSC65 A – APRIL 2012 – REVISED MAY 2012 ILED (AVG) = POUT (AVG) VOUT = η FLY www.ti.com PIN (AVG) VOUT = ηF LY 2 VIN (RM S) VOUT Re , (7) The LED current will have a ripple component varying at twice line frequency due to the PFC operation. The magnitude of the ripple component is based on the energy storage capacitor connected in parallel with the LED string at the output of Flyback PFC. In typical application, a low voltage aluminum electrolytic bulk capacitor is used as an energy storage device and is connected across the LED string to limit the ripple current within an acceptable range. INPUT POWER REGULATION AND INPUT VOLTAGE FEEDFORWARD CONTROL Using the LM3447, it is possible to regulate the LED current by implementing a control scheme using the duty cycle, D, as the control variable. The duty cycle is generated using an internal GM error-amplifier and a fixed frequency, triggered ramp generator, as shown in Figure 23. This technique should not be confused with other current mode control schemes where switch current, ISW, is used for control. With the LM3447, LED current can be directly controlled using a series sense resistor and a conventional closedloop feedback control scheme. Typically, for systems that need galvanic isolation between primary and secondary sides of the transformer, feedback control is complicated and expensive as it requires an additional signal processing amplifier and an opto-isolator. For improved luminous efficacy and simplicity, the LM3447 incorporates an innovative primary side input power regulation scheme based on input voltage feedforward control techniques. By commanding input power, the DCM Flyback PFC output is matched with the LED load characteristics to achieve indirect control of LED string current. The feedforward loop, consisting of input voltage sensing circuitry, the GM error amplifier and PWM comparator, is able to reject any input voltage disturbance by adjusting the duty cycle, thus achieving tight line regulation. VREC(t) + Rectified AC Line RAC – PRI NP LM INPUT VAC FEEDFORWARD INTERNAL REGULATORS VCC IFF = IVAC / 10 CVCC CTRL FF REFERENCE GENERATOR + INV RFF LOGIC & CONTROL VAL S Q R Q + CFF QSW GATE PWM COMP CCOMP RAMP LM3447 RSN VAL GND Figure 23. Feedforward Control Circuit The reference power level, PIN, for the LM3447, is set choosing resistors, RFF and RAC, based on the magnetizing inductance, LM, the internal reference voltage, VREF, the switching frequency, fS and the feedforward gain, GFF, such that p GFFVREF RFF = R AC 4 L MPIN fS (8) The feedforward gain, GFF = IVAC/IFF = 10 and internal reference voltage VREF = 1 V. 14 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: LM3447 LM3447 www.ti.com SNOSC65 A – APRIL 2012 – REVISED MAY 2012 For the above relationship to be valid and for PFC, it is necessary to ensure that the energy in the magnetizing inductor, LM, is reset every switching cycle and the power stage operates in DCM for the reference power level, PIN, over the entire range of input voltages. Based on this constraint, the transformer magnetizing inductor should be chosen as VR EF LM £ , 2 æ 1 ö 1 4PIN fS ç + ÷ ç nV VREC (PK,MIN ) ÷ è OUT ø (9) where n is the transformer primary to secondary turns-ratio, VOUT = VLED is the LED string voltage and VREC(PK,MIN) is the minimum peak rectified input voltage. For the LM3447 internal circuit implementation, shown in Figure 23, the reference voltage, VREF = 1V and the feedforward gain, GFF = 10. To ensure a robust design and to reject manufacturing variations, a margin of 2% to 10% should be provided when designing the transformer for magnetizing inductance calculated using Equation 9. A small capacitor, CFF is connected in parallel with the resistor RFF, to create a low pass filter that can attenuate twice the line frequency component from the sensed input voltage. It is recommended to set the filter pole frequency between 10–12Hz to provide 20dB attenuation, such that 1 , CFF ³ 2 p (10 Hz - 12 Hz)RFF (10) Slow integral compensation is achieved by placing a compensation capacitor CCOMP at the output of the GM amplifier. A capacitor value ranging from 4.7μF to 10μF is recommended to achieve a low bandwidth loop of 1Hz to 10Hz, based on the power level and transient response. AUX CIRCUIT AND VALLEY DETECT VSW IAUX IAUX VCC VALLEY DETECTION VAL RAUX1 AUX 4 s TIMER 1.84 s LEB + VAUX t VAL t VRAMP t RAUX2 1.75V RAMP 14.5 s RAMP CONTROL & LOGIC t RAMP OVP 812ms FAULT TIMER IP AUX NA VAL FLT2 ENHOLD + 1V GATE QSW TS LM3447 (a) 2TS t (b) Figure 24. (a) AUX Circuit; (b) Valley Switching Waveforms Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: LM3447 15 LM3447 SNOSC65 A – APRIL 2012 – REVISED MAY 2012 www.ti.com Valley switching is implemented by connecting the transformer auxiliary winding to the AUX input of LM3447 through a resistor divider network, RAUX1 and RAUX2, as shown in Figure 24 (a). The valley level is detected by monitoring the current sourced out of the AUX pin when the voltage at the auxiliary winding of the transformer is negative with respect to the GND node. The voltage at this node is clamped at approximately 100mV by the internal circuitry to protect the device during negative voltage excursions of the auxiliary winding. The waveforms in Figure 24(b) illustrate the sequence of events that have to occur for the LM3447 to initiate a new switching cycle. An internal 14.5μs timer is started at the same time as the switching FET (QSW) is turned on. This 14.5μs timer, set by the internal ramp rise time, is used to set the maximum frequency. After this timer expires the switching FET (QSW) is allowed to turn back on if a valley is detected (VAL) or the 4µs (tAUX(TO)) catch timer expires. The catch timer starts immediately after the Ramp signal drops and sets the lowest operating frequency. The particular valley (1st, 2nd …) in the ringing waveform, where the switch is enabled is a function of the input voltage and varies over the half line cycle. As a result, the AUX circuit shows increased sensitivity where the valley detect signal, VAL, overlaps the Ramp period. Here, the switching point is observed to randomly jump between two adjacent valleys, causing a discrete change in the switching period. Such perturbations in switching frequency cause the switching ripple component of the input current to increase and interfere with phase dimming performance. Therefore, valley switching is disabled and hard switching operation with fixed Ramp period is initiated on detection of external phase dimmers, as shown in Figure 25. The valley switching operation is controlled by the FLT2 input. The operation is disabled when the VFLT2 falls below 1V and is enabled again when it rises above 1.2V. A 200mV hysteresis is provided for noise immunity. A second function of AUX pin is to program the output overvoltage protection or open-LED detection feature. The output voltage is monitored by sampling the voltage at the auxiliary winding. The voltage is sampled after a fixed delay of 1.84μs, from the falling edge of the GATE drive signal. The leading edge blanking circuit helps reject the voltage transients caused by the leakage energy of the transformer thus preventing false tripping of OVP. The fault condition is detected when the AUX voltage exceeds the internal threshold, VAUX(OVP) (1.75V). In the case of an overvoltage fault, the switch is turned off for 812ms before attempting to restart the circuit. During this fault period, the compensation capacitor (CCOMP) is discharged, and the control loop is disabled. When the fault is cleared, the 812ms fault timer is disengaged and the control loop is activated to resume normal operation. VFLT2 1.2V 1V ENHOLD VRAMP VSW VGATE TS = TRAMP + 0.5TOSC TS = TRAMP time Figure 25. Waveforms Illustrating Valley Switching Enable and Disable Sequence The sizing of resistor RAUX1 and RAUX2 govern the AUX circuit behavior. Resistor RAUX1 is also used to limit the maximum source current from the AUX pin to 200μA and is based on the maximum input voltage and the transformer primary to auxiliary turns-ratio; 16 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: LM3447 LM3447 www.ti.com SNOSC65 A – APRIL 2012 – REVISED MAY 2012 R AUX1 = N A VR EC(PK ,MAX) NP 200 ´ 10- 6 , (11) Resistor RAUX2 is then selected to set the desired output overvoltage threshold, VOUT(OVP) based on the secondary to auxiliary turns-ratio æ ö ç ÷ 1.75 ÷R R AUX2 = ç AUX1, ç NA ÷ V 1.75 ç N OUT(OVP) ÷ è S ø (12) It is necessary to select the transformer’s secondary to auxiliary turns-ratio (NA/NS) to ensure that VAUX(OVP) is tripped before VCC(OVP). CURRENT SENSE AND OVERCURRENT PROTECTION n:1 + CPFC + ± PRI NP ± GATE LOGIC & CONTROL S Q R Q + 812ms FAULT TIMER OCP LM3447 170ns LEB SEC NS RO CBULK QSW ISNS 275mV RSN GND Figure 26. Current Sense Circuit The LM3447 provides switch overcurrent and LED short circuit protection by sensing the current through the switching transistor, QSW via a series connected sense resistor, RSN, as shown in Figure 26. At the beginning of each switching cycle, the Leading Edge Blanking (LEB) circuit pulls the ISNS input low for approximately 170ns. This prevents false tripping of the protection circuit due to voltage spikes caused by switch turn on transients. The cycle-by-cycle current limit is realized by comparing the sensed voltage at ISNS with the internal 275mV overcurrent protection threshold. When the sense voltage exceeds 275mV, the switch is immediately turned off for a duration of 812ms, set by the fault timer and the COMP capacitor, CCOMP is discharged. Under fault conditions, the LM3447 enters a hiccup mode, attempting to restart the circuit after a duration of 812ms. Upon clearance of the fault, normal operation resumes. The overcurrent limit is set by selecting the sense resistor, RSN. It is typical to limit the switch current to two times the maximum peak primary current, IP(PK,MAX), where IP(PK,MAX) = 2 PINTS LM , (13) Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: LM3447 17 LM3447 SNOSC65 A – APRIL 2012 – REVISED MAY 2012 www.ti.com and R SN = 275 ´ 10 -3 2IP(PK,MAX) (14) For RSN It is recommended to use a film type SMD resistor, with power rating greater than PSN and with low ESL. ANGLE DETECT CIRCUIT QPASS RHLD1 + RAC RBS ± RHLD2 VAC BIAS CURRENT MIRROR 10:1 VFLT2 1V 42k CHLD HOLD ENHOLD + 400mV + 1.75V FLT1 + RFLT CFLT 280mV VDIM VREF REFERENCE GENERATOR VTFB ANGLE DECODING CIRCUIT FLT2 LM3447 Figure 27. Phase Angle Detection and HOLD Current Circuit The LM3447 uses the input voltage, VREC, to detect the conduction phase angle. Figure 27 shows the LM3447 angle detect circuit, where the input voltage, VREC, is scaled by the current mirror circuits and re-generated across an internal 42kΩ resistor. This replica of the input voltage is compared with internal 280mV reference to obtain the conduction information. The resulting PWM signal, with its on-time proportional to the conduction period, is buffered and supplied through the FLT1 pin, as shown in Figure 28. To match the external phase dimmer characteristics with the LM3447 decoding circuit and prevent EMI filter capacitors from interfering with dimming operation, it is necessary to select an angle detection threshold, VADET(TH). This threshold can then be programmed using the resistor, RAC, such that VADET VADET R AC = = . IVAC(ANGLE) 66 ´ 10 -6 (15) For best results, set VADET(TH) as follows: • 25V to 40V for 120V systems • 50V to 80V for 230V systems Resistor RAC should also limit the VAC current under worst case operating conditions. The value of RAC should be optimized to meet both angle detect, VADET, and VAC current, IVAC constraints. 18 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: LM3447 LM3447 www.ti.com SNOSC65 A – APRIL 2012 – REVISED MAY 2012 HOLD CURRENT CIRCUIT The LM3447 incorporates an efficient hold current circuit to enhance compatibility with TRIAC based leading edge dimmers. Holding current from an external dimmer is drawn before the Flyback PFC circuit through the pass transistor, QPASS and limited by resistors RHLD1 and RHLD2, as shown in Figure 27. It should be noted that the additional current drawn has no effect on the rectified input voltage and therefore does not interfere with the input power regulation control scheme. VREC VHOLD(TH) VADET(TH) VFLT1 1.75V t VFLT2 t 1.2V 1V ENHOLD t IHOLD t t Figure 28. Angle Detection Circuit and Hold Current Circuit Operation To provide high efficiency, the hold circuit is enabled only when the presence of an external dimmer is detected based on the FLT2 input. The ENHOLD signal is asserted and hold operation is permitted when VFLT2 falls below 1V. The hold operation is halted when VFLT2 rises above 1.2V. During dimming, the hold current is drawn during the interval when rectified input voltage is below the VHOLD(TH), based on the external resistor RAC. The FET turnon is controlled by an internal comparator with a reference of 400mV (higher than angle detect reference), such that hold current is always asserted before angle detect threshold VADET(TH). The hold circuit operation is summarized in Figure 28. The hold trun-on threshold, VHOLD(TH) is given by VHOLD(TH) = R ACIVAC(HOLD) = 95 ´ 10 -6R AC. (16) The hold current is based on the BIAS voltage and set by the sum of resistors RHLD1 and RHLD2, 13.5 - VGS( PASS) IH OLD = . (RH LD1 + RH LD2 ) (17) In selecting the hold current level, it is critical to consider its impact on the average power dissipation and the operating junction temperature of pass transistor, QPASS under worst case operating conditions. The current should be limited to a safe value based on the pass transistor specifications or the ABS MAX rating of LM3447 (70mA). For best performance, it is recommended to set the hold current magnitude between 5mA and 20mA. A capacitor, CHLD of 2.2μF to 10μF, from RHLD2 to GND is connected to limit the rate of change of input current (diin/dt) caused by the step insertion of holding current. This prevents TRIAC based dimmers from misfiring at low dimming level. ANGLE DECODING CIRCUIT AND DIMMING The LM3447 incorporates a linear decoding circuit that translates the sensed conduction angle into an internal dimming command, VDIM. The conduction angle information, represented by the PWM signal at FLT1 output, is processed by an external low pass filter consisting of resistor, RFLT and capacitor, CFLT, which attenuates the twice line frequency component from the signal. The resulting analog signal at FLT2 is converted into the dimming command by a linear analog processing circuit. The piecewise linear relationship between the FLT2 input and the dimming command is shown graphically in Figure 29. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: LM3447 19 LM3447 SNOSC65 A – APRIL 2012 – REVISED MAY 2012 www.ti.com The dimming command, VDIM is • held constant at 1V for VFLT2 ranging from 1.75V to 1.45V (conduction angle 180° to 150°) • linearly varied with gain of 0.877 for VFLT2 ranging from 1.45V to 280mV (conduction angle 150° to 30°) • saturated at 13mV for VFLT2 lower than 280mV (conduction angle less than 30°) 1.2 Dimming Command, VDIM - V 1 0.8 0.6 0.4 0.2 0 0 0.3 0.6 0.9 1.2 FLT 2 Voltage, VFLT2 - V 1.5 1.8 Figure 29. Relationship Between VFLT2 and VDIM The relationship implemented by the angle decoding circuit is designed to map the non-linear power behavior of external phase dimmer circuits and enhance Flyback PFC power stage compatibility. Under normal operating conditions, the dimming command, VDIM is translated into a reference voltage, VREF, where VREF = VDIM. As dimming progresses, the input power commanded by the feedforward loop is modulated in accordance with VREF. This causes the output power and hence the LED current to vary based on the input conduction angle. Using this feedforward control scheme and the internal angle decoding circuit of the LM3447, it is possible to achieve monotonic, smooth and flicker free dimming with a dimming ratio of more than 50:1. THERMAL FOLDBACK CIRCUIT Thermal protection is necessary to prevent the LEDs and other power supply components from sustaining damage when operated at elevated ambient temperatures. A thermal foldback circuit is incorporated into the LM3447 to limit the maximum operating temperature of the LEDs by scaling the output power based on the heatsink temperature. The LED temperature is sensed using an external NTC resistor, RNTC, connected between the TSNS pin and GND, as shown in Figure 30(a). The thermal protection is engaged when the TSNS voltage decreases below the thermal foldback threshold voltage, VTSNS(TH), of 1V. The power is scaled by adjusting the reference voltage, VREF, based on the thermal foldback output voltage, VTFB, according to the relationship shown in Figure 30(b). The resistor value, RNTC(BK), at which the device enters thermal protection is fixed by the internal 7.88kΩ pull-up resistor and the TSNS reference voltage, VTSNS(REF) and is given by 7.88 kΩ RNTC = = 10.5 kΩ VTSNS(REF) - VTSNS(TH) (18) The temperature break-point, TBK and rate-of-change (slope) are governed by the non-linear characteristics of the NTC resistor, RNTC, given by its β-value. To achieve a break-point temperature, TBK, the NTC resistor, RNTC should selected as RNT C(BK) . RN TC (To ) = é æ 1 1 öù exp êβ ç ÷ú To øûú ëê è TBK (19) 20 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: LM3447 LM3447 www.ti.com SNOSC65 A – APRIL 2012 – REVISED MAY 2012 where, To is the room temperature in Kelvin, and RNTC(To) is the NTC value at room temperature. A temperature break-point ranging from 70°C (343K) to 90°C (363K) can be achieved by selecting an NTC resistance ranging from 100kΩ to 220kΩ and β-value of 3500K to 4500K. 1.2 Reference Voltage, VREF - V 1 0.8 0.6 0.4 0.2 (a) Circuit 0 0 0.3 0.6 0.9 1.2 1.5 Thermal Foldback Voltage, VTFB - V 1.8 (b) Relationship between VTSNS and VREF Figure 30. Thermal Foldback The precedence between the thermal foldback input, VTFB and the dimming input, VDIM, is decided by the reference generator circuit. This allows dimming operation to be performed when thermal protection is engaged. Dimming operation is allowed when the input power demanded by the decoder circuit, VDIM, is lower than the maximum power limit set by the thermal protection circuit, VTFB. This feature provides optimal lamp utilization under adverse operating conditions. OUTPUT BULK CAPACITOR The output bulk capacitor, CBULK, is required to store energy during the input voltage zero crossing interval and limit twice the line frequency ripple component flowing through the LEDs. The value of output capacitor is given by PI N CBU LK ³ , 2 p fL RLED VOUTILED(R IP) (20) where, RLED is the dynamic resistance of LED string, ILED(RIP) is the average to peak LED ripple current and fL is line frequency. In typical applications, the solution size becomes a limiting factor and dictates the maximum dimensions of the bulk capacitor. When selecting an electrolytic capacitor, manufacturer recommended de-rating factors should be applied based on the worst case capacitor ripple current, output voltage and operating temperature to achieve the desired operating lifetime. It is essential to provide a minimum load at the output of the PFC to discharge the capacitor after the power is switched off or during LED open circuit failures. A 20kΩ resistor, RO, is recommended for best performance. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: LM3447 21 LM3447 SNOSC65 A – APRIL 2012 – REVISED MAY 2012 www.ti.com DESIGN PROCEDURE (1) (2) STEP VARIABLE 1 PIN DESCRIPTION PIN = VOUT ILED η FLY where VOUT = VLED = Typical LED string voltage, ILED is the average LED current, ηTOT = ηEMI × ηFLY, ηTOT is the LED driver efficiency, ηEMI is the EMI input filter efficiency and ηFLY is the Flyback PFC efficiency. 2 DMAX 3 n:1 0.4 < DMAX < 0.5 where DMAX is the maximum allowable Flyback PFC duty cycle DM A X VREC(P K, MI N) 1 - D MA X VOUT n= , VSW = nVOUT + VREC(PK,MAX) + VOS and VSW < Maximum FET (Q1) breakdown voltage. where n is the transformer turns-ratio, VREC(PK,MIN) is the minimum peak rectified input voltage, VREC(PK,MAX) is the maximum peak rectified input voltage, VIN(RMS,MIN) is the minimum input RMS voltage, VIN(RMS,MAX) is the maximum input RMS voltage, VSW is the switch drain to source voltage, VOS is the overshoot voltage because of leakage inductance. 4 LM LM £ VRE F æ 1 ö 1 4PI N fS ç + ÷ è nVOUT VRE C(P K ,M IN) ø 2 , where VREF is the internal reference voltage; VREF = 1V, fS is the fixed switching frequency; fS = 70 kHz. 5 IP(PK,MAX) IP(PK,MAX) = 2 PIN TS , LM where TS is the switching period, TS = 1/fS 8 NP, NA, NS Transformer Design • • Core geometry (EE, PQ, RM) Bobbin (UL Class B or Class F) LM is the magnetizing inductance referred to primary side n:1 = NP:NS, primary to secondary winding turns-ratio NA = VCC VOUT NS , where NA is the auxiliary winding turns BMAX < 0.3T, where BMAX is the maximum operating flux density corresponding to IP(PK,MAX) (1) (2) 22 See the Electrical Characteristics Table for all constants and measured values, unless otherwise noted. See Figure 18 for all component locations in the Design Procedure Table. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: LM3447 LM3447 www.ti.com SNOSC65 A – APRIL 2012 – REVISED MAY 2012 STEP VARIABLE 6 RAC DESCRIPTION VA DET R AC = IV A C(A NGLE ) where VADET is the angle detection voltage; • • 25V to 40V for 120V system 50V to 80V for 230V system IVAC(ANGLE) is the angle detection threshold, and 7 RFF RFF = VR EC(PK,M AX) R AC p GFF VREF 4 £ 500 μA RAC , L MPINfS where GFF is the gain of Feedforward circuit; GFF = 10. 8 CFF 9 CCOMP 10 QPASS, RHLD1 1 , 2p (10 Hz - 12 Hz)RFF CFF £ 4.7μF ≤ CCOMP ≤ 10μF VDS (PA S S) = 1.2 VRE C(PK , MA X) , VB IA S (HI G) - VGS (PA S S) R HLD1 = , IS OA (PA SS ) where VGS(PASS) is the drain to source withstand voltage of pass transistor, QPASS, ISOA(PASS) is the maximum current through pass transistor based on safe operating area characteristics. 11 RBS RB S = VRE C(P K ,M AX ) IB IA S where, IBIAS is the BIAS current and IBIAS ≤ 500 μA 12 RAUX1, RAUX2 R AUX1 = NA VREC(PK,MAX) NP 200 ´ 10 -6 , æ ö ç ÷ 1.75 R AUX2 = ç ÷R AUX1 , ç NA V ÷ ç N OUT(OVP) - 1.75 ÷ è S ø where, VOUT(OVP) is the maximum output voltage under OVP condition 13 RSN 14 RFLT, CFLT 15 RHOLD R SN = 275 ´ 10 -3 2IP(PK,MAX) RFLT = 280 kΩ, CFLT = 0.1 μF R HLD2 = 13.5 - VGS(P A SS ) IHO LD - R HLD1 where, IHOLD is the holding current drawn through the external phase dimmer circuit Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: LM3447 23 LM3447 SNOSC65 A – APRIL 2012 – REVISED MAY 2012 STEP VARIABLE 16 RNTC www.ti.com DESCRIPTION RNTC(T ) = o RNTC(BK) é æ 1 1 öù exp êβ ç ÷ú ë è TBK To ø û , where, RNTC(BK) = 10.5 kΩ, is the fixed break point resistance, TBK is the break point temperature in Kelvin, TO is the room temperature in Kelvin, RNTC(To) is the manufacturer specified NTC resistance at room temperature, β is the NTC resistor characteristics specified by the manufacturer. 17 CBULK, RO CB ULK £ PI N , 2 p fL R LE D VOUT ILED(RI P) where, ILED(RIP) is the average to peak magnitude of twice the line frequency current ripple through LED, RLED is the dynamic resistance of the LED string, fL is the line frequency RO = 20 kΩ, is the recommended bleeder resistance Spacer REVISION HISTORY Changes from Original (April 2012) to Revision A • 24 Page Changed the device From: Product Preview To: Production ...................................................................................... 1 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: LM3447 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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