TI TPS65281

TPS65281, TPS65281-1
www.ti.com
SLVSBH7B – JULY 2012 – REVISED DECEMBER 2012
PRECISION ADJUSTABLE CURRENT LIMITED POWER DISTRIBUTION SWITCH WITH 4.5V
TO 18V INPUT VOLTAGE, 3A OUTPUT CURRENT SYNCHRONOUS BUCK REGULATOR
Check for Samples: TPS65281, TPS65281-1
FEATURES
1
INTEGRATED POWER DISTRIBUTION SWITCH
•
•
•
•
•
•
•
•
Operating Input Voltage Range: 2.5 V to 6.5 V
Adjustable Current Limit:
75 mA - 2.7 A (typical)
±6% Current-Limit Accuracy at 1.7 A (typical)
Over Current Latch-Off Protection (TPS65281)
and Over Current Auto-Recovery (TPS65281-1)
Reverse Input-Output Voltage Protection
Built-In Soft-Start
Integrated Back-to-Back Power MOSFETs With
100-mΩ On-Resistance
Over Temperature Protection
xxx
xxx
xxx
xxx
xxx
xxx
xxx
xxx
xxx
•
•
•
•
•
•
•
•
INTEGRATED BUCK CONVERTER
Wide Input Voltage Range: 4.5 V to 18 V
Maximum Continuous 3-A Output Current
Feedback Reference Voltage: 0.8 V ±1 %
Adjustable 300-kHz to 1.4-MHz Switching
Frequency
Adjustable Soft Start and Tracking With
Built-In 1-ms Internal Soft-Start Time
Cycle-by-Cycle Current Limit
Output Over-voltage Protection
16-Lead QFN (RGV) 4-mm x 4-mm Package
APPLICATIONS
•
•
•
•
•
USB Ports and Hubs
Digital TV
Set-Top Boxes
VOIP Phones
Tablet PC
DESCRIPTION/ORDERING INFORMATION
The TPS65281/TPS65281-1 incorporates an N-channel back-to-back power MOSFET switch and a monolithic
buck converter. The device is intended to provide a total power distribution solution for digital TV, set-top boxes,
tablet PC and VOIP phones etc applications, where precision current limiting is required or heavy capacitive load
or short circuit are encountered.
A 100-mΩ independent power distribution switch limits the output current to a programmable current limit
threshold between typical 75 mA and 2.7 A by using an external resistor. The current limit accauracy as tight as
±6% can be achieved at higher current limit setting. TPS65281 provides circuit breaker functionality by latching
off the power switch during over-current or reverse-voltage situations. TPS65281-1 limits output current to a safe
level by using a constant current mode when the output load exceeds the current limit threshold. An internal
reverse-voltage comparator disables the power switch when the output voltage is driven higher than the input to
protect the device on the input side of the switch in normal operation. The nFAULT output asserts low under
over-current and reverse-voltage conditions. Back-to-back power MOSFETs structure prevents the reverse
current injection from an active load at output port during shutdown of power switch.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012, Texas Instruments Incorporated
TPS65281, TPS65281-1
SLVSBH7B – JULY 2012 – REVISED DECEMBER 2012
www.ti.com
The buck DC/DC converter integrates power MOSFETs for optimized power efficiency and reduced external
component count. A wide 4.5-V to 18-V input supply range to buck encompasses most intermediate bus voltages
operating off 5-V, 9-V, 12-V or 15-V power bus. Constant frequency peak current mode control simplifies the
compensation and provides fast transient response. The buck can be precisely sequenced and ramp up in order
to align with other rails in the system with the soft-start pin. With SS pin floating, the built-in 1ms soft-start time
prevents in-rush current. Cycle-by-cycle over current protection and hiccup operation limit MOSFET power
dissipation in short circuit or over loading fault conditions. The switching frequency of the converter can be
programmed from 300 kHz to 1.4 MHz with an external resistor at ROSC pin. With ROSC pin connecting to V7V
pin, floating, or grounding, a default fixed switching frequency can be selected to reduce an external resistor.
The TPS65281/TPS65281-1 is available in a 16-lead thermally enhanced QFN (RGV) 4-mm x 4-mm thin
package.
ORDERING INFORMATION (1)
TA
PACKAGE
(2)
ORDERABLE PART NUMBER
TPS65281RGVR
–40°C to 85°C
16-Pin QFN (RGV)
TPS65281RGVT
TPS65281-1RGVR
TPS65281-1RGVT
(1)
(2)
2
TOP-SIDE MARKING
TPS65281
TPS65281-1
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
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SLVSBH7B – JULY 2012 – REVISED DECEMBER 2012
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
TYPICAL APPLICATION
C7
47nF
L1
4.7uH
+5V
C6
4.7nF
R3
40.2kΩ
C5
22uF
13
14
9
10
SW_IN
C4
10uF
7
AGND
VIN
USB Data
8
USB
Port
TPS65281
EN
EN_SW
6
USB fault signal
5
RLIM
USB control signal
4
1
2
SS
16
nFAULT
ROSC
C2
1uF
V7V
3
15
Enable
R5
100kΩ
SW_OUT
PGND
COMP
VIN
6V~18V
C1
10uF
FB
BST
LX
11
12
R4
7.68kΩ
C3
4.7nF
R2
20kΩ
R1
10kΩ
Figure 1. 12-V Power Bus
L1
4.7uH
C7
47nF
+3.3V
C6
4.7nF
R3
40.2kΩ
C5
22uF
13
9
SW_IN
11
10
FB
R5
100kΩ
SW_OUT
8
AGND
7
C1
10uF
14
VIN
USB Data
C4
10uF
USB
Port
TPS65281
EN_SW
5
USB fault signal
USB control signal
4
1
C3
4.7nF
6
RLIM
EN
ROSC
nFAULT
3
16
V7V
SS
C2
1uF
COMP
15
Enable
PGND
2
VIN
5V
LX
BST
12
R4
12.7kΩ
R2
20kΩ
R1
10kΩ
Figure 2. 5-V Power Bus
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SLVSBH7B – JULY 2012 – REVISED DECEMBER 2012
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FUNCTION BLOCK DIAGRAM
V7V
15
14
LDO
5V
VIN
Voltage Reference
Current Bias
Preregulator
HS current sensing
1 .25 M
CS
12
1 .25 M
EN
BST
16
enable buffer
HS driver
Current Sensing
(0 .1 V/A)
COMP
FB
11
Buck
Controller
2
PWM comparator
LX
V7V
slope
comp
10
LS driver
0 .8 V
SS
1
error amplifer
CS
LS current sensing
V7 V
10 uA
ROSC
SW_IN
3
1 ms
Internal
Soft Start
13
Oscillotor
BUCK
POWER SWITCH
9
PGND
7
AGND
UVLO
POR
reverse voltage
comparator
8
CS
SW_OUT
current sensing
Charge
Pump
1. 25M
4 ms Degl .
Time
Driver
Current
Limit
1. 25M
EN_SW
5
4
6
RLIM
nFAULT
10ms Degl .
Time
enable buffer
4
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SLVSBH7B – JULY 2012 – REVISED DECEMBER 2012
PIN OUT
RGV PACKAGE
(TOP VIEW)
BST
LX
FB
SW_IN
12
11
10
9
PGND 13
8 SW_OUT
VIN 14
7 AGND
Thermal Pad
1
2
3
4
RLIM
5 EN_SW
ROSC
EN 16
COMP
6 nFAULT
SS
V7V 15
Exposed thermal pad must be soldered to PCB for optimal thermal performance.
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TERMINAL FUNCTIONS
NAME
NO.
DESCRIPTION
SS
1
Soft-start and tracking input for buck converter. An internal 5-µA current source is connected to this pin. An
external soft-start can be programmed by connecting a capacitor between this pin and ground. Leave the pin
floating to have a default 1-ms of soft-start time. This pin allows the start-up of buck output to track an
external voltage using an external resistor divider at this pin.
COMP
2
Error amplifier output and Loop compensation pin for buck. Connect a series RC to compensate the control
loop of buck converter.
ROSC
3
Oscillator clock frequency control pin. Connect the pin to ground for a fixed 300-kHz switching frequency.
Connect the pin to V7V or float the pin for a fixed 600-kHz switching frequency. Other switch frequencies
between 300 kHz to 1.4 MHz can be programmed using a resistor connected from this pin to ground. A
internal 10-µA pull-up current develops a voltage to be used in oscillator. Directly applying the voltage to the
ROSC pin can linearly adjust the switching frequency.
RLIM
4
Power switch current limit control pin. An external resistor used to set current limit threshold of power switch.
Recommended 15 kΩ ≤ RLIM ≤ 232 kΩ.
EN_SW
5
Enable pin of power switch. Logic high turns on power switch. Forcing the pin below 0.4 V shuts down power
switch. Not recommend floating this pin, though there is a 2.5-MΩ pull-up resistor connecting this pin.
nFAULT
6
Active low open drain output, asserted in conditions when over-current happens for more than 10 ms or
reverse-voltage of power switch for more than 4 ms.
AGND
7
Analog ground common to buck controller and power switch controller. It must be routed separately from
high current power grounds to the (-) terminal of bypass capacitor of internal V7V LDO output.
SW_OUT
8
Power switch output pin
SW_IN
9
Power switch input pin
FB
10
Feedback sensing pin for buck output voltage. Connect this pin to the resistor divider of buck output. The
feedback reference voltage is 0.8 V±1%.
LX
11
Switching node connection to the internal power FETs, inductor and bootstrap capacitor for buck converter.
The voltage swing at this pin is from a diode voltage below the ground up to VIN voltage.
BST
12
Bootstrapped supply to the high side floating gate driver in buck converter. Connect a capacitor (recommend
47 nF) from BST pin to LX pin.
PGND
13
Power ground connection. Connect PGND pin as close as practical to the (-) terminal of input ceramic
capacitor.
VIN
14
Input power supply for buck. Connect VIN pin as close as practical to the (+) terminal of a input ceramic
capacitor (suggest 10 µF).
V7V
15
Internal LDO output. The internal gate driver for low side power MOSFET and control cirduits are powered
from this voltage. Decouple this pin to power ground with a minimum 1-µF ceramic capacitor. The output
voltage level of LDO is regulated to typical 6.3 V for optimal conduction on-resistances of internal power
MOSFETs.
EN
16
Enable for buck converter and the device. Logic high enables buck converter and bias supply to power
switches. Forcing the pin below 0.4 V shuts down the entire device, reducing the quiescent current to
approximate typical 7 µA. Not recommend floating this pin. The device can be automatically started up with
connecting EN pin to VIN though a 10 kΩ resistor.
Power PAD
6
Exposed pad beneath the IC. Connect to the ground. Always solder power pad to the board, and have as
many thermal vias as possible on the PCB to enhance power dissipation. There is no ground or any other
electric signal downbonded to the pad inside the IC package.
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SLVSBH7B – JULY 2012 – REVISED DECEMBER 2012
ABSOLUTE MAXIMUM RATINGS
(1)
over operating free-air temperature range (unless otherwise noted)
VIN
–0.3 to 18
V
LX (Maximum withstand voltage transient < 20ns)
–1.0 to 18
V
BST referenced to LX pin
–0.3 to 7
V
SW_IN, SW_OUT
–0.3 to 7
V
EN, EN_SW, nFAULT, V7V, ROSC, RLIM
–0.3 to 7
V
SS, COMP, FB
–0.3 to 3.6
V
AGND, PGND
–0.3 to 0.3
V
TJ
Operating virtual junction temperature range
–40 to 125
°C
TSTG
Storage temperature range
–55 to 150
°C
(1)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VIN
Input operating voltage
4.5
18
V
TA
Ambient temperature
–40
85
°C
ELECTROSTATIC DISCHARGE (ESD) PROTECTION (1)
MIN
Human body model (HBM)
MAX
UNIT
4000
V
Charge device model (CDM)
500
V
Machine model (MM)
200
V
(1)
SW_OUT pin human body model (HBM) ESD protection rating 4 kV, and machine model (MM) rating 200V.
THERMAL INFORMATION
TPS65281/TPS65281-1
THERMAL METRIC (1)
RGV
UNITS
16 PINS
θJA
Junction-to-ambient thermal resistance (2)
36.5
θJCtop
Junction-to-case (top) thermal resistance (3)
42.7
θJB
Junction-to-board thermal resistance (4)
14.7
ψJT
Junction-to-top characterization parameter (5)
0.5
ψJB
Junction-to-board characterization parameter (6)
14.8
θJCbot
Junction-to-case (bottom) thermal resistance (7)
3.3
(1)
(2)
(3)
(4)
(5)
(6)
(7)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
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ELECTRICAL CHARACTERISTICS
TJ = 25°C, VIN = 12 V, fSW = 600 kHz, RnFAULT = 100 kΩ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT SUPPLY
VIN
Input voltage range
IDDSDN
Shutdown supply current
EN = EN_SW = low
4.5
IDDQ_NSW
Switching quiescent current with no load at
DCDC output
EN = high, EN_SW = low, FB = 6 V
With Buck not switching
0.8
mA
IDDQ_SW
Switching quiescent current with no load at
DCDC output, Buck switching
EN = high, EN_SW = low, FB = 5 V
With Buck switching
13
mA
UVLO
VIN under voltage lockout
7
V
20
µA
Rising VIN
4.10
4.30
4.50
Falling VIN
3.85
4.10
4.35
V
6.47
V
1400
kHz
Hysteresis
V7V
18
0.2
Internal biasing supply
V7V load current = 0 A,
VIN = 12 V
6.17
Switching frequency range
Set by external resistor ROSC
300
6.32
OSCILLATOR
fSW_BK
fSW
Programmable frequency
ROSC = 51 kΩ
510
ROSC = 140 kΩ
1400
ROSC floating or connected to V7V
600
ROSC connected to ground
270
kHz
BUCK CONVERTER
VCOMP = 1.2 V, TJ = 25°C
0.792
0.8
0.808
VCOMP = 1.2 V, TJ = -40°C to 125°C
0.784
0.8
0.816
VFB
Feedback voltage
VLINEREG
Line regulation - DC
IOUT = 2 A
0.5
%/V
VLOADREG
Load regulation - DC
IOUT = 0.3 A - 2.7 A
0.5
%/A
Gm_EA
Error amplifier trans-conductance (1)
-2 µA < ICOMP < 2 µA
500
µs
Gm_SRC
COMP voltage to inductor current Gm (1)
ILX = 0.5 A
20
A/V
VENH
EN high level input voltage
VENL
EN low level input voltage
ISS
Soft-start charging current
tSS_INT
Internal soft-start time
ILIMIT
Buck peak inductor current limit
Rdson_HS
On resistance of high side FET in buck
Rdson_LS
On resistance of low side FET in buck
2
V
0.4
4.7
SS pin open
0.5
V
1
V
µA
1.5
ms
4
A
V7V = 6.3 V, with bond wire resistance
90
mΩ
VIN = 12 V, with bond wire resistance
70
mΩ
POWER DISTRIBUTION SWITCH
VSW_IN
Power switch input voltage range
VUVLO_SW
RDSON_SW
2.5
Input under-voltage lock out
Power switch NDMOS on-resistance
tD_on
Turn-on delay time from EN_SW turns high
tD_off
Turn-off delay time from EN_SW turns low
tr
Output rise time
tf
Output fall time
IOS
Current limit threshold (maximum DC current
delivered to load) and short circuit current,
SW_OUT connect to ground
tIOS
Response time to short circuit
(1)
8
6
V
VSW_IN rising
2.15
2.25
2.35
V
VSW_IN falling
2.08
2.13
2.28
Hysteresis
120
VSW_IN = 5 V, ISW_OUT = 0.5 A, including bond
wire resistance
100
VSW_IN = 2.5 V, ISW_OUT = 0.5 A, includes bond
wire resistance
100
mΩ
VSW_IN = 5 V, CL = 22 µF, RL = 100 Ω
(see Figure 3)
1.4
2
ms
1.2
2
ms
1.3
1.5
ms
5
10
ms
RLIM = 14.3 kΩ
1.65
1.76
1.87
RLIM = 20 kΩ
1.18
1.26
1.34
RLIM = 50 kΩ
0.47
0.5
0.53
RLIM shorted to SW_IN or open
1.12
1.2
1.28
VSW_IN = 5 V
V
mV
2
A
us
Specified by design.
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SLVSBH7B – JULY 2012 – REVISED DECEMBER 2012
ELECTRICAL CHARACTERISTICS (continued)
TJ = 25°C, VIN = 12 V, fSW = 600 kHz, RnFAULT = 100 kΩ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tDEGLITCH(OCP)
Switch over current fault deglitch
Fault assertion or de-assertion due to overcurrent condition
VL_nFAULT
nFAULT pin output low voltage
InFAULT = 1 mA
VEN_SWH
EN_SW high level input voltage
EN_SW high level input voltage
VEN_SWL
EN_SW high level input voltage
EN_SW low level input voltage
RDIS
Discharge resistance
VSW_IN = 5 V, EN_SW = 0 V
MIN
TYP
MAX
7
10
13
80
UNIT
ms
mV
2
V
0.4
100
V
Ω
THERMAL SHUTDOWN
TTRIP_BUCK
Thermal protection trip point
THYST_BUCK
Thermal protection hysteresis
Rising temperature
TTRIP_SW
Power switch thermal protection trip point in
current limit (TPS65281-1 only)
THYST_SW
160
Rising temperature
Hysteresis
50%
50%
tD_on tr
tD_off tf
°C
20
°C
145
°C
10
°C
VEN_SWx
90%
VOUT_SWx
10%
90%
10%
Figure 3. Power Switches Test Circuit and Voltage Waveforms
Figure 4. Response Time to Short Circuit Waveform
Figure 5. Output Voltage vs Current Limit Threshold
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TYPICAL CHARACTERISTICS
TJ = 25°C, VIN = 12 V, fSW = 600 kHz, RnFAULT = 100 kΩ (unless otherwise noted)
Vout_Buck
Vout_Buck
EN
EN
nFAULT
SW_OUT
nFAULT
SW_OUT
Figure 6. Power Up by EN Pin
Figure 7. Power Down by EN Pin
Vout_Buck
Vout_Buck
EN
EN
nFAULT
nFAULT
SW_OUT
SW_OUT
Figure 8. Power Up by VIN
(EN pin connects to VIN with a 10-kΩ resistor)
Figure 9. Power Down by VIN
Iout _Buck
Vout_Buck
Vout_Buck
LX
Figure 10. VOUT Ripple and LX
10
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Figure 11. Load Transient
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SLVSBH7B – JULY 2012 – REVISED DECEMBER 2012
TYPICAL CHARACTERISTICS (continued)
TJ = 25°C, VIN = 12 V, fSW = 600 kHz, RnFAULT = 100 kΩ (unless otherwise noted)
5.1
5.08
Output Voltage (V)
5.06
5.04
5.02
5
4.98
4.96
4.94
4.92
4.9
5
7
9
11
13
15
17
19
Input Voltage (V)
Figure 12. Buck Load Regulation
Figure 13. Buck Line Regulation
2
1.8
1.6
Frequency (MHz)
1.4
1.2
1
0.8
0.6
0.4
0.2
0
0.00
50.00
100.00
150.00
200.00
250.00
Rosc (kW)
Figure 14. Oscillator Frequency vs Rosc Voltage
Figure 15. Buck Efficiency
Vout_Buck
LX
SS
IL
IL
Figure 16. Buck Hiccup Response to Hard-Short Circuit
Figure 17. Zoom In Buck Output Hard Short Response
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TYPICAL CHARACTERISTICS (continued)
TJ = 25°C, VIN = 12 V, fSW = 600 kHz, RnFAULT = 100 kΩ (unless otherwise noted)
Vout_Buck
Vout_Buck
EN_SW
EN_SW
nFAULT
nFAULT
SW_OUT
SW_OUT
Figure 18. Power Switch Turn On Delay and Rise Time
Figure 19. Power Switch Turn Off Delay and Fall Time
Vout_Buck
ISW _OUT
nFAULT
EN_SW
SW_OUT
nFAULT
ISW_OUT
SW_OUT
Figure 20. Power Switch Hard Short
(Latch Off Version)
Figure 21. Power Switch Starts up to Short Circuit
(Latch Off Version)
EN_SW
nFAULT
ISW _OUT
Vout_Buck
ISW _OUT
SW_OUT
nFAULT
SW_OUT
Figure 22. Power Switch No Load to 2-Ω Resistor
(Latch Off Version)
12
Figure 23. Power Switch Response Time (TIOS) to Output
Hard Short
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SLVSBH7B – JULY 2012 – REVISED DECEMBER 2012
TYPICAL CHARACTERISTICS (continued)
TJ = 25°C, VIN = 12 V, fSW = 600 kHz, RnFAULT = 100 kΩ (unless otherwise noted)
Vout_Buck
EN
nFAULT
nFAULT
SW_OUT
SW_OUT
ISW_OUT
ISW_OUT
Figure 24. Power Switch Hard Short
(Auto-Recovery Version)
Figure 25. Power Switch Starts Up to Short Circuit
(Auto-Recovery Version)
ISW _OUT
Vout_Buck
nFAULT
SW_OUT
SW_IN
Vsw_out
Isw_out
nFAULT
Figure 26. Power Switch Recover from Over Current
(Auto-Recovery Version)
Figure 27. Power Switch Reverse Voltage Protection
Response
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OVERVIEW
TPS65281/TPS65281-1 PMIC integrates a current-limited, power distribution switch using N-channel MOSFETs
for applications where short circuits or heavy capacitive loads will be encountered and provide a precision current
limit protection. Additional device features include over termperature protection and reverse-voltage protection.
The device incorporates an internal charge pump and gate drive circuitry necessary to drive the N-channel
MOSFET. The charge pump supplies power to the driver circuit and provide the necessary voltage to pull the
gate of the MOSFET above the source. The charge pump operates from input voltage of power switch as low as
2.5 V and requires little supply current. The driver incorporates circuitry that controls the rise and fall times of
output voltage to limit large current and voltage surges and provides built-in soft-start functionality. TPS65281-1
device limits output current to a safe level by using a constant current mode when the output load exceeds the
current limit threshold. TPS65281 device lacthes off when the load exceeds the current limit threshold. The
device asserts the nFAULT signal during over current or reverse voltage faulty condition.
TPS65281/TPS65281-1 PMIC also integrates a synchronous step-down converter with a fixed 5-V output voltage
to provide the power for power switches in the USB ports. The synchronous buck converter incorporates a
90-mΩ high side power MOSFET and 70-mΩ low side power MOSFET to achieve high efficiency power
conversion. The converter supports an input voltage range from 4.5 V to 18 V. The converter operates in
continuous conduction mode with peak current mode control for simplified loop compensation. The switching
clock frequency can be programmed from 300 kHz to 1.4 MHz from the ROSC pin connection. The peak inductor
current limit threshold is internally set at 4 A typical. The device builds in an internal 1-ms soft-start time to
reduce inrush current during power-up.
POWER SWITCH DETAILED DESCRIPTION
Over Current Condition
The TPS65281/TPS65281-1 responds to over-current conditions on power switches by limiting the output
currents to the IOCP_SW level, which is fixed internally. The load current is less than the current-limit threshold and
the device does not limit current. During normal operation the N-channel MOSFET is fully enhanced, and
VSW_OUT = VSW_IN - (ISW_OUT x Rdson_SW). The voltage drop across the MOSFET is relatively small compared to
VSW_IN, and VSW_OUT ≈ VSW_IN. When an over current condition is detected, the device maintains a constant
output current and reduces the output voltage accordingly. During current-limit operation, the N-channel
MOSFET is no longer fully enhanced and the resistance of the device increases. This allows the device to
effectively regulate the current to the current-limit threshold. The effect of increasing the resistance of the
MOSFET is that the voltage drop across the device is no longer negligible (VSW_IN ≠ VSW_OUT), and VSW_OUT
decreases. The amount that VSW_OUT decreases is proportional to the magnitude of the overload condition. The
expected VSW_OUT can be calculated by IOS × RLOAD, where IOS is the current-limit threshold and RLOAD is the
magnitude of the overload condition.
Three possible overload conditions can occur as summarized in Table 1.
Table 1. Possible Overload Conditions
CONDITIONS
BEHAVIORS
Short circuit or partial short circuit present when
the device is powered up or enabled
The output voltage is held near zero potential with respect to ground and the TPS65281 ramps output
current to IOCP_SW. The TPS65281-1 will limit the current to IOS until the overload condition is removed or
the device begins to thermal cycle. The TPS65281 limits the current to IOS until the overload condition is
removed or the internal deglitch time (10 ms typical) is reached and the device is turned off. The device
will remain off until power is cycled or the device enable is toggled.
Gradually increasing load (<100 A/s) from normal
operating current to IOS
The current rises until current limit. Once the threshold has been reached, the device switches into its
current limiting at IOS. The TPS65281-1 will limit the current to IOS until the overload condition is removed
or the device begins to thermal cycle. The TPS65281 limits the current to IOS until the overload condition
is removed or the internal deglitch time (10 ms typical) is reached and the device is turned off. The device
will remain off until power is cycled or the device enable is toggled.
Short circuit, partial short circuit or fast transient
overload occurs while the device is enabled and
powered on
The device responds to the over-current condition within time tIOS (see Figure 5).The current sensing
amplifier is overdriven during this time, and needs time for loop response. Once tIOS has passed, the
current sensing amplifier recovers and limits the current to IOS. The TPS65281-1 will limit the current to IOS
until the overload condition is removed or the device begins to thermal cycle. The TPS65281 limits the
current to IOS until the overload condition is removed or the internal deglitch time (10 ms typical) is
reached and the device is turned off. The device will remain off until power is cycled or the device enable
is toggled.
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The TPS65281-1 thermal cycles if an overload condition is present long enough to activate thermal limiting in any
of the above cases. The power switch turns off when the junction temperature exceeds 145°C (typical) while in
current limit. The device remains off until the junction temperature cools 10°C (typical) and then restarts. The
TPS65281-1 cycles on and off until the overload is removed.
Reverse Current and Voltage Protection
A power switch in the TPS65281/TPS65281-1 incorporates two back-to-back N-channel power MOSFETs as to
prevent the reverse current flowing back the input through body diode of MOSFET when power switches are off.
The reverse-voltage protection feature turns off the N-channel MOSFET whenever the output voltage exceeds
the input voltage by 135 mV (typical) for 4 ms (typical). This prevents damage to devices on the input side of the
TPS65281/TPS65281-1 by preventing significant current from sinking into the input capacitance of power switch
or buck output capacitance. The TPS65281-1 device allows the N-channel MOSFET to turn on once the output
voltage goes below the input voltage for the same 4-ms deglitch time. The TPS65281 device keeps the power
switch turned off even if the reverse-voltage condition is removed and do not allow the N-channel MOSFET to
turn on until power is cycled or the device enable is toggled. The reverse-voltage comparator also asserts the
nFAULT output (active-low) after 4 ms.
nFAULT Response
The nFAULT open-drain output is asserted (active low) during an over current, over temperature or reversevoltage condition. The TPS65281-1 asserts the nFAULT signal until the fault condition is removed and the device
resumes normal operation. The TPS65281 asserts the nFAULT signal during a fault condition and remains
asserted while the part is latched-off. The nFAULT signal is de-asserted once device power is cycled or the
enable is toggled and the device resumes normal operation. The TPS65281/TPS65281-1 is designed to
eliminate false nFAULT reporting by using an internal delay deglitch circuit for over current (10 ms typical) and
reverse-voltage (4 ms typical) conditions without the need for external circuitry. This ensures that nFAULT is not
accidentally asserted due to normal operation such as starting into a heavy capacitive load. Deglitching circuitry
delays entering and leaving fault conditions. Over temperature conditions are not deglitched and assert the
FAULT signal immediately.
Under-Voltage Lockup (UVLO)
The under-voltage lockout (UVLO) circuit disables the power switch until the input voltage reaches the UVLO
turn-on threshold. Built-in hysteresis prevents unwanted on/off cycling due to input voltage drop from large
current surges.
Enable and Output Discharge
The logic enable EN_SW controls the power switch, bias for the charge pump, driver, and other circuits. The
supply current from power switch driver is reduced to less than 1 µA when a logic low is present on EN_SW. A
logic high input on EN_SW enables the driver, control circuits, and power switch. There is 2.5-MΩ pull-up resistor
connecting to EN_SW pin. After power switch is turned on, the resistor is switched to 1.25 MΩ. The enable input
is compatible with both TTL and CMOS logic levels. Floating the pin is not recommended.
When enable is de-asserted, the discharge function is active. The output capacitor of power switch is discharged
through an internal NMOS that has a discharge resistance of 100 Ω. Hence, the output voltage drops down to
zero. The time taken for discharge is dependent on the RC time constant of the resistance and the output
capacitor.
Power Switch Input and Output Capacitance
Input and output capacitance improves the performance of the device. The actual capacitance should be
optimized for the particular application. The output capacitor of buck should be placed as close to the SW_IN and
AGND if the integrated buck supply the power to power switch. For the application which input to power switch is
from another supply, a 0.1-µF or greater ceramic bypass capacitor between SW_IN and AGND is recommended
as close to the device as possible for local noise de-coupling. This precaution reduces ringing on the input due to
power-supply transients. Additional capacitance may be needed on the input to reduce voltage overshoot from
exceeding the absolute maximum voltage of the device during heavy transient conditions. This is especially
important during bench testing when long, inductive cables are used to connect the input of power switches in
the evaluation board to the bench power-supply.
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Placing a high-value electrolytic capacitor on the output pin is recommended when large transient currents are
expected on the output.
Programming the Current-Limit Threshold
The over-current threshold is user programmable via an external resistor. The TPS65281/TPS65281-1 uses an
internal regulation loop to provide a regulated voltage on the RLIM pin. The current-limit threshold is proportional
to the current sourced out of RLIM. The recommended 1% resistor range for RLIM is 5 kΩ ≤ RLIM ≤232 kΩ to
ensure stability of the internal regulation loop. Many applications require that the minimum current limit is above a
certain current level or that the maximum current limit is below a certain current level, so it is important to
consider the tolerance of the over-current threshold when selecting a value for RLIM. The following equations
and Figure 28 can be used to calculate the resulting over-current threshold for a given external resistor value
(RLIM). The traces routing the RLIM resistor to the TPS65281/TPS65281-1 should be as short as possible to
reduce parasitic effects on the current-limit accuracy.
RLIM can be selected to provide a current-limit threshold that occurs 1) above a minimum load current or
2) below a maximum load current.
Current-Limit Threshold Equations (IOS):
æ 22980 × V ö
Iosmax = ç
÷ (mA)
è RLIM0.94 × KW ø
(1)
æ 23950 × V ö
Iosnom = ç
÷ (mA)
è RLIM0.977 × KW ø
æ 25230 × V ö
Iosmin = ç
÷ (mA)
è RLIM1.016 × KW ø
(2)
(3)
Where 15 kΩ ≤ RLIM ≤ 232 kΩ.
While the maximum recommended value of RLIM is 232 kΩ, there is one additional configuration that allows for a
lower current-limit threshold. The RLIM pin may be connected directly to SW_IN to provide a 1.2 A (typ) currentlimit threshold. Additional low-ESR ceramic capacitance may be necessary from SW_IN to AGND in this
configuration to prevent unwanted noise from coupling into the sensitive RLIM circuitry.
60
Current Limit Resistor (kΩ)
50
40
30
20
10
0
0
0.5
1
1.5
2
2.5
3
3.5
4
Current Limit Threshold (A)
Figure 28. Current Limit Threshold (IOS) vs Current Limit Resistor (RLIM)
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Constant-Current vs. Latch-Off Operation and Impact on Output Voltage
Both the constant-current device (TPS65281-1) and latch-off device (TPS65281) operate identically during
normal operation, i.e. the load current is less than the current-limit threshold and the devices are not limiting
current. During normal operation the N-channel MOSFET is fully enhanced, and VSW_OUT = VSWIN - (ISW_OUT x
rDS(on)). The voltage drop across the MOSFET is relatively small compared to VSW_IN, and VSW_OUT ≈ VSW_IN.
Both the constant-current device (TPS65281-1) and latch-off device (TPS65281) operate identically during the
initial onset of an over-current event. Both devices limit current to the programmed current-limit threshold set by
RLIM by operating the N-channel MOSFET in the linear mode. During current-limit operation, the N-channel
MOSFET is no longer fully-enhanced and the resistance of the device increases. This allows the device to
effectively regulate the current to the current-limit threshold. The effect of increasing the resistance of the
MOSFET is that the voltage drop across the device is no longer negligible (VSW_IN ≠ VSW_OUT), and VSW_OUT
decreases. The amount that VSW_OUT decreases is proportional to the magnitude of the overload condition. The
expected VSW_OUT can be calculated by IOCP_SW × RLOAD, where IOCP_SW is the current-limit threshold and RLOAD
is the magnitude of the overload condition.
For example, if IOCP_SW is programmed to 1 A and a 1-Ω overload condition is applied, the resulting VOUT is 1 V.
While both the constant-current device (TPS65281-1) and latch-off device (TPS65281) operate identically during
the initial onset of an overcurrent event, they behave differently if the overcurrent event lasts longer than the
internal delay deglitch circuit (10 ms typical). The constant-current device (TPS65281-1) asserts the FAULT flag
after the deglitch period and continues to regulate the current to the current-limit threshold indefinitely. In
practical circuits, the power dissipation in the package will increase the die temperature above the
overtemperature shutdown threshold (145°C typical), and the device will turn off until the die temperature
decreases by the hysteresis of the thermal shutdown circuit (10°C typical). The device will turn on and continue
to thermal cycle until the overload condition is removed. The constant-current devices resume normal operation
once the overload condition is removed. The latch-off device (TPS65281) asserts the FAULT flag after the
deglitch period and immediately turns off the device. The device remains off regardless of whether the overload
condition is removed from the output. The latch-off device remains off and do not resume normal operation until
the surrounding system either toggles the enable or cycles power to the device.
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UNIVERSAL SERIAL BUS (USB) POWER-DISTRIBUTION REQUIREMENTS
One application for this device is for current limiting in universal serial bus (USB) applications. The original USB
interface was a 12-Mb/s or 1.5-Mb/s, multiplexed serial bus designed for low-to-medium bandwidth PC
peripherals (e.g., keyboards, printers, scanners, and mice). As the demand for more bandwidth increased, the
USB 2.0 standard was introduced increasing the maximum data rate to 480-Mb/s. The four-wire USB interface is
conceived for dynamic attach-detach (hot plug-unplug) of peripherals. Two lines are provided for differential data,
and two lines are provided for 5-V power distribution.
USB data is a 3.3-V level signal, but power is distributed at 5 V to allow for voltage drops in cases where power
is distributed through more than one hub across long cables. Each function must provide its own regulated 3.3 V
from the 5-V input or its own internal power supply. The USB specification classifies two different classes of
devices depending on its maximum current draw. A device classified as low-power can draw up to 100 mA as
defined by the standard. A device classified as high-power can draw up to 500 mA. It is important that the
minimum current-limit threshold of the current-limiting power-switch exceed the maximum current-limit draw of
the intended application. The latest USB standard should always be referenced when considering the currentlimit threshold.
The USB specification defines two types of devices as hubs and functions. A USB hub is a device that contains
multiple ports for different USB devices to connect and can be self-powered (SPH) or bus-powered (BPH). A
function is a USB device that is able to transmit or receive data or control information over the bus. A USB
function can be embedded in a USB hub. A USB function can be one of three types included in the list below.
• Low-power, bus-powered function
• High-power, bus-powered function
• Self-powered function
SPHs and BPHs distribute data and power to downstream functions. The TPS65281 has higher current capability
than required for a single USB port allowing it to power multiple downstream ports.
Self-Powered and Bus-Powered HUBs
A SPH has a local power supply that powers embedded functions and downstream ports. This power supply
must provide between 4.75 V and 5.25 V to downstream facing devices under full-load and no-load conditions.
SPHs are required to have current-limit protection and must report over-current conditions to the USB controller.
Typical SPHs are desktop PCs, monitors, printers, and stand-alone hubs.
A BPH obtains all power from an upstream port and often contains an embedded function. It must power up with
less than 100 mA. The BPH usually has one embedded function, and power is always available to the controller
of the hub. If the embedded function and hub require more than 100 mA on power up, the power to the
embedded function may need to be kept off until enumeration is completed. This is accomplished by removing
power or by shutting off the clock to the embedded function. Power switching the embedded function is not
necessary if the aggregate power draw for the function and controller is less than 100 mA. The total current
drawn by the bus-powered device is the sum of the current to the controller, the embedded function, and the
downstream ports, and it is limited to 500 mA from an upstream port.
Low-Power Bus-Powered and High-Power Bus-Powered Functions
Both low-power and high-power bus-powered functions obtain all power from upstream ports. Low-power
functions always draw less than 100 mA; high-power functions must draw less than 100 mA at power up and can
draw up to 500 mA after enumeration. If the load of the function is more than the parallel combination of 44 Ω
and 10 µF at power up, the device must implement inrush current limiting.
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USB Power Distribution Requirements
USB can be implemented in several ways regardless of the type of USB device being developed. Several powerdistribution features must be implemented.
SPHs must:
• Current limit downstream ports
• Report over-current conditions
BPHs must:
• Enable/disable power to downstream ports
• Power up at < 100 mA
• Limit inrush current (< 44 Ω and 10 µF)
Functions must:
• Limit inrush currents
• Power up at < 100 mA
The feature set of the TPS65281 meets each of these requirements. The integrated current limiting and overcurrent reporting is required by self-powered hubs. The logic-level enable and controlled rise times meet the
need of both input and output ports on bus-powered hubs and the input ports for bus-powered functions.
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BUCK DC/DC CONVERTER DETAILED DESCRIPTION
Output Voltage
The TPS65281/TPS65281-1 regulates output voltage set by a feedback resistor divider to 0.8-V reference
voltage. This pin should be directly connected to middle of resistor divider. It is recommended to use 1%
tolerance or better divider resistors.Great care should be taken to route the FB line away from noise sources,
such as the inductor or the LX switching node line. Start with 40.2 kΩ for the R1 resistor and use Equation 4 to
calculate R2.
0.8V
R2 = R1 × (
)
VOUT - 0.8V
(4)
Vout=5V
R1
40.2kΩ
10
-
FB
EA
+
C1
4.7 nF
0.8V
R2
7.7kΩ
Reference
2
COMP
Figure 29. Buck Feedback Resistor Divider
Switching Frequency Selection
The selection of switching frequency is a tradeoff between efficiency and component size. Low frequency
operation increases efficiency by reducing MOSFET switching losses, but requires larger inductance and
capacitance to maintain low output ripple voltage. The switching frequency of the TPS65281/TPS65281-1 buck
controller can be selected with the connection at ROSC pin. The ROSC pin can be connected to AGND, tied to
V7V, open or programmed through an external resistor. Tying ROSC pin to AGND selects 300 kHz, while tying
ROSC ping to V7V or floating ROSC pin selects 600 kHz. Placing a resistor between ROSC and AGND allows
the buck switching frequency to be programmed between 300 kHz to 1.4 MHz, as shown in Figure 14. The
programmed clock frequency by an external resistor can be calculated with the following equation:
fSW = 10 x ROSC
(5)
Soft-Start Time
The start-up of buck output is controlled by the voltage on the SS pin. When the voltage on the SS pin is less
than the internal 0.8-V reference, the TPS65281/TPS65281-1 regulates the internal feedback voltage to the
voltage on the SS pin instead of 0.8 V. The SS pin can be used to program an external soft-start function or to
allow output of the buck to track another supply during start-up. The device has an internal pull-up current source
of 4.7 µA that charges an external soft-start capacitor to provide a linear ramping voltage at SS pin. The
TPS65281 will regulate the internal feedback voltage according to the voltage on the SS pin, allowing VOUT to
rise smoothly from 0 V to its final regulated value. The total soft-start time will be approximately:
æ 0.8 × V ö
Tss = Css × ç
÷
è 4.7 × uA ø
(6)
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Internal V7V Regulator
The TPS65281/TPS65281-1 features an internal P-channel low dropout linear regulator (LDO) that supplies
power at the V7V pin from the VIN supply. V7V powers the gate drivers and much of the TPS65281/
TPS65281-1’s internal circuitry. The LDO regulates V7V to 6.3 V of over drive voltage on the power MOSFET for
the best efficiency performance. The LDO can supply a peak current of 50 mA and must be bypassed to ground
with a minimum 1-µF ceramic capacitor. The capacitor placed directly adjacent to the V7V and PGND pins is
highly recommended to supply the high transient currents required by the MOSFET gate drivers.
Short Circuit Protection
During the PWM on-time, the current through the internal high side switching MOSFET is sampled. The sampled
current is compared to a nominal 5-A over-current limit. If the sampled current exceeds the over-current limit
reference level, an internal over-current fault counter is set to 1 and an internal flag is set. Both internal high side
and low side power MOSFETs are immediately turned off and will not be turned on again until the next switching
cycle. If the over-current condition persists for eight sequential clock cycles, the over-current fault counter
overflows indicating an over-current fault condition exists. The buck regulator is shut down and stays turned off
for 10 ms. If the over-current condition clears prior to the counter reaching eight consecutive cycles, the internal
flag and counter are reset. The protection circuitry attempts to recover from the over-current condition after
10-ms power down time. The internal over-current flag and counter are reset. A normal soft-start cycle is
attempted and normal operation continues if the over-current fault condition has cleared. If the over-current fault
counter overflows during soft-start, the converter shuts down and this hiccup mode operation repeats.
Vout
Current limit threshold
IL
8 clock cycles
VLX
10ms
Figure 30. DC/DC Over-Current Protection
Inductor Selection
The higher operating frequency allows the use of smaller inductor and capacitor values. A higher frequency
generally results in lower efficiency because of MOSFET gate charge losses. In addition to this basic trade-off,
the effect of the inductor value on ripple current and low current operation must also be considered. The ripple
current depends on the inductor value. The inductor ripple current, iL, decreases with higher inductance or higher
frequency and increases with higher input voltage, VIN. Accepting larger values of iL allows the use of low
inductances, but results in higher output voltage ripple and greater core losses.
Use Equation 7 to calculate the value of the output inductor. LIR is a coefficient that represents inductor peak-topeak ripple to DC load current. It is suggested to use 0.1 ~ 0.3 for most LIR applications.
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Actual core loss of the inductor is independent of core size for a fixed inductor value, but it is dependent on the
inductance value selected. As inductance increases, core losses decrease. Unfortunately, increased inductance
requires more turns of wire and therefore copper losses will increase. Ferrite designs have very low core loss
and are preferred for high switching frequencies, so design goals can concentrate on copper loss and preventing
saturation. Ferrite core material saturates hard, which means that inductance collapses abruptly when the peak
design current is exceeded. It results in an abrupt increase in inductor ripple current and consequent output
voltage ripple. Do not allow the core to saturate. It is important that the RMS current and saturation current
ratings are not exceeding the inductor specification. The RMS and peak inductor current can be calculated from
Equation 9 and Equation 10.
V - Vout
Vout
L = in
×
IO × LIR Vin × fsw
(7)
DiL =
Vin - Vout
Vout
×
L
Vin × fsw
(8)
Vout × (Vinmax - Vout ) 2
)
Vinmax × L × fsw
2
iLrms = IO +
12
Di
ILpeak = IO + L
2
(
(9)
(10)
For this design example, use LIR = 0.3, and the inductor is calculated to be 5.40 µH with VIN = 12 V, VOUT = 5 V
and fSW = 600 kHz. Choose a 4.7 µH standard inductor, the peak to peak inductor ripple is about 34% of 3-A DC
load current.
Output Capacitor Selection
There are two primary considerations for selecting the value of the output capacitor. The output capacitors are
selected to meet load transient and output ripple’s requirements.
Equation 11 gives the minimum output capacitance to meet the transient specification. For this example,
LO = 4.7 µH, ΔIOUT = 3 A – 0.0 A = 3 A and ΔVOUT = 500 mV (10% of regulated 5 V). Using these numbers gives
a minimum capacitance of 17 µF. A standard 22 µF ceramic capacitor is used in the design.
Co >
DIOUT 2 × L
Vout × DVout
(11)
The selection of COUT is driven by the effective series resistance (ESR). Equation 12 calculates the minimum
output capacitance needed to meet the output voltage ripple specification. Where fSW is the switching frequency,
ΔVOUT is the maximum allowable output voltage ripple, and ΔiL is the inductor ripple current. In this case, the
maximum output voltage ripple is 50 mV (1% of regulated 5 V). From Equation 8, the output current ripple is 1 A.
From Equation 12, the minimum output capacitance meeting the output voltage ripple requirement is 4.6 µF with
3-mΩ esr resistance.
1
1
Co >
×
8 × fsw DVout
- esr
DiL
(12)
After considering both requirements, for this example, one 22 µF 6.3 V X7R ceramic capacitor with 3 mΩ of ESR
will be used.
Input Capacitor Selection
A minimum 10 µF X7R/X5R ceramic input capacitor is recommended to be added between VIN and GND. These
capacitors should be connected as close as physically possible to the input pins of the converters, as they
handle the RMS ripple current shown in Equation 13. For this example, IOUT = 2 A, VOUT = 5 V, minimum Vin_min =
9.6 V. Tthe input capacitors must support a ripple current of 1 A RMS.
Iinrms = Iout ×
22
Vout (Vinmin - Vout )
×
Vinmin
Vinmin
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The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be
calculated using Equation 14. Using the design example values, Iout_max = 2 A, CIN = 10 µF, fSW = 600 kHz, yields
an input voltage ripple of 83 mV.
I
× 0.25
DVin = out max
Cin × fsw
(14)
To prevent large voltage transients, a low ESR capacitor sized for the maximum RMS current must be used.
Bootstrap Capacitor Selection
The external bootstrap capacitor connected to the BST pins supply the gate drive voltages for the topside
MOSFETs. The capacitor between BST pin and LX pin is charged through an internal diode from V7V when the
LX pin is low. When high side MOSFETs are to be turned on, the driver places the bootstrap voltage across the
gate-source of the desired MOSFET. This enhances the top MOSFET switch and turns it on. The switch node
voltage, LX, rises to VIN and the BST pin follows. With the internal high side MOSFET on, the bootstrap voltage
is above the input supply: VBST = VIN + V7V. The selection on bootstrap capacitance is related with internal high
side power MOSFET gate capacitance. A 0.047-μF ceramic capacitor is recommended to be connected between
the BST to LX pin for proper operation. It is recommended to use a ceramic capacitor with X5R or better grade
dielectric. The capacitor should have 10-V or higher voltage rating.
Loop Compensation
The integrated buck DC/DC converter in TPS65281 incorporates a peak current mode. The error amplifier is a
trans-conductance amplifier with a gain of 500 µA/V. A typical type II compensation circuit adequately delivers a
phase margin between 60° and 90°. Cb adds a high frequency pole to attenuate high frequency noise when
needed. To calculate the external compensation components, follow these steps:
1. Select switching frequency, fSW, that is appropriate for application depending on L and C sizes, output ripple
and EMI. Switching frequency between 500 kHz and 1 MHz gives the best trade off between performance
and cost. To optimize efficiency, a lower switching frequency is desired.
2. Set up cross over frequency, fc, which is typically between 1/5 and 1/20 of fSW.
3. RC can be determined by:
2p × fc × Vo × Co
RC =
gM × Vref × gmps
(15)
where gm is the error amplifier gain (500 µA/V) and gmps is the power stage voltage to current conversion
gain (20 A/V).
1
fp =
CO × RL × 2p .
4. Calculate CC by placing a compensation zero at or before the dominant pole,
R × Co
CC = L
RC
(16)
5. Optional Cb can be used to cancel the zero from the ESR associated with CO.
Re sr × Co
Cb =
RC
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(17)
23
TPS65281, TPS65281-1
SLVSBH7B – JULY 2012 – REVISED DECEMBER 2012
www.ti.com
SW _IN
Buck Output : +5V
iL
R ESR
RL
Current Sense
I/V Converter
gmps = 10 A / V
Co
R1
C1
40.2 kW
4.7 nF
Vfb
COMP
EA
g M = 500µs
Rc
Vref = 0. 8V
R2
7.7 kW
Cb
Cc
Figure 31. DC/DC Loop Compensation
24
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TPS65281, TPS65281-1
www.ti.com
SLVSBH7B – JULY 2012 – REVISED DECEMBER 2012
APPLICATION INORMATION
Thermal Shutdown
The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 160°C.
The thermal shutdown forces the buck converter to stop switching when the junction temperature exceeds
thermal trip threshold. Once the die temperature decreases below 140°C, the device reinitiates the power up
sequence. The thermal shutdown hysteresis is 20°C.
Power Dissipation and Junction Temperature
The total power dissipation inside TPS65281/TPS65281-1 should not exceed the maximum allowable junction
temperature of 125°C. The maximum allowable power dissipation is a function of the thermal resistance of the
package, θJA, and ambient temperature. The analysis below gives an approximation in calculating junction
temperature based on the power dissipation in the package. However, it is important to note that thermal analysis
is strongly dependent on additional system level factors. Such factors include air flow, board layout, copper
thickness and surface area, and proximity to other devices dissipating power. Good thermal design practice must
include all system level factors in addition to individual component analysis.
To calculate the temperature inside the device under continuous load, use the following procedure.
1. Define the total continuous current through the buck converter (including the load current through power
switches). Make sure the continuous current does not exceed the maximum load current requirement.
2. From the graphs below, determine the expected losses (Y axis) in Watts for the buck converter inside the
device. The loss PD_BUCK depends on the input supply and the selected switching frequency. Please note,
the data is measured in the provided evaluation board (EVM).
3. Determine the load current IOUT through the power switch. Read RDS(on) of the power switch from the
Electrical Characteristics table.
4. The power loss through power switches can be calculated by:
PD_PW = RDS(on) × IOUT
(18)
5. The Dissipating Rating Table provides the thermal resistance, θJA, for specific packages and board layouts.
6. The maximum temperature inside the IC can be calculated by:
TJ = PD_BUCK + PD_PW × θJA + TA
(19)
Where:
TA = Ambient temperature (°C)
θJA = Thermal resistance (°C/W)
PD_BUCK = Total power dissipation in buck converter (W)
PD_PW = Total power dissipation in power switches (W)
Figure 32. Buck Power Loss vs Output Current
VIN = 12 V, fSW = 600 kHz
Figure 33. Buck Power Loss vs Output Current
VIN = 12 V, fSW = 300 kHz
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25
TPS65281, TPS65281-1
SLVSBH7B – JULY 2012 – REVISED DECEMBER 2012
www.ti.com
Auto-Retry Functionality
Some applications require that an over-current condition disables the part momentarily during a fault condition
and re-enables after a pre-set time. This auto-retry functionality can be implemented with an external resistor and
capacitor shown in Figure 34. During a fault condition, nFAULT pulls low disabling the part. The part is disabled
when EN is pulled low, and nFAULT goes high impedance allowing CRETRY to begin charging. The part reenables when the voltage on EN_SW reaches the turn-on threshold, and the auto-retry time is determined by the
resistor/capacitor time constant. The part will continue to cycle in this manner until the fault condition is removed.
C7
47nF
L1
4.7uH
+5V
C6
4.7nF
R3
40.2kΩ
C5
22uF
13
14
9
SW_IN
11
10
FB
RFAULT
100kΩ
SW_OUT
PGND
AGND
VIN
USB Data
8
C4
10uF
7
USB
Port
TPS65281
EN_SW
C3
4.7nF
USB fault signal
5
USB control signal
CRETRY
0.1uF
4
2
1
6
RLIM
EN
ROSC
16
nFAULT
SS
Enable
V7V
3
15
C2
1uF
COMP
VIN
5.5V~18V
C1
10uF
LX
BST
12
R4
7.68kΩ
R2
20kΩ
R1
10kΩ
Figure 34. Auto Retry Functionality
Some applications require auto-retry functionality and the ability to enable/disable with an external logic signal.
Figure 35 shows how an external logic signal can drive EN_SW through RFAULT and maintain auto-retry
functionality. The resistor/capacitor time constant determines the auto-retry time-out period.
C7
47nF
L1
4.7uH
+5V
C6
4.7nF
R3
40.2kΩ
C5
22uF
13
C1
10uF
14
9
11
10
FB
SW_IN
USB Data
SW_OUT
8
AGND
7
VIN
C4
10uF
USB
Port
TPS65281
6
5
RFAULT
100kΩ
external logic
signal & driver
CRETRY
0.1uF
4
1
C3
4.7nF
RLIM
EN_SW
ROSC
EN
3
16
nFAULT
SS
C2
1uF
V7V
COMP
15
Enable
PGND
2
VIN
5.5V~18V
LX
BST
12
R4
7.68kΩ
R2
20kΩ
R1
10kΩ
Figure 35. Auto Retry Functionality With External Enable Signal
26
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TPS65281, TPS65281-1
www.ti.com
SLVSBH7B – JULY 2012 – REVISED DECEMBER 2012
PCB Layout Recommendation
When laying out the printed circuit board, the following guidelines should be used to ensure proper operation of
the IC. These items are also illustrated graphically in the layout diagram of Figure 36.
• There are several signal paths that conduct fast changing currents or voltages that can interact with stray
inductance or parasitic capacitance to generate noise or degrade the power supplies performance. To help
eliminate these problems, the VIN pin should be bypassed to ground with a low ESR ceramic bypass
capacitor with X5R or X7R dielectric. This capacitor provides the AC current into the internal power
MOSFETs. Connect the (+) terminal of the input capacitor as close as possible to the VIN pin, and connect
the (-) terminal of the input capacitor as close as possible to the PGND pin. Care should be taken to minimize
the loop area formed by the bypass capacitor connections, the VIN pins, and the power ground PGND
connections.
• Since the LX connection is the switching node, the output inductor should be located close to the LX pin, and
the area of the PCB conductor minimized to prevent excessive capacitive coupling. Keep the switching node,
LX, away from all sensitive small-signal nodes.
• Connect V7V decoupling capacitor (connected close to the IC), between the V7V and the power ground
PGND pin. This capacitor carries the MOSFET drivers’ current peaks.
• Place the output filter capacitor of the buck converter close to SW_IN pins and AGND pin. Try to minimize the
ground conductor length while maintaining adequate width.
• The AGND pin should be separately routed to the (-) terminal of V7V bypass capacitor to avoid switching
grounding path. A ground plane is recommended connecting to this ground path.
• The compensation should be as close as possible to the COMP pins. The COMP and ROSC pins are
sensitive to noise so the components associated to these pins should be located as close as possible to the
IC and routed with minimal lengths of trace.
• Flood all unused areas on all layers with copper. Flooding with copper will reduce the temperature rise of the
power components. You can connect the copper areas to PGND, AGND, VIN or any other DC rail in your
system.
• There is no electric signal internal connected to thermal pad in the device. Nevertheless connect the exposed
pad beneath the IC to ground. Always solder the thermal pad to the board, and have as many vias as
possible on the PCB to enhance power dissipation.
PGND
VOUT_BUCK
Top Side
Power
Ground
Area
output inductor
boot capacitor
SW_IN
FB
LX
BST
SW_OUT
PGND
Input bypass capacitor
VIN
output capacitor
VIN
AGND
V7V
nFAULT
EN
EN_SW
Bottom Side
Power
Ground Area
power switch VOUT
output capacitor
AGND
EN_SW
RLIM
ROSC
SS
COMP
nFAULT
LDO capacitor
Bottom Side
Analog
Ground Area
Top Side Analog
Ground Area
Thermal VIA
Signal VIA
Thermal VIA
Signal VIA
Figure 36. 2-Layers PCB Layout Recommendation Diagram
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27
PACKAGE OPTION ADDENDUM
www.ti.com
20-Jan-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package Qty
Drawing
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Samples
(3)
(Requires Login)
(2)
TPS65281-1RGVR
ACTIVE
VQFN
RGV
16
2500
TBD
Call TI
TPS65281RGVR
ACTIVE
VQFN
RGV
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
TPS65281RGVT
ACTIVE
VQFN
RGV
16
250
TBD
Call TI
Call TI
Level-2-260C-1 YEAR
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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