SN54ABT7820 512 × 18 × 2 STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SGBS303E – AUGUST 1994 – REVISED APRIL 2000 D D D D D D Member of the Texas Instruments Widebus Family Advanced BiCMOS Technology Released as DSCC SMD (Standard Microcircuit Drawing) 5962-9650901QXA Independent Asynchronous Inputs and Outputs Two Separate 512 × 18 FIFOs Buffering Data in Opposite Directions Programmable Almost-Full/Almost-Empty Flag Empty, Full, and Half-Full Flags Fast Access Times of 12 ns With a 50-pF Load and Simultaneous Switching Data Outputs Packaged in 84-Pin Ceramic Pin Grid Array D D D GB PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L description A FIFO memory is a storage device that allows data to be written into and read from its array at independent data rates. The SN54ABT7820 is arranged as two 512 × 18-bit FIFOs for high speed and fast access times. It processes data at rates up to 40 MHz, with access times of 18 ns in a bit-parallel format. The SN54ABT7820 consists of bus transceiver circuits, two 512 × 18 FIFOs, and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal FIFO memories. Enable inputs GAB and GBA control the transceiver functions. The SAB and SBA control inputs select whether real-time or stored data is transferred. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. Figure 1 illustrates the eight fundamental bus-management functions that can be performed with the SN54ABT7820. The SN54ABT7820 is characterized for operation over the full military temperature range of –55°C to 125°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments. Copyright 1998, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54ABT7820 512 × 18 × 2 STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SGBS303E – AUGUST 1994 – REVISED APRIL 2000 Terminal Assignments TERMINAL NAME TERMINAL NAME TERMINAL NAME TERMINAL A1 PENA B11 FULLB F9 NC K2 A11 A2 GBA C1 GND F10 B6 K3 GND A3 SBA C2 HFA F11 GND K4 A4 LDCKA C5 UNCKB G1 A5 K5 VCC GND A5 VCC VCC C6 NC G2 GND K6 A17 C7 G3 A4 K7 GND C10 G9 B4 K8 A8 VCC LDCKB VCC HFB C11 GND G10 GND K9 VCC GND A9 SAB D1 A1 G11 B5 K10 B10 A10 GAB D2 A0 H1 A7 K11 B9 A11 AF/AEB D10 B0 H2 GND L1 A10 B1 FULLA D11 B1 H10 GND L2 A12 B2 AF/AEA E1 A3 H11 B7 L3 A13 B3 RSTA E2 A2 J1 A8 L4 A14 B4 GND E3 J2 A16 EMPTYB E9 J5 VCC A15 L5 B5 VCC VCC L6 B15 B6 UNCKA E10 B2 J6 NC L7 B16 B7 EMPTYA E11 B3 J7 B17 L8 B14 B8 GND F1 A6 J10 L9 B13 B9 RSTB F2 GND J11 VCC B8 L10 B12 B10 PENB F3 NC K1 A9 L11 B11 A6 A7 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 NAME SN54ABT7820 512 × 18 × 2 STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SGBS303E – AUGUST 1994 – REVISED APRIL 2000 Terminal Functions TERMINAL NAME I/O DESCRIPTION A0 – A17 I/O Port-A data. The 18-bit bidirectional data port for side A. AF/AEA O FIFO A almost-full/almost-empty flag. Depth offset values can be programmed for AF/AEA, or the default value of 128 can be used for both the almost-empty offset (X) and the almost-full offset (Y). AF/AEA is high when FIFO A contains X or fewer words or (512 – Y) or more words. AF/AEA is set high after FIFO A is reset. AF/AEB O FIFO B almost-full/almost-empty flag. Depth offset values can be programmed for AF/AEB, or the default value of 128 can be used for both the almost-empty offset (X) and the almost-full offset (Y). AF/AEB is high when FIFO B contains X or fewer words or (512 – Y) or more words. AF/AEB is set high after FIFO B is reset. B0 – B17 I/O Port-B data. The 18-bit bidirectional data port for side B. EMPTYA O FIFO A empty flag. EMPTYA is low when FIFO A is empty and is high when FIFO A is not empty. EMPTYA is set low after FIFO A is reset. EMPTYB O FIFO B empty flag. EMPTYB is low when FIFO B is empty and is high when FIFO B is not empty. EMPTYB is set low after FIFO B is reset. FULLA O FIFO A full flag. FULLA is low when FIFO A is full and is high when FIFO A is not full. FULLA is set high after FIFO A is reset. FULLB O FIFO B full flag. FULLB is low when FIFO B is full and is high when FIFO B is not full. FULLB is set high after FIFO B is reset. GAB I Port-B output enable. B0 – B17 outputs are active when GAB is high and are in the high-impedance state when GAB is low. GBA I Port-A output enable. A0 – A17 outputs are active when GBA is high and are in the high-impedance state when GBA is low. HFA O FIFO A half-full flag. HFA is high when FIFO A contains 256 or more words and is low when FIFO A contains 255 or fewer words. HFA is set low after FIFO A is reset. HFB O FIFO B half-full flag. HFB is high when FIFO B contains 256 or more words and is low when FIFO B contains 255 or fewer words. HFB is set low after FIFO B is reset. LDCKA I FIFO A load clock. Data is written into FIFO A on a low-to-high transition of LDCKA when FULLA is high. The first word written into an empty FIFO A is sent directly to the FIFO A data outputs. LDCKB I FIFO B load clock. Data is written into FIFO B on a low-to-high transition of LDCKB when FULLB is high. The first word written into an empty FIFO B is sent directly to the FIFO B data outputs. PENA I FIFO A program enable. After reset and before a word is written into FIFO A, the binary value on A0 – A7 is latched as an AF/AEA offset value when PENA is low and LDCKA is high. PENB I FIFO B program enable. After reset and before a word is written into FIFO B, the binary value on B0 – B7 is latched as an AF/AEB offset value when PENB is low and LDCKB is high. RSTA I FIFO A reset. A low level on RSTA resets FIFO A, forcing EMPTYA low, HFA low, FULLA high, and AF/AEA high. RSTB I FIFO B reset. A low level on RSTB resets FIFO B, forcing EMPTYB low, HFB low, FULLB high, and AF/AEB high. SAB I Port-B read select. SAB selects the source of B0 – B17 read data. A low level selects real-time data from A0 – A17. A high level selects the FIFO A output. SBA I Port-A read select. SBA selects the source of A0 – A17 read data. A low level selects real-time data from B0 – B17. A high level selects the FIFO B output. UNCKA I FIFO A unload clock. Data is read from FIFO A on a low-to-high transition of UNCKA when EMPTYA is high. UNCKB I FIFO B unload clock. Data is read from FIFO B on a low-to-high transition of UNCKB when EMPTYB is high. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54ABT7820 512 × 18 × 2 STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SGBS303E – AUGUST 1994 – REVISED APRIL 2000 logic symbol† SAB SBA GAB GBA RSTA PENA LDCKA UNCKA FULLA EMPTYA A9 A3 A10 A2 A1 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 EN1 EN2 RESET B PROG ENA PROG ENB LDCKA LDCKB A4 B6 B1 B7 AF/AEA A0 MODE 0 B3 B2 HFA 1 Φ FIFO 512 × 18 × 2 SN54ABT7820 C2 D2 UNCKA UNCKB EMPTYB ALMOST-FULL/ ALMOST-EMPTY B HALF-FULL B 0 0 D1 B11 B5 A11 C10 D10 D11 E2 E10 E1 E11 G3 G9 G1 G11 F1 F10 H1 H11 J1 J11 K1 A Data K11 B Data L1 K10 K2 L11 L2 L10 L3 L9 L4 L8 J5 L6 L5 L7 K6 RSTB PENB LDCKB UNCKB FULLB EMPTYB AF/AEB HFB B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 J7 17 17 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 4 A8 FULLB HALF-FULL A B10 C5 FULLA EMPTYA ALMOST-FULL/ ALMOST-EMPTY A B9 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 B15 B16 B17 SN54ABT7820 512 × 18 × 2 STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SGBS303E – AUGUST 1994 – REVISED APRIL 2000 logic diagram (positive logic) SAB SBA Φ FIFO B 512 × 18 HFB RSTB AF/AEB PENB EMPTYB FULLB UNCKB LDCKB Q GBA [1] D B0 [2] [3] [4] 1 of 18 Channels [15] [16] To Other Channels [17] [18] GAB Φ FIFO A 512 × 18 RSTA PENA HFA AF/AEA EMPTYA UNCKA FULLA LDCKA A0 D [1] Q [2] [3] [4] 1 of 18 Channels [15] [16] To Other Channels [17] [18] POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54ABT7820 512 × 18 × 2 STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SGBS303E – AUGUST 1994 – REVISED APRIL 2000 In FIFO A Out Bus A Bus B Bus A Bus B FIFO B Out In FIFO B Out In SAB SBA GAB GBA L X H L In SAB SBA GAB GBA X X L L FIFO A Out In Bus A Bus B Bus B FIFO B Out In SAB SBA GAB GBA X L L H SAB SBA GAB GBA H L H H FIFO A Out In Bus A Bus B Bus B FIFO B Out In SAB SBA GAB GBA H X H L SAB SBA GAB GBA L H H H FIFO A Out In FIFO A Out Bus A Bus A Bus B Bus B FIFO B Out In FIFO B Out In SAB SBA GAB GBA X H L H SAB SBA GAB GBA H H H H Figure 1. Bus-Management Functions 6 FIFO A Out Bus A FIFO B Out In In FIFO A Out Bus A FIFO B Out In In FIFO A Out In POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54ABT7820 512 × 18 × 2 STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SGBS303E – AUGUST 1994 – REVISED APRIL 2000 SELECT-MODE CONTROL TABLE OPERATION CONTROL SBA SAB A BUS B BUS L L Real-time B to A bus Real-time A to B bus H L FIFO B to A bus Real-time A to B bus L H Real-time B to A bus FIFO A to B bus H H FIFO B to A bus FIFO A to B bus OUTPUT-ENABLE CONTROL TABLE OPERATION CONTROL GBA GAB A BUS B BUS L L Isolation/input to A bus Isolation/input to B bus H L A bus enabled Isolation/input to B bus L H Isolation/input to A bus B bus enabled H H A bus enabled B bus enabled Figure 1. Bus-Management Functions (Continued) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 0 Î Î Î É Î É Î Î Î Î ÎÎ Î Î Î Î Î Î ÎÎ ÎÎ Î Î ÎÎ ÎÎ Î Î ÎÎ Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î ÎÎ Î Î Î Î Î Î Î Î Î ÎÎ LDCKA A0 – A17 Word 1 Word 129 Word 2 Word 256 Word 384 Word 512 Don’t Care Word 2 Word 1 Q0 – Q17 Word 129 Word 130 Word 257 Word 258 Word 384 Word 385 Î Î Î Î ÎÎ POST OFFICE BOX 655303 Î Î ÎÎ Î ÎÎ Î UNCKA Word 512 Invalid • DALLAS, TEXAS 75265 EMPTYA FULLA HFA AF/AEA Set X = Y = 128 Empty + X Half-Full Full – Y Full Full – Y † SAB = GAB = H, GBA = L Operation of FIFO B is identical to that of FIFO A. † Figure 2. Timing Diagram for FIFO A Half-Full Empty + X Empty SN54ABT7820 512 × 18 × 2 STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY 1 PENA SGBS303E – AUGUST 1994 – REVISED APRIL 2000 8 RSTA SN54ABT7820 512 × 18 × 2 STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SGBS303E – AUGUST 1994 – REVISED APRIL 2000 offset values for almost-full/almost-empty (AF/AE) flagFigure 2 The AF/AE flag of each FIFO has two programmable limits: the almost-empty offset value (X) and the almost-full offset value (Y). The offsets of a flag can be programmed from the input of its FIFO after it is reset and before any data is written to its memory. An AF/AE flag is high when its FIFO contains X or fewer words or (512 – Y) or more words. To program the offset values for AF/AEA, PENA can be brought low after FIFO A is reset and only when LDCKA is low. On the following low-to-high transition of LDCKA, the binary value on A0 – A7 is stored as the almost-empty offset value (X) and the almost-full offset value (Y). Holding PENA low for another low-to-high transition of LDCKA reprograms Y to the binary value on A0 – A7 at the time of the second LDCKA low-to-high transition. PENA can be brought back high only when LDCKA is low during the first two LDCKA cycles. PENA can be brought high at any time after the second LDCKA pulse returns low. A maximum value of 255 can be programmed for either X or Y (see Figure 3). To use the default values of X = Y = 128 for AF/AEA, PENA must be tied high. No data is stored in the FIFO when its AF/AE offsets are programmed. The AF/AEB flag is programmed in the same manner. PENB enables LDCKB to program the AF/AEB offset values taken from B0 – B7. RSTA LDCKA 1 ÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÌÌÌÌÌ ÌÌÌÌÌ ÌÌÌÌÌ 2 ÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏ PENA A0 – A17 X and Y Y Word 1 EMPTYA Figure 3. Programming X and Y Separately for AF/AEA POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SN54ABT7820 512 × 18 × 2 STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SGBS303E – AUGUST 1994 – REVISED APRIL 2000 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Voltage range applied to any output in the high state or power-off state, VO . . . . . . . . . . . . . . – 0.5 V to 5.5 V Current into any output in the low state, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 50 mA Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. recommended operating conditions VCC VIH Supply voltage VIL VI Low-level input voltage IOH IOL ∆t / ∆v Input transition rise or fall rate TA Operating free-air temperature High-level input voltage MIN NOM MAX 4.5 5 5.5 2 UNIT V V 0.8 V V High-level output current VCC –12 Low-level output current 24 mA 5 ns / V Input voltage 0 – 55 125 mA °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V, II = – 18 mA IOH = – 3 mA VCC = 5 V, VCC = 4.5 V, IOH = – 3 mA IOH = – 12 mA VOL II VCC = 4.5 V, VCC = 5.5 V, IOL = 24 mA VI = VCC or GND IOZH§ IOZL § VCC = 5.5 V, VCC = 5.5 V, VO = 2.7 V VO = 0.5 V IO ¶ VCC = 5.5 V, VO = 2.5 V VOH ICC VCC = 5.5 V, Ci Control inputs Co Flags Cio A or B ports IO = 0, MIN MAX UNIT – 1.2 V 2.5 2 – 40 VI = VCC or GND – 100 0.55 V ±5 µA 50 µA – 50 µA – 180 mA Outputs high 15 Outputs low 95 Outputs disabled 15 VI = 2.5 V or 0.5 V VO = 2.5 V or 0.5 V POST OFFICE BOX 655303 V 3 VO = 2.5 V or 0.5 V ‡ All typical values are at VCC = 5 V, TA = 25°C. § The parameters IOZH and IOZL include the input leakage current. ¶ Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 10 TYP‡ • DALLAS, TEXAS 75265 mA 6 pF 4 pF 8 pF SN54ABT7820 512 × 18 × 2 STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SGBS303E – AUGUST 1994 – REVISED APRIL 2000 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 4) MIN fclock tw Clock frequency Pulse duration LDCKA, LDCKB high 9 LDCKA, LDCKB low 9 UNCKA, UNCKB high 9 UNCKA, UNCKB low th Setup time Hold time UNIT 40 MHz ns 9 RSTA, RSTB low tsu MAX 10 A0 – A17 before LDCKA↑ and B0 – B17 before LDCKB↑ 4 PENA before LDCKA↑ and PENB before LDCKB↑ 6 LDCKA inactive before RSTA high and LDCKB inactive before RSTB high 4 A0 – A17 after LDCKA↑ and B0 – B17 after LDCKB↑ 0 PENA after LDCKA low and PENB after LDCKB low 3 LDCKA inactive after RSTA high and LDCKB inactive after RSTB high 4 ns ns switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 4) PARAMETER FROM (INPUT) fmax LDCK, UNCK tpd d tPLH TO (OUTPUT) LDCKA↑, LDCKB↑ B/A EMPTYA, EMPTYB UNCKA↑, UNCKB↑ tPHL RSTA low, RSTB low LDCKA↑, LDCKB↑ EMPTYA EMPTYB EMPTYA, FULLA, FULLB UNCKA↑, UNCKB↑ tPLH tpd d tPLH tPHL tpd d ten tdis RSTA low, RSTB low LDCKA↑, LDCKB↑ UNCKA↑, UNCKB↑ MAX 40 UNCKA↑, UNCKB↑ LDCKA↑, LDCKB↑ MIN FULLA, FULLB AF/AEA AF/AEB AF/AEA, UNIT MHz 3 18 3 15 3 17 3 16 5 18 5 16 5 17 7 22 7 18 7 18 ns ns ns ns ns RSTA low, RSTB low AF/AEA, AF/AEB 1 16 LDCKA↑, LDCKB↑ HFA, HFB 6 17 7 17 1 16 1 12 1 11 1 10 ns 1 13 ns UNCKA, UNCKB RSTA low, RSTB low SAB/SBA† HFA HFB HFA, B/A A/B GBA/GAB A/B GBA/GAB A/B † These parameters are measured with the internal output state of the storage register opposite that of the bus input. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ns ns ns 11 SN54ABT7820 512 × 18 × 2 STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SGBS303E – AUGUST 1994 – REVISED APRIL 2000 PARAMETER MEASUREMENT INFORMATION 7V PARAMETER S1 ten 500 Ω From Output Under Test Test Point tdis tpd 500 Ω CL = 50 pF (see Note A) S1 tPZH tPZL tPHZ tPLZ tPLH tPHL LOAD CIRCUIT Open Closed Open Closed Open Open tw 3V 3V Timing Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION th 3V Data Input 1.5 V 3V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 1.5 V 0V 1.5 V VOL Output Waveform 2 S1 at Open VOL + 0.3 V 1.5 V VOH – 0.3 V VOH ≈0V NOTE A: CL includes probe and jig capacitance. Figure 4. Load Circuit and Voltage Waveforms • DALLAS, TEXAS 75265 VOL tPHZ VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES POST OFFICE BOX 655303 tPLZ 1.5 V tPZH VOH 12 1.5 V ≈ 3.5 V Output Waveform 1 S1 at 7 V tPHL 1.5 V 1.5 V 0V 1.5 V tPLH Output Control tPZL 3V Output 1.5 V 1.5 V tsu Input Input SN54ABT7820 512 × 18 × 2 STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SGBS303E – AUGUST 1994 – REVISED APRIL 2000 TYPICAL CHARACTERISTICS PROPAGATION DELAY TIME vs LOAD CAPACITANCE SUPPLY CURRENT vs CLOCK FREQUENCY 160 VCC = 5 V TA = 25°C RL = 500 Ω VCC = 5.5 V 140 I CC(f) – Supply Current – mA t pd – Propagation Delay Time – ns typ + 6 TA = 75°C CL = 0 pF typ + 4 typ + 2 typ 120 VCC = 5 V 100 80 VCC = 4.5 V 60 40 typ – 2 0 50 100 150 200 250 300 20 10 15 20 25 30 35 40 45 CL – Load Capacitance – pF 50 55 60 65 70 fclock – Clock Frequency – MHz Figure 6 Figure 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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