SN74ABT7820 512 × 18 × 2 STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCAS206D – AUGUST 1991 – REVISED APRIL 1998 D D D D D Member of the Texas Instruments Widebus Family Advanced BiCMOS Technology Independent Asynchronous Inputs and Outputs Two Separate 512 × 18 FIFOs Buffering Data in Opposite Directions Programmable Almost-Full/Almost-Empty Flags D D D D Empty, Full, and Half-Full Flags Fast Access Times of 12 ns With a 50-pF Load and Simultaneous Switching Data Outputs Supports Clock Rates up to 67 MHz Package Options Include 80-Pin Quad Flat (PH) and 80-Pin Thin Quad Flat (PN) Packages GBA SBA GND LDCKA UNCKB EMPTYB VCC VCC VCC VCC EMPTYA UNCKA LDCKB GND SAB GAB PH PACKAGE (TOP VIEW) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 RSTA PENA AF/AEA HFA FULLA GND A0 A1 VCC A2 A3 GND A4 A5 GND A6 A7 GND A8 A9 VCC A10 A11 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 RSTB PENB AF/AEB HFB FULLB GND B0 B1 VCC B2 B3 GND B4 B5 GND B6 B7 GND B8 B9 VCC B10 B11 GND A12 A13 V CC A14 A15 GND A16 A17 B17 B16 GND B15 B14 VCC B13 B12 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments Incorporated. Copyright 1998, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74ABT7820 512 × 18 × 2 STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCAS206D – AUGUST 1991 – REVISED APRIL 1998 PENA RSTA GBA SBA GND LDCKA UNCKB EMPTYB VCC VCC VCC VCC EMPTYA UNCKA LDCKB GND SAB GAB RSTB PENB PN PACKAGE (TOP VIEW) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 AF/AEA HFA FULLA GND A0 A1 VCC A2 A3 GND A4 A5 GND A6 A7 GND A8 A9 VCC A10 1 60 2 59 3 58 4 57 5 6 56 7 55 54 8 53 9 52 51 50 10 11 12 13 49 14 47 15 16 46 48 17 45 44 18 43 19 42 41 20 AF/AEB HFB FULLB GND B0 B1 VCC B2 B3 GND B4 B5 GND B6 B7 GND B8 B9 VCC B10 A11 GND A12 A13 VCC A14 A15 GND A16 A17 B17 B16 GND B15 B14 VCC B13 B12 GND B11 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 description A FIFO memory is a storage device that allows data to be written into and read from its array at independent data rates. The SN74ABT7820 is arranged as two 512 × 18-bit FIFOs for high speed and fast access times. It processes data at rates up to 67 MHz with access times of 12 ns in a bit-parallel format. The SN74ABT7820 consists of bus-transceiver circuits, two 512 × 18 FIFOs, and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal FIFO memories. Enable inputs (GAB and GBA) control the transceiver functions. The SAB and SBA control inputs select whether real-time or stored data is transferred. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. Figure 1 illustrates the eight fundamental bus-management functions that can be performed with the SN74ABT7820. The SN74ABT7820 is characterized for operation from 0°C to 70°C. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ABT7820 512 × 18 × 2 STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCAS206D – AUGUST 1991 – REVISED APRIL 1998 In FIFO A Out Bus A Bus B Bus A Bus B FIFO B Out In FIFO B Out In SAB SBA GAB GBA X X L L SAB SBA GAB GBA L X H L In FIFO A Out In Bus A Bus B Bus B FIFO B Out In SAB SBA GAB GBA H L H H SAB SBA GAB GBA X L L H FIFO A Out In Bus A Bus B FIFO A Out Bus A Bus B FIFO B Out In FIFO B Out In SAB SBA GAB GBA L H H H SAB SBA GAB GBA H X H L In FIFO A Out Bus A FIFO B Out In In FIFO A Out In FIFO A Out In FIFO A Out Bus A Bus A Bus B Bus B FIFO B Out In FIFO B Out In SAB SBA GAB GBA H H H H SAB SBA GAB GBA X H L H Figure 1. Bus-Management Functions POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74ABT7820 512 × 18 × 2 STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCAS206D – AUGUST 1991 – REVISED APRIL 1998 SELECT-MODE CONTROL TABLE CONTROL OPERATION SBA SAB A BUS B BUS L L Real-time B-to-A bus Real-time A-to-B bus H L FIFO B-to-A bus Real-time A-to-B bus L H Real-time B-to-A bus FIFO A-to-B bus H H FIFO B-to-A bus FIFO A-to-B bus OUTPUT-ENABLE CONTROL TABLE CONTROL OPERATION GBA GAB A BUS B BUS L L Isolation/input to A bus Isolation/input to B bus H L A bus enabled Isolation/input to B bus L H Isolation/input to A bus B bus enabled H H A bus enabled B bus enabled Figure 1. Bus-Management Functions (Continued) 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ABT7820 512 × 18 × 2 STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCAS206D – AUGUST 1991 – REVISED APRIL 1998 logic symbol† SAB SBA GAB GBA RSTA PENA LDCKA UNCKA FULLA EMPTYA 66 79 65 80 1 2 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 EN1 EN2 RESET A RESET B PROG ENA PROG ENB LDCKA LDCKB 70 4 7 63 76 UNCKA 5 64 68 69 AF/AEA A0 MODE 0 77 3 HFA 1 Φ FIFO 512 × 18 × 2 SN74ABT7820 UNCKB FULLB FULLA EMPTYA ALMOST FULL/ ALMOST EMPTY A HALF-FULL A EMPTYB ALMOST FULL/ ALMOST EMPTY B HALF-FULL B 0 0 8 62 61 58 57 11 54 13 52 14 51 16 49 17 48 19 46 45 B Data 22 43 23 42 25 40 26 39 28 37 29 36 31 34 32 LDCKB UNCKB FULLB 75 55 A Data PENB 60 10 20 RSTB EMPTYB AF/AEB HFB B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 33 17 17 B15 B16 B17 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the PH package. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN74ABT7820 512 × 18 × 2 STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCAS206D – AUGUST 1991 – REVISED APRIL 1998 logic diagram (positive logic) SAB SBA Φ FIFO B 512 × 18 HFB RSTB AF/AEB PENB EMPTYB FULLB UNCKB LDCKB Q GBA [1] D B0 [2] [3] [4] 1 of 18 Channels [15] [16] To Other Channels [17] [18] GAB Φ FIFO A 512 × 18 RSTA PENA HFA AF/AEA EMPTYA UNCKA FULLA LDCKA A0 D [1] Q [2] [3] [4] 1 of 18 Channels [15] [16] To Other Channels [17] [18] 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ABT7820 512 × 18 × 2 STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCAS206D – AUGUST 1991 – REVISED APRIL 1998 Terminal Functions TERMINAL I/O A0 – A17 I/O Port-A data. The 18-bit bidirectional data port for side A. DESCRIPTION AF/AEA O FIFO A almost-full/almost-empty flag. Depth-offset values can be programmed for AF/AEA or the default value of 128 can be used for both the almost-empty offset (X) and the almost-full offset (Y). AF/AEA is high when FIFO A contains X or fewer words or (512 – Y) or more words. AF/AEA is set high after FIFO A is reset. AF/AEB O FIFO B almost-full/almost-empty flag. Depth-offset values can be programmed for AF/AEB or the default value of 128 can be used for both the almost-empty offset (X) and the almost-full offset (Y). AF/AEB is high when FIFO B contains X or fewer words or (512 – Y) or more words. AF/AEB is set high after FIFO B is reset. B0 – B17 I/O Port-B data. The 18-bit bidirectional data port for side B. EMPTYA O FIFO A empty flag. EMPTYA is low when FIFO A is empty and high when FIFO A is not empty. EMPTYA is set low after FIFO A is reset. EMPTYB O FIFO B empty flag. EMPTYB is low when FIFO B is empty and high when FIFO B is not empty. EMPTYB is set low after FIFO B is reset. FULLA O FIFO A full flag. FULLA is low when FIFO A is full and high when FIFO A is not full. FULLA is set high after FIFO A is reset. FULLB O FIFO B full flag. FULLB is low when FIFO B is full and high when FIFO B is not full. FULLB is set high after FIFO B is reset. GAB I Port-B output enable. B0 – B17 outputs are active when GAB is high and in the high-impedance state when GAB is low. GBA I Port-A output enable. A0 – A17 outputs are active when GBA is high and in the high-impedance state when GBA is low. HFA O FIFO A half-full flag. HFA is high when FIFO A contains 256 or more words and is low when FIFO A contains 255 or fewer words. HFA is set low after FIFO A is reset. HFB O FIFO B half-full flag. HFB is high when FIFO B contains 256 or more words and is low when FIFO B contains 255 or fewer words. HFB is set low after FIFO B is reset. LDCKA I FIFO A load clock. Data is written into FIFO A on a low-to-high transition of LDCKA when FULLA is high. The first word written into an empty FIFO A is sent directly to the FIFO A data outputs. LDCKB I FIFO B load clock. Data is written into FIFO B on a low-to-high transition of LDCKB when FULLB is high. The first word written into an empty FIFO B is sent directly to the FIFO B data outputs. PENA I FIFO A program enable. After reset and before a word is written into FIFO A, the binary value on A0 – A7 is latched as an AF/AEA offset value when PENA is low and LDCKA is high. PENB I FIFO B program enable. After reset and before a word is written into FIFO B, the binary value on B0 – B7 is latched as an AF/AEB offset value when PENB is low and LDCKB is high. RSTA I FIFO A reset. A low level on RSTA resets FIFO A forcing EMPTYA low, HFA low, FULLA high, and AF/AEA high. RSTB I FIFO B reset. A low level on RSTB resets FIFO B forcing EMPTYB low, HFB low, FULLB high, and AF/AEB high. SAB I Port-B read select. SAB selects the source of B0 – B17 read data. A low level selects real-time data from A0 – A17. A high level selects the FIFO A output. SBA I Port-A read select. SBA selects the source of A0 – A17 read data. A low level selects real-time data from B0 – B17. A high level selects the FIFO B output. UNCKA I FIFO A unload clock. Data is read from FIFO A on a low-to-high transition of UNCKA when EMPTYA is high. UNCKB I FIFO B unload clock. Data is read from FIFO B on a low-to-high transition of UNCKB when EMPTYB is high. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 0 ÎÎ ÎÎ ÉÎÎÉÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ LDCKA A0 – A17 Word 1 Word 2 Word 129 Word 256 Word 384 Word 512 Don’t Care Word 2 Word 1 Q0 – Q17 Word 129 Word 130 Word 257 Word 258 Word 384 Word 385 ÎÎÎ ÎÎÎ ÎÎÎ POST OFFICE BOX 655303 ÎÎ ÎÎ ÎÎ UNCKA Word 512 Invalid • DALLAS, TEXAS 75265 EMPTYA FULLA HFA AF/AEA Set X = Y = 128 Empty + X Half-Full Full – Y Full Full – Y † SAB = GAB = H, GBA = L Operation of FIFO B is identical to that of FIFO A. Figure 2. Timing Diagram for FIFO A† Half-Full Empty + X Empty SN74ABT7820 512 × 18 × 2 STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY 1 PENA SCAS206D – AUGUST 1991 – REVISED APRIL 1998 8 RSTA SN74ABT7820 512 × 18 × 2 STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCAS206D – AUGUST 1991 – REVISED APRIL 1998 offset values for AF/AEFigure 2 The AF/AE flag of each FIFO has two programmable limits: the almost-empty offset value (X) and the almost-full offset value (Y). The offsets of a flag can be programmed from the input of its FIFO after it is reset and before any data is written to its memory. An AF/AE flag is high when its FIFO contains X or fewer words or (512 – Y) or more words. To program the offset values for AF/AEA, program enable (PENA) can be brought low after FIFO A is reset and only when LDCKA is low. On the following low-to-high transition of LDCKA, the binary value on A0 – A7 is stored as the almost-empty offset value (X) and the almost-full offset value (Y). Holding PENA low for another low-to-high transition of LDCKA reprograms Y to the binary value on A0 – A7 at the time of the second LDCKA low-to-high transition. PENA can be brought back high only when LDCKA is low during the first two LDCKA cycles. PENA can be brought high at any time after the second LDCKA pulse returns low. A maximum value of 255 can be programmed for either X or Y (see Figure 3). To use the default values of X = Y = 128 for AF/AEA, PENA must be tied high. No data is stored in the FIFO when its AF/AE offsets are programmed. The AF/AEB flag is programmed in the same manner. PENB enables LDCKB to program the AF/AEB offset values taken from B0– B7. RSTA LDCKA 1 ÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÌÌÌÌÌ ÌÌÌÌÌ ÌÌÌÌÌ 2 ÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏ PENA A0 – A17 X and Y Y Word 1 EMPTYA Figure 3. Programming X and Y Separately for AF/AEA POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SN74ABT7820 512 × 18 × 2 STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCAS206D – AUGUST 1991 – REVISED APRIL 1998 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Voltage range applied to any output in the high state or power-off state, VO . . . . . . . . . . . . . . – 0.5 V to 5.5 V Current into any output in the low state, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 50 mA Package thermal impedance, θJA (see Note 2): PH package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W PN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions MIN NOM MAX 4.5 5 5.5 UNIT VCC VIH Supply voltage VIL VI Low-level input voltage IOH IOL High-level output current VCC –12 mA Low-level output current 24 mA ∆t / ∆v Input transition rise or fall rate 5 ns / V TA Operating free-air temperature 70 °C 10 High-level input voltage 2 V 0.8 Input voltage 0 0 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 V V V SN74ABT7820 512 × 18 × 2 STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCAS206D – AUGUST 1991 – REVISED APRIL 1998 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VIK VCC = 4.5 V, VCC = 4.5 V, II = – 18 mA IOH = – 3 mA VOH VCC = 5 V, VCC = 4.5 V, IOH = – 3 mA IOH = – 12 mA VOL II VCC = 4.5 V, VCC = 5.5 V, IOL = 24 mA VI = VCC or GND IOZH‡ IOZL‡ VCC = 5.5 V, VCC = 5.5 V, VO = 2.7 V VO = 0.5 V IO§ VCC = 5.5 V, VO = 2.5 V ICC VCC = 5.5 V, IO = 0, MIN TYP† MAX UNIT –1.2 V 2.5 V 3 2 –40 VI = VCC or GND –100 0.55 V ±5 µA 50 µA –50 µA –180 mA Outputs high 15 Outputs low 95 Outputs disabled 15 mA Ci Control inputs VI = 2.5 V or 0.5 V 6 pF Co Flags VO = 2.5 V or 0.5 V VO = 2.5 V or 0.5 V 4 pF 8 pF Cio A or B ports † All typical values are at VCC = 5 V, TA = 25°C. ‡ The parameters IOZH and IOZL include the input leakage current. § Not more than one output should be tested at a time, and the duration of the test should not exceed one second. timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figures 2 through 4) ’ABT7820-15 MIN fclock tw tsu th Clock frequency P l Pulse duration Setup time Hold time MAX ’ABT7820-20 MIN 67 MAX ’ABT7820-25 MIN 50 MAX ’ABT7820-30 MIN 40 33 LDCKA, LDCKB high 4 6 9 11 LDCKA, LDCKB low 4 6 9 11 UNCKA, UNCKB high 4 6 9 11 UNCKA, UNCKB low 4 6 9 11 RSTA, RSTB low 6 8 10 12 A0 – A17 before LDCKA↑ and B0 – B17 before LDCKB↑ 3 4 4 4 PENA before LDCKA↑ and PENB before LDCKB↑ 5 5 5 5 LDCKA inactive before RSTA high and LDCKB inactive before RSTB high 3 3 4 4 A0 – A17 after LDCKA↑ and B0 – B17 after LDCKB↑ 0 0 0 0 PENA after LDCKA low and PENB after LDCKB low 2 2 2 2 LDCKA inactive after RSTA high and LDCKB inactive after RSTB high 3 3 4 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MAX UNIT MHz ns ns ns 11 SN74ABT7820 512 × 18 × 2 STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCAS206D – AUGUST 1991 – REVISED APRIL 1998 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 5) PARAMETER FROM (INPUT) fmax LDCK, UNCK tpd d tpd‡ tPLH LDCKA↑, LDCKB↑ UNCKA↑, UNCKB↑ UNCKA↑, UNCKB↑ TO (OUTPUT) ’ACT7820-20 MIN 67 50 4 MAX ’ACT7820-25 MIN MAX 40 MIN MAX 33.3 UNIT MHz 14 4 15 4 18 4 20 12 4 13.5 4 15 4 17 ns 4 B/A 9 8 ns 4 14 4 15 4 17 4 19 4 13 4 14 4 16 4 18 EMPTYA, EMPTYB ns tPHL UNCKA↑, UNCKB↑ tPHL RSTA low, RSTB low EMPTYA, EMPTYB 6 16 6 16 6 18 6 20 ns tPHL LDCKA↑, LDCKB↑ FULLA, FULLB 6 13 6 14 6 16 6 18 ns 6 15 6 15 6 17 6 19 8 20 8 20 8 22 8 22 8 16 8 17 8 18 8 20 8 16 8 17 8 18 8 20 tPLH tpd d UNCKA↑, UNCKB↑ RSTA low, RSTB low LDCKA↑, LDCKB↑ UNCKA↑, UNCKB↑ FULLA,, FULLB AF/AEA,, AF/AEB ns ns tPLH RSTA low, RSTB low AF/AEA, AF/AEB 2 12 2 14 2 16 2 18 ns tPLH LDCKA↑, LDCKB↑ HFA, HFB 8 15 8 15 8 17 8 19 ns 8 15 8 15 8 17 8 19 2 12 2 14 2 16 2 18 2 10 2 11 2 12 2 14 2 9 2 10 2 11 2 13 UNCKA, UNCKB tPHL tpd d ten tdis RSTA low, RSTB low SAB/SBA§ A/B HFA, HFB B/A ns ns GBA/GAB A/B 2 6.5 2 8 2 10 2 12 ns GBA/GAB A/B 2 11 2 12 2 13 2 14 ns † All typical values are at 5 V, TA = 25°C. ‡ This parameter is measured with a 30-pF load (see Figure 5). § These parameters are measured with the internal output state of the storage register opposite that of the bus input. 12 ’ACT7820-30 B/A LDCKA↑, LDCKB↑ ’ACT7820-15 TYP† MAX MIN POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ABT7820 512 × 18 × 2 STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCAS206D – AUGUST 1991 – REVISED APRIL 1998 PARAMETER MEASUREMENT INFORMATION 7V PARAMETER S1 ten 500 Ω From Output Under Test Test Point tdis tpd 500 Ω CL = 50 pF (see Note A) S1 tPZH tPZL tPHZ tPLZ tPLH tPHL LOAD CIRCUIT Open Closed Open Closed Open Open tw 3V 3V Timing Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION th 3V Data Input 1.5 V 3V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 1.5 V tPLH 1.5 V 1.5 V tPZH VOH 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES tPLZ ≈ 3.5 V Output Waveform 1 S1 at 7 V tPHL 1.5 V 1.5 V 0V 3V 1.5 V Output Control tPZL 0V Output 1.5 V 1.5 V tsu Input Input Output Waveform 2 S1 at Open VOL + 0.3 V VOL tPHZ 1.5 V VOH – 0.3 V VOH ≈0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTE A: CL includes probe and jig capacitance. Figure 4. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 SN74ABT7820 512 × 18 × 2 STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCAS206D – AUGUST 1991 – REVISED APRIL 1998 TYPICAL CHARACTERISTICS PROPAGATION DELAY TIME vs LOAD CAPACITANCE VCC = 5 V TA = 25°C RL = 500 Ω t pd – Propagation Delay Time – ns typ + 6 typ + 4 typ + 2 typ typ – 2 0 50 100 150 200 250 300 CL – Load Capacitance – pF Figure 5 SUPPLY CURRENT vs CLOCK FREQUENCY 160 TA = 75°C CL = 0 pF VCC = 5.5 V I CC(f) – Supply Current – mA 140 120 VCC = 5 V 100 80 VCC = 4.5 V 60 40 20 10 15 20 25 30 35 40 45 50 55 60 65 70 fclock – Clock Frequency – MHz Figure 6 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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