54ACT11828, 74ACT11828 10-BIT BUFFERS/BUS DRIVERS WITH 3-STATE OUTPUTS SCAS092 – D3387, APRIL 1993 • • • • • • • Inputs Are TTL-Voltage Compatible 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers Flow-Through Architecture to Optimize PCB Layout Center-Pin VCC and GND Configurations to Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS) 1-mm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic SmallOutline Packages, Ceramic Chip Carriers, and Standard Ceramic 300-mil DIPs 54ACT11828 . . . JT PACKAGE 74ACT11828 . . . DW PACKAGE (TOP VIEW) Y1 Y2 Y3 Y4 Y5 GND GND GND GND Y6 Y7 Y8 Y9 Y10 t description These 10-bit buffers/bus drivers provide highperformance bus interface for wide data paths or buses carrying parity. The 54ACT11828 is characterized for operation over the full military temperature range of – 55°C to 125°C. The 74ACT11828 is characterized for operation from – 40°C to 85°C. G2 A L L H L L L L H X H X Z H X X Z 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 G1 A1 A2 A3 A4 A5 VCC VCC A6 A7 A8 A9 A10 G2 4 5 3 2 1 28 27 26 25 6 24 7 23 8 22 9 21 10 20 11 19 12 13 14 15 16 17 18 A8 A9 A10 G2 Y10 Y9 Y8 Y5 GND GND GND GND Y6 Y7 OUTPUT Y G1 27 A3 A4 A5 V CC V CC A6 A7 A2 A1 G1 Y1 Y2 Y3 Y4 FUNCTION TABLE INPUTS 28 2 54ACT11828 . . . FK PACKAGE (TOP VIEW) The 3-state control gate is a 2-input NOR such that if either G1 or G2 is high, all ten outputs are in the high-impedance state. The ′ACT11828 provides inverted data. 1 EPIC is a trademark of Texas Instruments Incorporated. Copyright 1993, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–1 54ACT11828, 74ACT11828 10-BIT BUFFERS/BUS DRIVERS WITH 3-STATE OUTPUTS SCAS092 – D3387, APRIL 1993 logic symbol† G1 G2 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 28 15 logic diagram (positive logic) & G1 EN G2 27 1 26 2 25 3 24 4 23 5 20 10 19 11 18 12 17 13 16 14 Y1 A1 28 15 27 1 26 2 25 3 24 4 23 5 20 10 19 11 18 12 17 13 16 14 Y1 Y2 Y3 A2 Y2 Y4 Y5 A3 Y3 Y6 Y7 A4 Y4 Y8 Y9 A5 Y5 Y10 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DW, JT, and NT packages. A6 A7 A8 A9 A10 Y6 Y7 Y8 Y9 Y10 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 250 mA Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2–2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 54ACT11828, 74ACT11828 10-BIT BUFFERS/BUS DRIVERS WITH 3-STATE OUTPUTS SCAS092 – D3387, APRIL 1993 recommended operating conditions 54ACT11828 MAX MIN MAX 4.5 5.5 4.5 5.5 VCC VIH Supply voltage VIL VI Low-level input voltage Input voltage 0 VO IOH Output voltage 0 High-level output current IOL Dt /Dv Low-level output current TA Operating free-air temperature High-level input voltage 74ACT11828 MIN 2 2 0.8 Input transition rise or fall rate UNIT V V 0.8 V VCC VCC V – 24 – 24 mA 24 24 mA VCC VCC 0 0 V 0 10 0 10 ns/ V – 55 125 – 40 85 °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = – 50 mA VOH VOL IOH = – 24 mA VCC MIN TA = 25°C TYP MAX 54ACT11828 74ACT11828 MIN MIN MAX 4.5 V 4.4 4.4 4.4 5.5 V 5.4 5.4 5.4 4.5 V 3.94 3.7 3.8 5.5 V 4.94 4.7 4.8 MAX V IOH = – 50 mA† IOH = – 75 mA† 5.5 V IOL = 50 mA 4.5 V 0.1 0.1 0.1 5.5 V 0.1 0.1 0.1 4.5 V 0.36 0.5 0.44 5.5 V 0.36 0.5 0.44 IOL = 24 mA UNIT 3.85 5.5 V 3.85 V IOL = 50 mA† IOL = 75 mA† 5.5 V IOZ II VO = VCC or GND VI = VCC or GND 5.5 V ± 0.5 ± 10 ±5 5.5 V ± 0.1 ±1 ±1 ICC VI = VCC or GND, IO = 0 One input at 3.4 V, Other inputs at GND or VCC 5.5 V 8 160 80 mA mA mA 5.5 V 0.9 1 1 mA DICC‡ Ci VI = VCC or GND VI = VCC or GND 1.65 5.5 V 5V 1.65 4.5 Co 5V 12 † Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. ‡ This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V to VCC. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 pF pF 2–3 54ACT11828, 74ACT11828 10-BIT BUFFERS/BUS DRIVERS WITH 3-STATE OUTPUTS SCAS092 – D3387, APRIL 1993 switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL A or B Y tPZH tPZL G1 or G2 Y tPHZ tPLZ G1 or G2 Y MIN TA = 25°C TYP MAX 54ACT11828 74ACT11828 MIN MAX MIN MAX 1.9 5.6 8.3 1.9 10.9 1.9 10.2 5.2 8 10.3 5.2 12.4 5.2 11.7 2.9 7 9.9 2.9 13 2.9 12.1 3.4 8.3 11.4 3.4 15.8 3.4 14.7 6 9 11.3 6 12.9 6 12.3 5.9 8.5 10.9 5.9 12.3 5.9 11.7 UNIT ns ns ns operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd d TEST CONDITIONS Outputs enabled Power dissipation capacitance pF CL = 50 pF, Outputs disabled TYP 37 f = 1 MHz 11 UNIT pF PARAMETER MEASUREMENT INFORMATION 2 × VCC 500 Ω From Output Under Test S1 GND CL = 50 pF (see Note A) 500 Ω LOAD CIRCUIT Input (see Note B) Output Control (low-level enabling) 3V 1.5 V 1.5 V 0V tPHL tPLH VOH Output Open 50% VCC 50% VCC VOL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND 3V 0V tPZL [ VCC tPLZ Output Waveform 1 S1 at 2 × VCC (see Note C) Output Waveform 2 S1 at GND (see Note C) 1.5 V 1.5 V 50% VCC VOL tPHZ tPZH VOLTAGE WAVEFORMS 20% VCC 50% VCC 80% VCC VOH [0V VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 2–4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1998, Texas Instruments Incorporated