TI 74AC11590

74AC11590
8-BIT BINARY COUNTER
WITH REGISTERED 3-STATE OUTPUTS
SCAS194 – D3988, MARCH 1992 – REVISED APRIL 1993
•
•
•
•
•
•
•
DW OR N PACKAGE
(TOP VIEW)
Parallel Registered Outputs
Internal Counters Have Direct Clear
Flow-Through Architecture Optimizes
PCB Layout
Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
EPIC  (Enhanced-Performance Implanted
CMOS) 1-µm Process
500-mA Typical Latch-Up Immunity
at 125°C
Package Options Include Plastic
Small-Outline Packages and Standard
Plastic 300-mil DIPs
QB
QC
QD
GND
GND
GND
GND
QE
QF
QG
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
QA
CCK
CCKEN
CCLR
VCC
VCC
OE
RCK
RCO
QH
description
The 74AC11590 contains an 8-bit binary counter that feeds an 8-bit storage register. The storage register has
parallel outputs. Separate clocks are provided for both the binary counter and storage register.
The binary counter features a direct clear (CCLR) input and a count-enable (CCKEN) input. For cascading, a
ripple-carry (RCO) output is provided. Expansion is easily accomplished for two stages by connecting RCO of
the first stage to CCKEN of the second stage. Cascading for larger count chains can be accomplished by
connecting RCO of each stage to CCK of the following stage.
Both the register and the counter have individual positive-edge-triggered clocks. If both clocks are connected
together, the counter state is always one count ahead of the register. Internal circuitry prevents clocking from
the clock enable.
The 74AC11590 is characterized for operation from – 40°C to 85°C.
logic symbol†
OE
RCK
14
13
18
CCKEN
CCK
19
17
CCLR
EN3
C2
G1
1+
CTR8
4
12
RCO
(CT = 255) Z4
CT = 0
2D
3
20
1
2
3
8
9
10
11
QA
QB
QC
QD
QE
QF
QG
QH
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright  1993, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–1
74AC11590
8-BIT BINARY COUNTER
WITH REGISTERED 3-STATE OUTPUTS
SCAS194 – D3988, MARCH 1992 – REVISED APRIL 1993
logic diagram (positive logic)
OE
RCK
CCKEN
CCK
CCLR
14
13
18
12
19
17
T
1R
C1
1S
T
1R
C1
1S
T
1R
C1
1S
T
1R
C1
1S
T
1R
C1
1S
T
1R
C1
1S
T
1R
C1
1S
T
1R
C1
1S
R
R
R
R
R
R
R
R
2–2
RCO
POST OFFICE BOX 655303
20
1
2
3
8
9
10
11
• DALLAS, TEXAS 75265
QA
QB
QC
QD
QE
QF
QH
QH
74AC11590
8-BIT BINARY COUNTER
WITH REGISTERED 3-STATE OUTPUTS
SCAS194 – D3988, MARCH 1992 – REVISED APRIL 1993
typical operating sequence
CCKEN
CCLR
255
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
CLK
RCK
OE
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
QA
QB
QC
QD
QE
QF
QG
QH
RCO
0
1
2
3
Count
3
5
6
7
8
Inhibit
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
Counter Clear
10
0
Count
1
2
Outputs
Disabled
2–3
74AC11590
8-BIT BINARY COUNTER
WITH REGISTERED 3-STATE OUTPUTS
SCAS194 – D3988, MARCH 1992 – REVISED APRIL 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 225 mA
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
recommended operating conditions (see Note 2)
VCC
VIH
Supply voltage
VCC = 3 V
VCC = 4.5 V
High-level input voltage
VCC = 5.5 V
VCC = 3 V
VIL
VI
VO
IOH
IOL
∆t /∆v
Low-level input voltage
NOM
MAX
3
5
5.5
3.85
0.9
1.35
0
0
VCC = 3 V
VCC = 4.5 V
POST OFFICE BOX 655303
VCC
VCC
– 24
– 24
VCC = 4.5 V
VCC = 5.5 V
24
• DALLAS, TEXAS 75265
V
V
–4
VCC = 5.5 V
VCC = 3 V
Input transition rise or fall rate
V
1.65
Output voltage
Low-level output current
V
V
3.15
Input voltage
High-level output current
UNIT
2.1
VCC = 4.5 V
VCC = 5.5 V
TA
Operating free-air temperature
NOTE 2: Unused or floating inputs must be held high or low.
2–4
MIN
mA
12
mA
24
0
10
ns/ V
– 40
85
°C
74AC11590
8-BIT BINARY COUNTER
WITH REGISTERED 3-STATE OUTPUTS
SCAS194 – D3988, MARCH 1992 – REVISED APRIL 1993
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
IOH = – 50 µA
VOH
IOH = – 4 mA
ICC
Ci
Co
MAX
MIN
3V
2.9
2.9
4.5 V
4.4
4.4
5.5 V
5.4
5.4
3V
2.58
2.48
3.94
3.8
IOL = – 24 mA
A
5.5 V
4.94
4.8
IOH = – 75 mA†
5.5 V
IOL = 12 mA
IOL = 24 mA
II
IOZ
TYP
4.5 V
IOL = 50 µA
VOL
TA = 25°C
MIN
MAX
UNIT
V
3.85
3V
0.1
0.1
4.5 V
0.1
0.1
5.5 V
0.1
0.1
3V
0.36
0.44
4.5 V
0.36
0.44
5.5 V
0.36
0.44
V
IOL = 75 mA†
VI = VCC or GND
5.5 V
5.5 V
± 0.1
±1
µA
VO = VCC or GND
VI = VCC or GND,
5.5 V
± 0.5
±5
µA
5.5 V
8
80
µA
IO = 0
VI = VCC or GND
VO = VCC or GND
1.65
5V
3
pF
5V
11
pF
† Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
fclock
Clock frequency, CCK or RCK
tw
Pulse duration
tsu
Setup time
0
50
MIN
MAX
UNIT
0
50
MHz
CCK or RCK high or low
10
10
CCLR low
7.4
7.4
CCKEN low before CCK↑
5.2
5.2
CCLR high before CCK↑
CCK↑ before RCK↑‡
3.4
3.4
8.1
8.1
ns
ns
th
Hold time
CCKEN low after CCK↑
0
0
ns
‡ This setup time ensures that the register will see stable data from the counter outputs. The clocks may be tied together, in which case the register
will be one clock pulse behind the counter.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–5
74AC11590
8-BIT BINARY COUNTER
WITH REGISTERED 3-STATE OUTPUTS
SCAS194 – D3988, MARCH 1992 – REVISED APRIL 1993
timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
fclock
Clock frequency, CCK or RCK
tw
Pulse duration
tsu
Setup time
0
80
MIN
MAX
UNIT
0
80
MHz
CCK or RCK high or low
6.3
6.3
CCLR low
4.9
4.9
CCKEN low before CCK↑
3.7
3.7
CCLR high before CCK↑
CCK↑ before RCK↑†
1.6
1.6
5.5
5.5
ns
ns
th
Hold time
CCKEN low after CCK↑
0.5
0.5
ns
† This setup time ensures that the register will see stable data from the counter outputs. The clocks may be tied together, in which case the register
will be one clock pulse behind the counter.
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
fmax
tPLH
tPHL
tPLH
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPLH
tPHL
FROM
(INPUT)
TO
(OUTPUT)
CCK or RCK
MIN
TA = 25°C
TYP
MAX
50
CCK
RCO
CCLR
RCO
RCK
Q
OE
Q
OE
Q
CCKEN
RCO
MIN
MAX
50
UNIT
MHz
7
13.5
15.9
7
18.3
9
16.9
19.5
9
22.1
6.2
12.4
14.8
6.2
17.1
7.3
13.7
16.2
7.3
18.7
7
13.6
15.9
7
17.9
7.8
15.5
18.5
7.8
21.1
8.5
18.2
21.4
8.5
24.5
6.3
10
11.9
6.3
13.2
6.8
10.8
12.8
6.8
14.1
6
11.7
14
6
16.2
6
11.6
13.7
6
15.4
ns
ns
ns
ns
ns
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
fmax
tPLH
TO
(OUTPUT)
CCK or RCK
TA = 25°C
MIN
TYP
MAX
80
CCK
RCO
CCLR
RCO
tPLH
tPHL
RCK
Q
tPZH
tPZL
OE
Q
tPHZ
tPLZ
OE
Q
tPLH
tPHL
CCKEN
RCO
tPHL
tPLH
2–6
FROM
(INPUT)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MIN
MAX
80
UNIT
MHz
3.6
7.8
10.2
3.6
11.7
4.7
9.8
12.7
4.7
14.4
3.2
7.2
9.5
3.2
10.9
3.7
8
10.4
3.7
12
3.6
8.2
10.7
3.6
12.1
3.8
8.9
11.9
3.8
13.6
3.7
9.5
12.6
3.7
14.3
4.5
7.5
9.4
4.5
10.5
5.4
8.7
10.8
5.4
12
3
6.9
9
3
10.4
2.9
7
9.2
2.9
10.4
ns
ns
ns
ns
ns
ns
74AC11590
8-BIT BINARY COUNTER
WITH REGISTERED 3-STATE OUTPUTS
SCAS194 – D3988, MARCH 1992 – REVISED APRIL 1993
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd
d
TEST CONDITIONS
Outputs enabled
Power dissipation capacitance
pF
CL = 50 pF,
Outputs disabled
TYP
UNIT
66
f = 1 MHz
pF
43
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
500 Ω
CL = 50 pF
(see Note A)
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
Timing Input
(see Note B)
0V
tw
50%
th
tsu
VCC
Input
VCC
50%
50%
VCC
50%
50%
Data Input
0V
0V
VOLTAGE WAVEFORMS
Output
Control
(low-level
enabling)
VCC
Input
(see Note B)
50%
50%
0V
tPHL
tPLH
In-Phase
Output
50% VCC
VOH
50% VCC
VOL
50% VCC
VCC
VOH
50% VCC
VOL
Output
Waveform 2
S1 at GND
(see Note C)
50%
50%
0V
tPZL
[ VCC
tPLZ
Output
Waveform 1
S1 at 2 × VCC
(see Note C)
tPLH
tPHL
Out-of-Phase
Output
VOLTAGE WAVEFORMS
50% VCC
VOL
tPHZ
tPZH
VOLTAGE WAVEFORMS
20% VCC
50% VCC
80% VCC
VOH
[0V
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–7
74AC11590
8-BIT BINARY COUNTER
WITH REGISTERED 3-STATE OUTPUTS
SCAS194 – D3988, MARCH 1992 – REVISED APRIL 1993
2–8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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