SCAS497 − D3442, MARCH 1990 − REVISED APRIL 1993
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DW OR NT PACKAGE
(TOP VIEW)
Applications Include:
Buffer/Storage Registers
Shift Registers
Pattern Generators
Flow-Through Architecture to Optimize
PCB Layout
Multiple Center-Pin VCC and GND
Configurations to Minimize High-Speed
Switching Noise
EPICt (Enhanced-Performance Implanted
CMOS) 1-mm Process
500-mA Typical Latch-Up Immunity
at 125°C
Package Options Include Plastic
Small-Outline Packages and Standard
Plastic 300-mil DIPs
1Q
2Q
3Q
4Q
GND
GND
GND
GND
5Q
6Q
7Q
8Q
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
CLR
1D
2D
3D
4D
VCC
VCC
5D
6D
7D
8D
CLK
description
These positive-edge-triggered flip-flops implement D-type flip-flop logic with a direct clear input.
Data at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going
edge of the clock pulse. When the clock input is at either the high or low level, the D input signal has no effect
at the output.
The 74AC11273 is characterized for operation from − 40°C to 85°C.
logic symbol†
FUNCTION TABLE
INPUTS
CLR
CLK
D
OUTPUT
Q
CLR
L
X
X
L
CLK
H
↑
H
H
H
↑
L
L
H
L
X
1D
2D
Q0
3D
4D
5D
6D
7D
8D
24
13
23
G1
C1
1D
1
22
2
21
3
20
4
17
9
16
10
15
11
14
12
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
† This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1993, Texas Instruments Incorporated
! " #$%! " &$'(#! )!%*
)$#!" # ! "&%##!" &% !+% !%" %," "!$%!"
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2−1
SCAS497 − D3442, MARCH 1990 − REVISED APRIL 1993
logic diagram (positive logic)
1D
2D
23
3D
22
4D
21
5D
20
6D
17
7D
16
8D
15
14
13
CLK
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
24
CLR
1
1Q
2
2Q
3
3Q
4
4Q
9
5Q
10
6Q
11
7Q
12
8Q
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 200 mA
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
recommended operating conditions
VCC
VIH
Supply voltage
VCC = 3 V
VCC = 4.5 V
High-level input voltage
VCC = 5.5 V
VCC = 3 V
VIL
VI
VO
IOH
IOL
Input voltage
2−2
5
5.5
3.15
•
•
V
0.9
1.35
V
1.65
VCC
VCC
V
V
−4
− 24
VCC = 5.5 V
VCC = 3 V
−24
VCC = 4.5 V
VCC = 5.5 V
24
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V
3.85
0
Low-level output current
Operating free-air temperature
3
UNIT
2.1
VCC = 3 V
VCC = 4.5 V
High-level output current
TA
MAX
0
Output voltage
Input transition rise or fall rate
NOM
VCC = 4.5 V
VCC = 5.5 V
Low-level input voltage
Dt /Dv
MIN
mA
12
mA
24
0
10
ns / V
− 40
85
°C
SCAS497 − D3442, MARCH 1990 − REVISED APRIL 1993
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = − 50 mA
IOH = − 4 mA
VOH
IOH = − 24 mA
IOH = − 50 mA{
IOH = − 75 mA{
MIN
TA = 25°C
TYP
MAX
MIN
3V
2.9
2.9
4.5 V
4.4
4.4
5.5 V
5.4
5.4
3V
2.58
2.48
4.5 V
3.94
3.8
5.5 V
4.94
4.8
MAX
UNIT
V
5.5 V
5.5 V
IOL = 50 mA
IOL = 12 mA
3.85
3V
0.1
0.1
4.5 V
0.1
0.1
5.5 V
0.1
0.1
3V
0.36
0.44
4.5 V
0.36
0.44
IOL = 24 mA
5.5 V
0.36
0.44
IOL = 50 mA{
5.5 V
IOL = 75 mA{
5.5 V
VI = VCC or GND
VI = VCC or GND,
5.5 V
VOL
II
ICC
VCC
V
1.65
± 0.1
IO = 0
5.5 V
VI = VCC or GND
5V
4
† Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
8
±1
mA
80
mA
Ci
pF
timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
fclock
Clock frequency
tw
Pulse duration
tsu
Setup time before CLK↑
th
Hold time, data after CLK↑
0
CLR low
55
MIN
MAX
UNIT
0
55
MHz
6
6
CLK high or low
9.1
9.1
Data
7.5
7.5
6
6
0
0
CLR inactive
ns
ns
ns
timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
fclock
Clock frequency
0
CLR low
tw
Pulse duration
tsu
Setup time before CLK↑
th
Hold time, data after CLK↑
CLK high or low
Data
CLR inactive
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80
MIN
MAX
UNIT
0
80
MHz
5
5
6.3
6.3
5
5
4.5
4.5
0
0
ns
ns
ns
2−3
SCAS497 − D3442, MARCH 1990 − REVISED APRIL 1993
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
TA = 25°C
TYP
MAX
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN
fmax
tPHL
tPLH
CLR
Any Q
5.2
14.3
16.5
5.2
18.4
4.2
12.1
14.3
4.2
16.5
5.5
14.5
16.7
5.5
18.6
55
CLK
tPHL
Any Q
MIN
MAX
55
UNIT
MHz
ns
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
TA = 25°C
TYP
MAX
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN
fmax
tPHL
tPLH
CLR
Any Q
4.3
9.2
10.9
4.3
12.3
3.5
7.7
9.3
3.5
10.7
4.5
9.3
11
4.5
12.4
80
CLK
tPHL
Any Q
MIN
MAX
80
UNIT
MHz
ns
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd
2−4
TEST CONDITIONS
Power dissipation capacitance
CL = 50 pF,
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f = 1 MHz
TYP
UNIT
80
pF
SCAS497 − D3442, MARCH 1990 − REVISED APRIL 1993
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
tw
CL = 50 pF
(see Note A)
VCC
500 Ω
Input
50%
50%
0V
VOLTAGE WAVEFORMS
LOAD CIRCUIT
VCC
Input
(see Note B)
Timing Input
(see Note B)
VCC
50%
0V
Data Input
50%
0V
tPHL
tPLH
In-Phase
Output
th
tsu
50%
50% VCC
VCC
50%
tPLH
tPHL
50%
0V
Out-of-Phase
Output
VOH
50% VCC
VOL
50% VCC
VOH
50% VCC
VOL
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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2−5
SCAS497 − D3442, MARCH 1990 − REVISED APRIL 1993
2−6
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POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77001
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