74AC11648 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCAS114 – MARCH 1990 – REVISED APRIL 1993 • • • • • • • • DW OR NT PACKAGE (TOP VIEW) Independent Registers for A and B Buses Multiplexed Real-Time and Stored Data Inverting Data Paths Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS) 1-µm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs OE A1 A2 A3 A4 GND GND GND GND A5 A6 A7 A8 DIR description 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 CLKAB SAB B1 B2 B3 B4 VCC VCC B5 B6 B7 B8 CLKBA SBA The 74AC11648 consists of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the 74AC11648. Output-enable (OE) and direction-control (DIR) inputs are provided to control the transceiver functions. In the transceiver mode, data present at the high-impedance port may be stored in either register or in both. The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The direction control (DIR) determines which bus will receive data when OE is low. In the isolation mode (OE high), A data may be stored in one register and/or B data may be stored in the other register. When an output function is disabled, the input function is still enabled and may be used to store and transmit data. Only one of the two buses, A or B, may be driven at a time. The 74AC11648 is characterized for operation from – 40°C to 85°C. EPIC is a trademark of Texas Instruments Incorporated. Copyright 1993, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–1 74AC11648 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS 1 OE L 14 DIR L 15 SBA L 27 SAB X 16 28 CLKAB CLKBA X X BUS B BUS A BUS A BUS B SCAS114 – MARCH 1990 – REVISED APRIL 1993 1 OE L 28 16 CLKAB CLKBA X ↑ X ↑ ↑ ↑ 27 SAB X X X 15 SBA X X X STORAGE FROM A, B, OR A AND B 1 OE L L 15 SBA X BUS B 14 DIR L H 28 CLKAB X L 16 CLKBA L X 27 SAB X H TRANSFER STORED DATA TO A AND/OR B Figure 1. Bus-Management Functions 2–2 27 SAB L BUS A BUS B BUS A 14 DIR X X X 16 CLKBA X REAL-TIME TRANSFER BUS A TO BUS B REAL-TIME TRANSFER BUS B TO BUS A 1 OE X X H 28 CLKAB X 14 DIR H POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 SBA H X 74AC11648 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCAS114 – MARCH 1990 – REVISED APRIL 1993 FUNCTION TABLE INPUTS DATA I/O OPERATION OR FUNCTION OE DIR CLKAB CLKBA SAB SBA A1 THRU A8 X X ↑ X X X Input B1 THRU B8 Unspecified† X X X ↑ X X Unspecified† Input H X ↑ ↑ X X Input Input Store A and B data H X L L X X Input disabled Input disabled Isolation, hold storage L L X X X L Output Input Real-time B data to A bus Store A, B unspecified† Store B, A unspecified† L L X L X H Output Input Stored B data to A bus L H X X L X Input Output Real-time A data to B bus L H L X H X Input Output Stored A data to B bus † The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled; i.e., data at the bus pins will be stored on every low-to-high transition of the clock inputs. logic symbol‡ 1 OE DIR CLKBA SBA CLKAB SAB A1 14 16 15 G3 3 EN1 [BA] 3 EN2 [AB] C4 G5 28 27 2 C6 G7 ≥1 1 6D A3 A4 A5 A6 A7 A8 5 7 1 A2 4D 5 20 B1 1 ≥1 2 7 3 25 4 24 5 23 10 20 11 19 12 18 13 17 B2 B3 B4 B5 B6 B7 B8 ‡ This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–3 74AC11648 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCAS114 – MARCH 1990 – REVISED APRIL 1993 logic diagram (positive logic) OE DIR CLKBA SBA CLKAB SAB 1 14 16 15 28 27 1 of Eight Channels 1D C1 A1 2 26 B1 1D C1 To Seven Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 200 mA Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2–4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 74AC11648 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCAS114 – MARCH 1990 – REVISED APRIL 1993 recommended operating conditions VCC Supply voltage VIH High-level input voltage VCC = 3 V VCC = 4.5 V VCC = 5.5 V MIN NOM MAX 3 5 5.5 V 3.85 VCC = 3 V VCC = 4.5 V 0.9 Low-level input voltage VI VO Input voltage 0 Output voltage 0 IOH High-level output current 1.35 VCC = 5.5 V Low-level output current ∆t /∆v Input transition rise or fall rate TA Operating free-air temperature V 2.1 3.15 VIL IOL UNIT V 1.65 VCC VCC VCC = 3 V VCC = 4.5 V VCC = 5.5 V V V –4 – 24 mA – 24 VCC = 3 V VCC = 4.5 V VCC = 5.5 V 12 24 mA 24 0 10 ns/ V – 40 85 °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = – 50 µA VOH 3V 2.9 2.9 4.5 V 4.4 4.4 5.4 5.4 2.58 2.48 4.5 V 3.94 3.8 IOH = – 24 mA A 5.5 V 4.94 IOH = – 75 mA† 5.5 V IOL = 12 mA IOL = 24 mA ICC Ci MIN 3V IOL = 50 µA II IOZ‡ TA = 25°C MIN TYP MAX 5.5 V IOH = – 4 mA VOL VCC MAX UNIT V 4.8 3.85 3V 0.1 0.1 4.5 V 0.1 0.1 5.5 V 0.1 0.1 3V 0.36 0.44 4.5 V 0.36 0.44 5.5 V 0.36 0.44 V IOL = 75 mA† 5.5 V 5.5 V ± 0.1 ±1 µA A or B ports VI = VCC or GND VO = VCC or GND 5.5 V ± 0.5 ±5 µA VI = VCC or GND, VI = VCC or GND 8 80 µA Control inputs Control inputs IO = 0 1.65 5.5 V 5V 4.5 Cio A or B ports VO = VCC or GND 5V 12 † Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. ‡ For I/O ports, the parameter IOZ includes the input leakage current. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 pF pF 2–5 74AC11648 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCAS114 – MARCH 1990 – REVISED APRIL 1993 timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 2) TA = 25°C MIN MAX fclock tw Clock frequency 0 tsu th Setup time, A or B before CLKAB↑ or CLKBA↑ Pulse duration, CLK high or low Hold time, A or B after CLKAB↑ or CLKBA↑ 40 MIN MAX UNIT 0 40 MHz 12.5 12.5 ns 6.5 6.5 ns 0 0 ns timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 2) TA = 25°C MIN MAX 0 MAX UNIT 0 90 MHz fclock tw Clock frequency Pulse duration, CLK high or low 5.6 5.6 ns tsu th Setup time, A or B before CLKAB↑ or CLKBA↑ 4.5 4.5 ns 1 1 ns Hold time, A or B after CLKAB↑ or CLKBA↑ 90 MIN switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 2) PARAMETER fmax tPLH FROM (INPUT) TO (OUTPUT) MIN TA = 25°C TYP MAX 40 MIN MAX 40 MHz 3 8.7 12.6 3 14.3 3.8 9.3 14.4 3.8 15.9 5 11.1 17.2 5 19.4 5.2 12.8 20.5 5.2 23 4.1 7.2 9.9 4.1 10.6 3.7 6.5 9.1 3.7 9.7 4.3 10.1 15.6 4.3 17.6 5.2 11.5 17.6 5.2 19.4 3.7 9.1 14.1 3.7 15.8 4.5 10.3 15.9 4.5 17.4 3.2 8.6 13.6 3.2 15.3 4.6 10.3 15.6 4.6 17.1 4.9 11.6 18.2 4.9 20.6 5.2 14.2 21.6 5.2 24.3 DIR A or B 3.8 7.1 10.1 3.8 † These parameters are measured with the internal output state of the storage register opposite to that of the bus input. 10.9 tPHL tPZH tPZL tPHZ tPLZ tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ 2–6 A or B B or A OE A or B OE A or B CLKBA or CLKAB A or B SBA or SAB† (A or B high) A or B SBA or SAB† (A or B low) A or B DIR A or B POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT ns ns ns ns ns ns ns ns 74AC11648 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCAS114 – MARCH 1990 – REVISED APRIL 1993 switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 2) PARAMETER fmax tPLH tPHL tPZH tPZL tPHZ tPLZ tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) TO (OUTPUT) MIN TA = 25°C TYP MAX 90 A or B B or A OE A or B OE A or B CLKBA or CLKAB A or B SBA or SAB† (A or B high) A or B SBA or SAB† (A or B low) A or B DIR A or B DIR A or B MIN MAX 90 UNIT MHz 2.6 5.6 8.3 2.6 9.5 3.2 6.4 9.4 3.2 10.6 4.2 7.8 11.3 4.2 12.8 4.1 8.1 12 4.1 13.6 3.8 6.3 8.6 3.8 9.2 3.5 5.7 7.8 3.5 8.4 3.6 6.9 10 3.6 11.4 4.3 8 11.4 4.3 12.8 3.1 6.2 9.2 3.1 10.4 3.8 7.6 10.4 3.8 11.6 2.8 6.1 8.9 2.8 10.1 3.8 7.3 10.4 3.8 11.6 4 8 11.9 4 13.4 4.1 8.4 12.7 4.1 14.4 3.5 6.1 8.5 3.5 9.1 3.4 5.9 7.8 3.4 8.4 ns ns ns ns ns ns ns ns operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd d Power dissipation capacitance per transceiver TEST CONDITIONS Outputs enabled Outputs disabled POST OFFICE BOX 655303 pF CL = 50 pF, • DALLAS, TEXAS 75265 f = 1 MHz TYP 66 17 UNIT pF 2–7 74AC11648 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCAS114 – MARCH 1990 – REVISED APRIL 1993 PARAMETER MEASUREMENT INFORMATION 2 × VCC S1 500 Ω From Output Under Test Open GND TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND 500 Ω CL = 50 pF (see Note A) LOAD CIRCUIT Timing Input (see Note B) 0V tw 50% th tsu VCC Input VCC 50% 50% VCC 50% 50% Data Input 0V 0V VOLTAGE WAVEFORMS Output Control (low-level enabling) VCC Input (see Note B) 50% 50% 0V tPHL tPLH In-Phase Output 50% VCC VOH 50% VCC VOL 50% VCC VCC VOH 50% VCC VOL Output Waveform 2 S1 at GND (see Note C) 50% 50% 0V tPZL [ VCC tPLZ Output Waveform 1 S1 at 2 × VCC (see Note C) tPLH tPHL Out-of-Phase Output VOLTAGE WAVEFORMS 50% VCC VOL tPHZ tPZH VOLTAGE WAVEFORMS 20% VCC 50% VCC 80% VCC VOH [0V VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. The outputs are measured one at a time with one input transition per measurement. Figure 2. Load Circuit and Voltage Waveforms 2–8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1998, Texas Instruments Incorporated