TPS61090 TPS61091, TPS61092 Actual Size (4,15 mm x 4,15 mm) www.ti.com SLVS484A – JUNE 2003 – REVISED APRIL 2004 SYNCHRONOUS BOOST CONVERTER WITH 2A SWITCH FEATURES • • • • • • • • • • DESCRIPTION Synchronous (96% Efficient) Boost Converter With 500-mA Output Current From 1.8-V Input Available in a 16-Pin QFN 4 x 4 Package Device Quiescent Current: 20-µA (Typ) Input Voltage Range: 1.8-V to 5.5-V Adjustable Output Voltage Up to 5.5-V Fixed Output Voltage Options Power Save Mode for Improved Efficiency at Low Output Power Low Battery Comparator Low EMI-Converter (Integrated Antiringing Switch) Load Disconnect During Shutdown Over-Temperature Protection The TPS6109x devices provide a power supply solution for products powered by either a one-cell Li-Ion or Li-polymer, or a two-cell alkaline, NiCd or NiMH battery and required supply currents up to or higher than 1 A. The converter generates a stable output voltage that is either adjusted by an external resistor divider or fixed internally on the chip. It provides high efficient power conversion and is capable of delivering output currents up to 0.5 A at 5 V at a supply voltage down to 1.8 V. The implemented boost converter is based on a fixed frequency, pulse-width- modulation (PWM) controller using a synchronous rectifier to obtain maximum efficiency. Boost switch and rectifier switch are connected internally to provide the lowest leakage inductance and best EMI behavior possible. The maximum peak current in the boost switch is limited to a value of 2500 mA. APPLICATIONS • The converter can be disabled to minimize battery drain. During shutdown, the load is completely disconnected from the battery. A low-EMI mode is implemented to reduce ringing and, in effect, lower radiated electromagnetic energy when the converter enters the discontinuous conduction mode. All Single Cell Li or Dual Cell Battery, or USB Powered Operated Products as MP-3 Player, PDAs, and Other Portable Equipment The output voltage can be programmed by an external resistor divider or is fixed internally on the chip. The device is packaged in a 16-pin QFN 4 x 4 mm (16 RSA) package. L1 6.8 µH SW VOUT VBAT 1.8 V to 5 V C1 Input 10 µF R1 R3 EN C2 2.2 µF C3 100 µF e.g. 5 V up to 500 mA FB LBI R4 R5 R2 SYNC GND LBO Low Battery Output PGND TPS6109x Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2003–2004, Texas Instruments Incorporated TPS61090 TPS61091, TPS61092 www.ti.com SLVS484A – JUNE 2003 – REVISED APRIL 2004 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. AVAILABLE OUTPUT VOLTAGE OPTIONS (1) TA 40°C to 85°C (1) (2) OUTPUT VOLTAGE DC/DC PACKAGE Part Number (2) Adjustable 16-Pin QFN 4x4mm TPS61090RSA 3.3 V 16-Pin QFN 4x4mm TPS61091RSA 5V 16-Pin QFN 4x4mm TPS61092RSA Contact the factory to check availability of other fixed output voltage versions. The RSA package is available taped and reeled. Add R suffix to device type (e.g., TPS61090RSAR) to order quantities of 3000 devices per reel. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) TPS6109x Input voltage range on LBI -0.3 V to 3.6 V Input voltage range on SW, VOUT, LBO, VBAT, SYNC, EN, FB -0.3 V to 7 V Operating free air temperature range TA -40°C to 85°C Maximum junction temperature TJ 150°C Storage temperature range Tstg (1) -65°C to 150°C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS MIN Supply voltage at VBAT, VI 1.8 Inductance, L 2.2 Input, capacitance, Ci Output capacitance, Co 22 NOM MAX UNIT 5.5 V 6.8 µH 10 µF 100 µF Operating free air temperature, TA -40 85 °C Operating virtual junction temperature, TJ -40 125 °C ELECTRICAL CHARACTERISTICS over recommended free-air temperature range and over recommended input voltage range (typical values are at an ambient temperature range of 25°C) (unless otherwise noted) DC/DC STAGE PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VI Input voltage range 1.8 5.5 VO TPS61090 output voltage range 1.8 5.5 V VFB TPS61090 feedback voltage 490 500 510 mV f Oscillator frequency 500 600 700 kHz 500 700 kHz 2000 2200 2500 mA Frequency range for synchronization ISW Switch current limit VOUT= 5 V Start-up current limit mA mΩ VOUT= 5 V 55 Rectifying switch on resistance VOUT= 5 V 55 Line regulation 2 0.4 x ISW Boost switch on resistance Total accuracy -3% V mΩ 3% 0.6% TPS61090 TPS61091, TPS61092 www.ti.com SLVS484A – JUNE 2003 – REVISED APRIL 2004 Electrical Characteristics (continued) over recommended free-air temperature range and over recommended input voltage range (typical values are at an ambient temperature range of 25°C) (unless otherwise noted) DC/DC STAGE PARAMETER TEST CONDITIONS MIN TYP MAX Load regulation UNIT 0.6% Quiescent current into VBAT IO = 0 mA, VEN = VBAT = 1.8 V, VOUT =5 V 10 25 µA into VOUT IO = 0 mA, VEN = VBAT = 1.8 V, VOUT = 5 V 10 20 µA VEN= 0 V, VBAT = 2.4 V 0.1 1 µA Shutdown current CONTROL STAGE PARAMETER TEST CONDITIONS VUVLO Under voltage lockout threshold VLBI voltage decreasing VIL LBI voltage threshold VLBI voltage decreasing MIN TYP 490 500 MAX UNIT 510 mV 1.5 LBI input hysteresis V 10 mV LBI input current EN = VBAT or GND 0.01 0.1 LBO output low voltage VO = 3.3 V, IOI = 100 µA 0.04 0.4 LBO output low current 100 LBO output leakage current VIL EN, SYNC input low voltage VIH EN, SYNC input high voltage VLBO = 7 V 0.01 Clamped on GND or VBAT V µA 0.1 µA 0.2 × VBAT V 0.1 µA 0.8 × VBAT EN, SYNC input current µA V 0.01 Overtemperature protection 140 °C Overtemperature hysteresis 20 °C PIN ASSIGNMENTS GND FB VOUT VOUT RSA Package (Top View) VOUT LBO SW LBI VBAT SYNC PGND SW PGND EN PGND NC Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION EN 11 I Enable input. (1/VBAT enabled, 0/GND disabled) FB 14 I Voltage feedback of adjustable versions 3 TPS61090 TPS61091, TPS61092 www.ti.com SLVS484A – JUNE 2003 – REVISED APRIL 2004 Pin Assignments (continued) Terminal Functions (continued) TERMINAL NAME I/O NO. DESCRIPTION GND 13 I/O LBI 9 I Control/logic ground Low battery comparator input (comparator enabled with EN) LBO 12 O Low battery comparator output (open drain) NC 2 SYNC 10 I Not connected Enable/disable power save mode (1: VBAT disabled, 0: GND enabled, clock signal for synchronization) SW 3, 4 I Boost and rectifying switch input PGND 5, 6, 7 I/O Power ground VBAT 8 I Supply voltage VOUT 1, 15, 16 O DC/DC output PowerPAD™ Must be soldered to achieve appropriate power dissipation. Should be connected to PGND. FUNCTIONAL BLOCK DIAGRAM SW VOUT VBAT AntiRinging PGND PGND Gate Control 100 k PGND Error Amplifier _ 10 pF FB Regulator + VREF = 0.5 V + _ Control Logic Oscillator GND Temperature Control EN SYNC GND + _ LBI + _ GND 4 Low Battery Comparator VREF = 0.5 V LBO TPS61090 TPS61091, TPS61092 www.ti.com SLVS484A – JUNE 2003 – REVISED APRIL 2004 PARAMETER MEASUREMENT INFORMATION L1 6.8 µH SW VOUT VBAT Power Supply C1 10 µF R1 R3 EN C2 2.2 µF C3 100 µF VOUT Boost Output FB LBI R4 R5 R2 SYNC GND List of Components: U1 = TPS6109xRSA L1 = Sumida CDRH103R-6R8 C1, C2 = X7R/X5R Ceramic C3 = Low ESR Tantalum LBO Low Battery Output PGND TPS6109x 5 TPS61090 TPS61091, TPS61092 www.ti.com SLVS484A – JUNE 2003 – REVISED APRIL 2004 TYPICAL CHARACTERISTICS Table of Graphs DC/DC Converter Figure Maximum output current vs Input voltage Efficiency Output voltage 1, 2 vs Output current (TPS61090) (VO = 2.5 V, VI = 1.8 V, VSYNC = 0 V) 3 vs Output current (TPS61091) (VO = 3.3 V, VI = 1.8 V, 2.4 V, VSYNC = 0 V) 4 vs Output current (TPS61092) (VO = 5.0 V, VI = 2.4 V, 3.3 V, VSYNC = 0 V) 5 vs Input voltage (TPS61091) (IO = 10 mA, 100 mA, 500 mA, VSYNC = 0 V) 6 vs Input voltage (TPS61092) (IO = 10 mA, 100 mA, 500 mA, VSYNC = 0 V) 7 vs Output current (TPS61091) (VI = 2.4 V) 8 vs Output current (TPS61092) (VI = 3.3 V) 9 No-load supply current into VBAT vs Input voltage (TPS61092) 10 No-load supply current into VOUT vs Input voltage (TPS61092) 11 Output voltage in continuous mode (TPS61092) 12 Output voltage in power save mode (TPS61092) 13 Load transient response (TPS61092) 14 Line transient response (TPS61092) 15 DC/DC converter start-up after enable (TPS61092) 16 TPS61091 TPS61092 MAXIMUM OUTPUT CURRENT vs INPUT VOLTAGE MAXIMUM OUTPUT CURRENT vs INPUT VOLTAGE 2.5 2.5 2 2 Maximum Output Current - A Maximum Output Current - A Waveforms 1.5 1 1.5 1 0.5 0.5 0 1.8 2.2 2.6 3 3.4 3.8 VI - Input Voltage - V Figure 1. 6 4.2 4.6 5 0 1.8 2.2 2.6 3 3.4 3.8 VI - Input Voltage - V Figure 2. 4.2 4.6 5 TPS61090 TPS61091, TPS61092 www.ti.com SLVS484A – JUNE 2003 – REVISED APRIL 2004 TPS61090 TPS61091 EFFICIENCY vs OUTPUT CURRENT EFFICIENCY vs OUTPUT CURRENT 100 100 90 90 80 80 70 70 Efficiency - % Efficiency - % TYPICAL CHARACTERISTICS (continued) 60 50 40 30 VI = 2.4 V VI = 1.8 V 60 50 40 30 20 20 VO = 2.5 V VI = 1.8 V 10 0 0 1 10 100 1000 IO - Output Current - mA VO = 3.3 V 10 10000 1 10 100 1000 IO - Output Current - mA Figure 3. 10000 Figure 4. TPS61092 TPS61091 EFFICIENCY vs OUTPUT CURRENT EFFICIENCY vs INPUT VOLTAGE 100 100 IO = 100 mA VI = 3.3 V 90 VI = 2.4 V 80 90 IO = 10 mA IO = 500 mA Efficiency - % Efficiency - % 70 60 50 40 80 70 30 60 20 10 VO = 5 V 0 1 10 100 1000 IO - Output Current - mA Figure 5. 10000 50 1.8 2 2.2 2.4 2.6 2.8 VI - Input Voltage - V 3 3.2 Figure 6. 7 TPS61090 TPS61091, TPS61092 www.ti.com SLVS484A – JUNE 2003 – REVISED APRIL 2004 TYPICAL CHARACTERISTICS (continued) TPS61092 TPS61091 EFFICIENCY vs INPUT VOLTAGE OUTPUT VOLTAGE vs OUTPUT CURRENT 100 3.35 IO = 100 mA 95 VBAT = 2.4 V IO = 500 mA 90 Efficiency - % VO - Output Voltage - V IO = 10 mA 85 80 75 70 65 3.3 3.25 60 55 3.2 10 50 1.8 2.2 2.6 3 3.4 3.8 VI - Input Voltage - V 4.2 4.6 5 100 1000 IO - Output Current - mA Figure 7. 5.1 10000 Figure 8. TPS61092 TPS61092 OUTPUT VOLTAGE vs OUTPUT CURRENT NO-LOAD SUPPLY CURRENT INTO VBAT vs INPUT VOLTAGE 16 No-Load Supply Current Into VBAT - µ A VBAT = 3.3 V VO - Output Voltage - V 5.05 5 4.95 4.9 4.85 4.8 10 100 1000 IO - Output Current - mA Figure 9. 8 10000 85°C 14 25°C 12 10 -40°C 8 6 4 2 0 2 3 4 VI - Input Voltage - V Figure 10. 5 TPS61090 TPS61091, TPS61092 www.ti.com SLVS484A – JUNE 2003 – REVISED APRIL 2004 TYPICAL CHARACTERISTICS (continued) TPS61092 MINIMUM LOAD RESISTANCE AT STARTUP vs INPUT VOLTAGE NO-LOAD SUPPLY CURRENT INTO VOUT vs INPUT VOLTAGE 25 Minimum Load resistance at Startup - No-Load Supply Current Into VOUT - µ A 16 85°C 14 25°C 12 10 -40°C 8 6 4 20 15 10 5 2 0 1.8 0 1.8 2.2 2.6 3 3.4 3.8 4.2 VI - Input Voltage - V 4.6 5 2.2 2.6 3 3.4 3.8 VI - Input Voltage - V Figure 11. 4.2 4.6 5 Figure 12. TPS61092 TPS61092 OUTPUT VOLTAGE IN CONTINUOUS MODE OUTPUT VOLTAGE IN POWER SAVE MODE VI = 3.3 V, RL = 10 Ω VI = 3.3 V, RL =100 Ω Output Voltage 50 mV/Div, AC Output Voltage 20 mV/Div Inductor Current 200 mA/Div, DC Inductor Current 200 mA/Div Timebase - 1 µs/Div Figure 13. Timebase - 100 µs/Div Figure 14. 9 TPS61090 TPS61091, TPS61092 www.ti.com SLVS484A – JUNE 2003 – REVISED APRIL 2004 TYPICAL CHARACTERISTICS (continued) TPS61092 TPS61092 LOAD TRANSIENT RESPONSE LINE TRANSIENT RESPONSE VI = 2.2 V to 2.7 V, RL =50 Ω VI = 2.5 V, IL =200 mA to 400 mA Input Voltage 500 mV/Div, DC Output Current 500 mA/Div, DC Output Voltage 20 mV/Div, AC Output Voltage 50 mV/Div, AC Timebase - 2 ms/Div Timebase - 2 ms/Div Figure 15. Figure 16. TPS61092 DC/DC CONVERTER START-UP AFTER ENABLE Enable 5 V/Div, DC Output Voltage 2 V/Div, DC Inductor Current 500 mA/Div, DC Voltage at SW 2 V/Div, DC VI = 2.4 V, RL =50 Ω Timebase - 200 µs/Div Figure 17. 10 TPS61090 TPS61091, TPS61092 www.ti.com SLVS484A – JUNE 2003 – REVISED APRIL 2004 APPLICATION INFORMATION DESIGN PROCEDURE The TPS6109x dc/dc converters are intended for systems powered by a dual or triple cell NiCd or NiMH battery with a typical terminal voltage between 1.8 V and 5.5 V. They can also be used in systems powered by one-cell Li-Ion with a typical stack voltage between 2.5 V and 4.2 V. Additionally, two or three primary and secondary alkaline battery cells can be the power source in systems where the TPS6109x is used. Programming the Output Voltage The output voltage of the TPS61090 dc/dc converter section can be adjusted with an external resistor divider. The typical value of the voltage on the FB pin is 500 mV. The maximum allowed value for the output voltage is 5.5 V. The current through the resistive divider should be about 100 times greater than the current into the FB pin. The typical current into the FB pin is 0.01 µA, and the voltage across R4 is typically 500 mV. Based on those two values, the recommended value for R4 should be lower than 500 kΩ, in order to set the divider current at 1 µA or higher. Because of internal compensation circuitry the value for this resistor should be in the range of 200 kΩ. From that, the value of resistor R3, depending on the needed output voltage (VO), can be calculated using Equation 1: R3 R4 V O 1 V FB 200 k V O 1 500 mV (1) If as an example, an output voltage of 5.0 V is needed, a 1.8-MΩ resistor should be chosen for R3. If for any reason the value for R4 is chosen significantly lower than 200 kΩ additional capacitance in parallel to R3 is recommended. The required capacitance value can be easily calculated using Equation 2 C parR3 10 pF 200 k –1 R4 (2) L1 SW VOUT C2 VBAT Power Supply C1 R1 C3 VOUT Boost Output R3 EN FB LBI R4 R5 R2 SYNC LBO Low Battery Output PGND GND TPS6109x Figure 18. Typical Application Circuit for Adjustable Output Voltage Option Programming the LBI/LBO Threshold Voltage The current through the resistive divider should be about 100 times greater than the current into the LBI pin. The typical current into the LBI pin is 0.01 µA, and the voltage across R2 is equal to the LBI voltage threshold that is generated on-chip, which has a value of 500 mV. The recommended value for R2is therefore in the range of 500 kΩ. From that, the value of resistor R1, depending on the desired minimum battery voltage VBAT, can be calculated using Equation 3. 11 TPS61090 TPS61091, TPS61092 www.ti.com SLVS484A – JUNE 2003 – REVISED APRIL 2004 APPLICATION INFORMATION (continued) R1 R2 V V BAT LBIthreshold 1 390 k V BAT 1 500 mV (3) The output of the low battery supervisor is a simple open-drain output that goes active low if the dedicated battery voltage drops below the programmed threshold voltage on LBI. The output requires a pullup resistor with a recommended value of 1 MΩ. The maximum voltage which is used to pull up the LBO outputs should not exceed the output voltage of the dc/dc converter. If not used, the LBO pin can be left floating or tied to GND. Inductor Selection A boost converter normally requires two main passive components for storing energy during the conversion. A boost inductor and a storage capacitor at the output are required. To select the boost inductor, it is recommended to keep the possible peak inductor current below the current limit threshold of the power switch in the chosen configuration. For example, the current limit threshold of the TPS6109x's switch is 2500 mA at an output voltage of 5 V. The highest peak current through the inductor and the switch depends on the output load, the input (VBAT), and the output voltage (VOUT). Estimation of the maximum average inductor current can be done using Equation 4: V OUT I I L OUT V 0.8 BAT (4) For example, for an output current of 500 mA at 5 V, at least 1750 mA of average current flows through the inductor at a minimum input voltage of 1.8 V. The second parameter for choosing the inductor is the desired current ripple in the inductor. Normally, it is advisable to work with a ripple of less than 20% of the average inductor current. A smaller ripple reduces the magnetic hysteresis losses in the inductor, as well as output voltage ripple and EMI. But in the same way, regulation time at load changes rises. In addition, a larger inductor increases the total system costs. With those parameters, it is possible to calculate the value for the inductor by using Equation 5: V L V –V BAT OUT BAT I ƒ V L OUT (5) Parameter f is the switching frequency and ∆IL is the ripple current in the inductor, i.e., 20% × IL. In this example, the desired inductor has the value of 5.5 µH. With this calculated value and the calculated currents, it is possible to choose a suitable inductor. Care has to be taken that load transients and losses in the circuit can lead to higher currents as estimated in equation 4. Also, the losses in the inductor caused by magnetic hysteresis losses and copper losses are a major parameter for total circuit efficiency. The following inductor series from different suppliers have been used with the TPS6109x converters: List of Inductors VENDOR INDUCTOR SERIES CDRH6D28 Sumida CDRH6D38 CDRH103R Wurth Elektronik WE-PD type L WE-PD type XL EPCOS 12 B82464G TPS61090 TPS61091, TPS61092 www.ti.com SLVS484A – JUNE 2003 – REVISED APRIL 2004 Capacitor Selection Input Capacitor At least a 10-µF input capacitor is recommended to improve transient behavior of the regulator and EMI behavior of the total power supply circuit. A ceramic capacitor or a tantalum capacitor with a 100-nF ceramic capacitor in parallel, placed close to the IC, is recommended. Output Capacitor DC/DC Converter The major parameter necessary to define the minimum value of the output capacitor is the maximum allowed output voltage ripple in steady state operation of the converter. This ripple is determined by two parameters of the capacitor, the capacitance and the ESR. It is possible to calculate the minimum capacitance needed for the defined ripple, supposing that the ESR is zero, by using equation Equation 6: I C min V V OUT OUT BAT ƒ V V OUT (6) Parameter f is the switching frequency and ∆V is the maximum allowed ripple. With a chosen ripple voltage of 10 mV, a minimum capacitance of 53 µF is needed. The total ripple is larger due to the ESR of the output capacitor. This additional component of the ripple can be calculated using Equation 7: V I R ESR OUT ESR (7) An additional ripple of 40 mV is the result of using a tantalum capacitor with a low ESR of 80 mΩ. The total ripple is the sum of the ripple caused by the capacitance and the ripple caused by the ESR of the capacitor. In this example, the total ripple is 50 mV. Additional ripple is caused by load transients. This means that the output capacitance needs to be larger than calculated above to meet the total ripple requirements. The output capacitor has to completely supply the load during the charging phase of the inductor. A reasonable value of the output capacitance depends on the speed of the load transients and the load current during the load change. With the calculated minimum value of 53 µF and load transient considerations, a reasonable output capacitance value is in a 100 µF range. For economical reasons this usually is a tantalum capacitor. Because of this the control loop has been optimized for using output capacitors with an ESR of above 30 mΩ. Small Signal Stability When using output capacitors with lower ESR, like ceramics, it is recommended to use the adjustable voltage version. The missing ESR can be easily compensated there in the feedback divider. Typically a capacitor in the range of 10 pF in parallel to R3 helps to obtain small signal stability with lowest ESR output capacitors. For more detailed analysis the small signal transfer function of the error amplifier and regulator, which is given is Equation 8, can be used. d5(R3 R4) A d A REG REG V R4 (1 i 2.3 s) FB (8) LAYOUT CONSIDERATIONS As for all switching power supplies, the layout is an important step in the design, especially at high peak currents and high switching frequencies. If the layout is not carefully done, the regulator could show stability problems as well as EMI problems. Therefore, use wide and short traces for the main current path and for the power ground tracks. The input capacitor, output capacitor, and the inductor should be placed as close as possible to the IC. Use a common ground node for power ground and a different one for control ground to minimize the effects of ground noise. Connect these ground nodes at any place close to one of the ground pins of the IC. The feedback divider should be placed as close as possible to the control ground pin of the IC. To lay out the control ground, it is recommended to use short traces as well, separated from the power ground traces. This avoids ground shift problems, which can occur due to superimposition of power ground current and control ground current. 13 TPS61090 TPS61091, TPS61092 www.ti.com SLVS484A – JUNE 2003 – REVISED APRIL 2004 APPLICATION INFORMATION L1 Battery Input VOUT SW 6.8 µH C2 2.2 µF VBAT R1 C1 10 µF EN C3 100 µF VCC 5 V Boost Output FB R5 LBI R2 SYNC LBO LBO GND PGND TPS61092 List of Components: U1 = TPS6109xRSA L1 = Sumida CDRH103R-6R8 C1, C2 = X7R,X5R Ceramic C3 = Low ESR Tantalum Figure 19. Power Supply Solution for Maximum Output Power C5 VCC2 10 V Unregulated Auxiliary Output DS1 C6 1 µF 0.1 µF L1 6.8 µH Battery Input SW VOUT C2 2.2 µF VBAT C1 10 µF R1 C3 100 µF VCC1 5 V Boost Main Output EN FB LBI R5 R2 SYNC GND List of Components: U1 = TPS6109xRSA L1 = Sumida CDRH103R-6R8 C1, C2, C5, C6, = X7R,X5R Ceramic C3 = Low ESR Tantalum DS1 = BAT54S LBO LBO PGND TPS61092 Figure 20. Power Supply Solution With Auxiliary Positive Output Voltage 14 TPS61090 TPS61091, TPS61092 www.ti.com SLVS484A – JUNE 2003 – REVISED APRIL 2004 Application Information (continued) C5 DS1 VCC2 -5 V Unregulated Auxiliary Output C6 1 µF 0.1 µF L1 6.8 µH SW VOUT C2 2.2 µF VBAT Battery Input C1 10 µF R1 C3 100 µF VCC1 5 V Boost Main Output EN FB LBI R5 R2 SYNC GND List of Components: U1 = TPS6109xRSA L1 = Sumida CDRH103R-6R8 C1, C2, C5, C6 = X7R,X5R Ceramic C3 = Low ESR Tantalum DS1 = BAT54S LBO LBO PGND TPS61092 Figure 21. Power Supply Solution With Auxiliary Negative Output Voltage DETAILED DESCRIPTION Synchronous Rectifier The device integrates an N-channel and a P-channel MOSFET transistor to realize a synchronous rectifier. Because the commonly used discrete Schottky rectifier is replaced with a low RDS(ON) PMOS switch, the power conversion efficiency reaches 96%. To avoid ground shift due to the high currents in the NMOS switch, two separate ground pins are used. The reference for all control functions is the GND pin. The source of the NMOS switch is connected to PGND. Both grounds must be connected on the PCB at only one point close to the GND pin. A special circuit is applied to disconnect the load from the input during shutdown of the converter. In conventional synchronous rectifier circuits, the backgate diode of the high-side PMOS is forward biased in shutdown and allows current flowing from the battery to the output. This device however uses a special circuit which takes the cathode of the backgate diode of the high-side PMOS and disconnects it from the source when the regulator is not enabled (EN = low). The benefit of this feature for the system design engineer is that the battery is not depleted during shutdown of the converter. No additional components have to be added to the design to make sure that the battery is disconnected from the output of the converter. Controller Circuit The controller circuit of the device is based on a fixed frequency multiple feedforward controller topology. Input voltage, output voltage, and voltage drop on the NMOS switch are monitored and forwarded to the regulator. So changes in the operating conditions of the converter directly affect the duty cycle and must not take the indirect and slow way through the control loop and the error amplifier. The control loop, determined by the error amplifier, only has to handle small signal errors. The input for it is the feedback voltage on the FB pin or, at fixed output voltage versions, the voltage on the internal resistor divider. It is compared with the internal reference voltage to generate an accurate and stable output voltage. The peak current of the NMOS switch is also sensed to limit the maximum current flowing through the switch and the inductor. The typical peak current limit is set to 2200 mA. An internal temperature sensor prevents the device from getting overheated in case of excessive power dissipation. 15 TPS61090 TPS61091, TPS61092 SLVS484A – JUNE 2003 – REVISED APRIL 2004 www.ti.com Detailed Description (continued) Device Enable The device is put into operation when EN is set high. It is put into a shutdown mode when EN is set to GND. In shutdown mode, the regulator stops switching, all internal control circuitry including the low-battery comparator is switched off, and the load is isolated from the input (as described in the Synchronous Rectifier Section). This also means that the output voltage can drop below the input voltage during shutdown. During start-up of the converter, the duty cycle and the peak current are limited in order to avoid high peak currents drawn from the battery. Undervoltage Lockout An undervoltage lockout function prevents device start-up if the supply voltage on VBAT is lower than typically 1.6 V. When in operation and the battery is being discharged, the device automatically enters the shutdown mode if the voltage on VBAT drops below approximately 1.6 V. This undervoltage lockout function is implemented in order to prevent the malfunctioning of the converter. Softstart When the device enables the internal startup cycle starts with the first step, the precharge phase. During precharge, the rectifying switch is turned on until the output capacitor is charged to a value close to the input voltage. The rectifying switch current is limited in that phase. This also limits the output current under short-circuit conditions at the output. After charging the output capacitor to the input voltage the device starts switching. Until the output voltage is reached, the boost switch current limit is set to 40% of its nominal value to avoid high peak currents at the battery during startup. When the output voltage is reached, the regulator takes control and the switch current limit is set back to 100%. Power Save Mode and Synchronization The SYNC pin can be used to select different operation modes. To enable power save, SYNC must be set low. Power save mode is used to improve efficiency at light load. In power save mode the converter only operates when the output voltage trips below a set threshold voltage. It ramps up the output voltage with one or several pulses and goes again into power save mode once the output voltage exceeds the set threshold voltage. This power save mode can be disabled by setting the SYNC to VBAT. Applying an external clock with a duty cycle between 30% and 70% at the SYNC pin forces the converter to operate at the applied clock frequency. The external frequency has to be in the range of about ±20% of the nominal internal frequency. Detailed values are shown in the electrical characteristic section of the data sheet. Low Battery Detector Circuit—LBI/LBO The low-battery detector circuit is typically used to supervise the battery voltage and to generate an error flag when the battery voltage drops below a user-set threshold voltage. The function is active only when the device is enabled. When the device is disabled, the LBO pin is high-impedance. The switching threshold is 500 mV at LBI. During normal operation, LBO stays at high impedance when the voltage, applied at LBI, is above the threshold. It is active low when the voltage at LBI goes below 500 mV. The battery voltage, at which the detection circuit switches, can be programmed with a resistive divider connected to the LBI pin. The resistive divider scales down the battery voltage to a voltage level of 500 mV, which is then compared to the LBI threshold voltage. The LBI pin has a built-in hysteresis of 10 mV. See the application section for more details about the programming of the LBI threshold. If the low-battery detection circuit is not used, the LBI pin should be connected to GND (or to VBAT) and the LBO pin can be left unconnected. Do not let the LBI pin float. 16 TPS61090 TPS61091, TPS61092 www.ti.com SLVS484A – JUNE 2003 – REVISED APRIL 2004 Low-EMI Switch The device integrates a circuit that removes the ringing that typically appears on the SW node when the converter enters discontinuous current mode. In this case, the current through the inductor ramps to zero and the rectifying PMOS switch is turned off to prevent a reverse current flowing from the output capacitors back to the battery. Due to the remaining energy that is stored in parasitic components of the semiconductor and the inductor, a ringing on the SW pin is induced. The integrated antiringing switch clamps this voltage to VBAT and therefore dampens ringing. THERMAL INFORMATION Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added heat sinks and convection surfaces, and the presence of other heat-generating components affect the power-dissipation limits of a given component. Three basic approaches for enhancing thermal performance are listed below. • Improving the power dissipation capability of the PCB design • Improving the thermal coupling of the component to the PCB • Introducing airflow in the system The maximum junction temperature (TJ) of the TPS6109x devices is 150°C. The thermal resistance of the 16-pin QFN PowerPAD package (RSA) isRΘJA = 38.1 °C/W, if the PowerPAD is soldered and the board layout is optimized. Specified regulator operation is assured to a maximum ambient temperature TA of 85°C. Therefore, the maximum power dissipation is about 1700 mW. More power can be dissipated if the maximum ambient temperature of the application is lower. T T J(MAX) A P 150°C 85°C 1700 mW D(MAX) R 38.1 kW JA If designing for a lower junction temperature of 125°C, which is recommended, maximum heat dissipation is lower. Using the above equation (8) results in 1050 mW power dissipation. 17 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) TPS61090RSAR ACTIVE QFN RSA 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS6 1090 TPS61090RSARG4 ACTIVE QFN RSA 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS6 1090 TPS61091RSAR ACTIVE QFN RSA 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS6 1091 TPS61091RSARG4 ACTIVE QFN RSA 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS6 1091 TPS61092RSAR ACTIVE QFN RSA 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS6 1092 TPS61092RSARG4 ACTIVE QFN RSA 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS6 1092 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS61090RSAR QFN RSA 16 3000 330.0 12.4 4.3 4.3 1.5 8.0 12.0 Q2 TPS61091RSAR QFN RSA 16 3000 330.0 12.4 4.3 4.3 1.5 8.0 12.0 Q2 TPS61092RSAR QFN RSA 16 3000 330.0 12.4 4.3 4.3 1.5 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS61090RSAR QFN RSA 16 3000 338.1 338.1 20.6 TPS61091RSAR QFN RSA 16 3000 338.1 338.1 20.6 TPS61092RSAR QFN RSA 16 3000 338.1 338.1 20.6 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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