IT8706R Special General Purpose I/O Preliminary Specification V0.1 Copyright 2000 ITE, Inc. This is Preliminary document release. All specifications are subject to change without notice. The material contained in this document supersedes all previous documentation issued for the related products included herein. Please contact ITE, Inc. for the latest document(s). All sales are subject to ITE’s Standard Terms and Conditions, a copy of which is included in the back of this document. ITE, IT8706R is a trademark of ITE, Inc. Intel is claimed as a trademark by Intel Corp. All other trademarks are claimed by their respective owners. All specifications are subject to change without notice. Additional copies of this manual or other ITE literature may be obtained from: ITE, Inc. Marketing Department 7F, No. 435, Nei Hu District, Jui Kuang Rd., Taipei 114, Taiwan, R.O.C. Phone: Fax: (02) 2657-9896 (02) 2657-8561, 2657-8576 ITE (USA) Inc. Marketing Department 1235 Midas Way Sunnyvale, CA 94086 U.S.A. Phone: Fax: (408) 530-8860 (408) 530-8861 ITE (USA) Inc. Eastern U.S.A. Sales Office 896 Summit St., #105 Round Rock, TX 78664 U.S.A. Phone: Fax: (512) 388-7880 (512) 388-3108 If you have any marketing or sales questions, please contact: Lawrence Liu, at ITE Taiwan: E-mail: [email protected], Tel: 886-2-26579896 X6071, Fax: 886-2-26578561 David Lin, at ITE U.S.A: E-mail: [email protected], Tel: (408) 530-8860 X238, Fax: (408) 530-8861 Don Gardenhire, at ITE Eastern USA Office: E-mail: [email protected], Tel: (512) 388-7880, Fax: (512) 388-3108 To find out more about ITE, visit our World Wide Web at: http://www.iteusa.com http://www.ite.com.tw Or e-mail [email protected] for more product information/services. Contents CONTENTS 1. 2. 3. 4. 5. 6. Features ...........................................................................................................................................................1 General Description..........................................................................................................................................1 Block Diagram ..................................................................................................................................................3 Pin Configuration..............................................................................................................................................5 IT8706R Pin Descriptions (26 signal pins + 2 VCC/GND) ...............................................................................7 System Configuration .......................................................................................................................................9 6.1 Overview................................................................................................................................................9 6.2 Register Descriptions ..........................................................................................................................10 6.2.1 Configure Control — Index 02h ..............................................................................................11 6.2.2 Logical Device Number (LDN) — Index 07h ..........................................................................11 6.2.3 Chip ID Byte 1 — Index 20h ...................................................................................................11 6.2.4 Chip ID Byte 2 — Index 21h ...................................................................................................11 6.2.5 Chip Version — Index 22h......................................................................................................11 6.2.6 Test Mode Register — Index 2Fh...........................................................................................12 6.2.7 Simple I/O Base Address MSB Register — Index 60h...........................................................12 6.2.8 Simple I/O Base Address LSB Register — Index 61h............................................................12 6.2.9 Panel Button De-bounce Base Address MSB Register — Index 62h ....................................12 6.2.10 Panel Button De-bounce Base Address LSB Register — Index 63h .....................................12 6.2.11 GPIO Pin Set 1, 2 and 3 Polarity Registers — Index F0h, F1h and F2h ...............................12 6.2.12 Simple I/O Set 1, 2, and 3 Output Enable Registers — Index F3h, F4h and F5h..................12 6.2.13 Panel Button De-bounce Control Register — Index F6h........................................................13 6.2.14 Panel Button De-bounce Set 1, 2, and 3 Enable Registers — Index F7h, F8h and F9h .......13 7. Functional Description....................................................................................................................................15 7.1 LPC Interface.......................................................................................................................................15 7.1.1 LPC Transactions ...................................................................................................................15 7.2 General Purpose I/O ...........................................................................................................................15 7.3 Power On Strapping Options...............................................................................................................16 8. DC Characteristics .........................................................................................................................................17 9. AC Characteristics..........................................................................................................................................19 10. Package Information ......................................................................................................................................21 11. Ordering Information ......................................................................................................................................23 FIGURES Figure 7-1. General Logic of GPIO Function .......................................................................................................16 Figure 9-1. LCLK Waveform................................................................................................................................19 Figure 9-2. LPC Waveform..................................................................................................................................19 TABLES Table 4-1. Pins Listed in Numeric Order ...............................................................................................................5 Table 4-2. Pins Listed in Alphabetical Order .........................................................................................................5 Table 6-1. Configuration Register List .................................................................................................................10 Table 9-1. LCLK and LRESET# AC Table ..........................................................................................................19 Table 9-2. LPC AC Table.....................................................................................................................................19 www.ite.com.tw www.iteusa.com i IT8706R V0.1 Features & General Description 1. Features Low Pin Count Interface − Complies with Intel Low Pin Count Interface Specification Rev. 1.0 18 General Purpose I/O Pins − Input mode supports switch de-bounce − Simple Input/Output function Single +5V Power Supply 28-pin SOP 2. General Description The IT8706R is a Low Pin Count Interface-based General Purpose I/O (GPIO) chip. The IT8706R provides 18 GPIO ports with internal button de-bounced circuits and SMI generation circuit. The device operates with only single +5V power supply. The IT8706R is available in 28-pin SOP package. www.ite.com.tw www.iteusa.com 1 IT8706R V0.1 ITPM-PN-200012 Joseph Huang, Feb. 21, 2000 IT8706R www.ite.com.tw www.iteusa.com 2 IT8706R V0.1 Block Diagram LPC I/F 3. Block Diagram Clock Gen. LPC Interface & Plug-and-Play Registers SMI# General Purpose I/O I/O Ports www.ite.com.tw www.iteusa.com 3 IT8706R V0.1 IT8706R www.ite.com.tw www.iteusa.com 4 IT8706R V0.1 Pin Configuration 4. Pin Configuration IT8706R 28 - SOP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 GP24 GP25 GP26 GP27 GP30/MCI0 GP31/MCI1 SMI# LRESET# LFRAME# LAD0 LAD1 LAD2 LAD3 GND VCC GP23 GP22 GP21 GP20 GP17 GP16 GP15 GP14 GP13 GP12 GP11 GP10 LCLK 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Table 4-1. Pins Listed in Numeric Order Pin 1 2 3 4 5 6 7 Signal Pin 8 9 10 11 12 13 14 GP24 GP25 GP26 GP27 GP30/MCI0 GP31/MCI1 SMI# Signal LRESET# LFRAME# LAD0 LAD1 LAD2 LAD3 GND Pin 15 16 17 18 19 20 21 Signal Pin 22 23 24 25 26 27 28 LCLK GP10 GP11 GP12 GP13 GP14 GP15 Signal GP16 GP17 GP20 GP21 GP22 GP23 VCC Table 4-2. Pins Listed in Alphabetical Order Signal GND GP10 GP11 GP12 GP13 GP14 GP15 www.ite.com.tw www.iteusa.com Pin 14 16 17 18 19 20 21 Signal GP16 GP17 GP20 GP21 GP22 GP23 GP24 Pin 22 23 24 25 26 27 1 5 Signal GP25 GP26 GP27 GP30/MCI0 GP31/MCI1 LAD0 LAD1 Pin 2 3 4 5 6 10 11 Signal LAD2 LAD3 LCLK LFRAME# LRESET# SMI# VCC Pin 12 13 15 9 8 7 28 IT8706R V0.1 IT8706R www.ite.com.tw www.iteusa.com 6 IT8706R V0.1 IT8706R Pin Descriptions 5. IT8706R Pin Descriptions (26 signal pins + 2 VCC/GND) Table 5-1. Pin Description of LPC Bus Interface Symbol Pin(s) No. Attribute Description 28 14 PWR GND +5V Power Supply. Ground. LPC RESET #. LPC Frame #. This signal indicates the start of LPC cycle. LPC Address/Data 0 - 3. 4-bit LPC address/bi-directional data lines. LAD0 is the LSB and LAD3 is the MSB. LPC Clock. 33 MHz PCI clock input. System Management Interrupt #. SMI# is an active low output asserted by this chip to inform the system that some active inputs are detected. Supplies VCC GND LPC Bus Interface Signals LRESET# LFRAME# LAD[0:3] 8 9 10 – 13 DI DI DIO8 LCLK SMI# 15 7 DI DOD8 GP1[7:0] 23 – 16 DIOD8 GP2[7:0] 4 – 1, 27 – 24 6–5 DIOD8 GPIO Signals GP3[1:0]/ MCI[1:0] DIOD8/DI General Purpose I/O 1 [7:0]. Including input detecting and simple I/O functions. General Purpose I/O 2 [7:0]. Including input detecting and simple I/O functions. General Purpose I/O 3 [1:0]/MCI[1:0]. Including input detecting and simple I/O functions. During LRESET#, these pins are inputs for MCI[1:0] power-on strapping options. IO Cell: DOD8: 8mA Digital Open-Drain Output buffer DIO8: 8mA Digital Input/Output buffer DIOD8: 8mA Digital Open-Drain Input/Output buffer DI: Digital Input www.ite.com.tw www.iteusa.com 7 IT8706R V0.1 IT8706R www.ite.com.tw www.iteusa.com 8 IT8706R V0.1 System Configuration 6. System Configuration 6.1 Overview After the hardware reset or power-on reset (LRESET#), the IT8706R enters the normal mode. Hardware Reset Any other I/O transition cycle Wait for key string I/O write to 2Eh N Is the data "87h" ? Y Any other I/O transition cycle Check Pass key I/O write to 2Eh N Next Data? Y N Last Data? Y MB PnP Mode There are three steps to completing the configuration setup: (1) Enter the MB PnP Mode; (2) Modify the data of configuration registers; (3) Exit the MB PnP Mode. Undesired result may occur if the MB PnP Mode is not exited normally. (1) Enter the MB PnP Mode To enter the MB PnP Mode, four special I/O write operations are to be performed during Wait for Key state. To ensure the initial state of the key-check logic, it is necessary to perform four write operations to the Special Address port (2Eh). Two different enter keys are provided to select configuration ports (2Eh/2Fh or 4Eh/4Fh) of the next step. 87h, 06h, 55h, 55h; or 87h, 06h, 55h, AAh; www.ite.com.tw www.iteusa.com Address port Data port 2Eh 2Fh 4Eh 4Fh 9 IT8706R V0.1 IT8706R (2) Modify the Data of the Registers All configuration registers can be accessed after entering the MB PnP Mode. Before accessing a selected register, the content of Index 07h must be changed to the LDN to which the register belongs, except some Global registers. (3) Exit the MB PnP Mode Set bit 1 of the configure control register (Index=02h) to “1” to exit the MB PnP Mode. 6.2 Register Descriptions Table 6-1. Configuration Register List Register Name R/W LDN Index Default W All 02h - R/W All 07h 00h Chip ID Byte 1 R All 20h 87h Chip ID Byte 2 R All 21h 06h All 22h 00h Configure Control Logic Device Number (LDN) Chip Version R/W Note1 Test Mode Register R/W F4h 2Fh 00h Simple I/O Base Address MSB Register R/W 10h 60h 00h Simple I/O Base Address LSB Register R/W 10h 61h 00h Panel Button De-bounce Base Address MSB Register R/W 10h 62h 00h Panel Button De-bounce Base Address LSB Register R/W 10h 63h 00h GPIO Set 1 Pin Polarity Register R/W 10h F0h 00h GPIO Set 2 Pin Polarity Register R/W 10h F1h 00h GPIO Set 3 Pin Polarity Register R/W 10h F2h 00h Simple I/O Set 1 Output Enable Register R/W 10h F3h 00h Simple I/O Set 2 Output Enable Register R/W 10h F4h 00h Simple I/O Set 3 Output Enable Register R/W 10h F5h 00h Panel Button De-bounce Control Register R/W 10h F5h 00h Panel Button De-bounce Set 1 Enable Register R/W 10h F7h 00h Panel Button De-bounce Set 2 Enable Register R/W 10h F8h 00h 10h F9h 00h Panel Button De-bounce Set 3 Enable Register R/W Note 1: Bits 5-4 in the register are write only. Bits 3-0 are read only. www.ite.com.tw www.iteusa.com 10 IT8706R V0.1 System Configuration 6.2.1 Configure Control — Index 02h This register is write only. Its values are not sticky; that is to say, a hardware reset will automatically clear the bits, and does not require the software to clear them. Bit R/W 7-2 - 1 W 0 - 6.2.2 Default Description Reserved Returns to the “Wait for Key” state. This bit is used when the configuration sequence is completed. Reserved Logical Device Number (LDN) — Index 07h This register is used to select the current logical devices. By reading from or writing to the configuration of I/O, Interrupt, DMA and other special functions, all registers of the logical devices can be accessed. In addition, ACTIVATE command is only effective for the selected logical devices. This register is read/write. Bit R/W Default 7-0 R/W 00h 6.2.3 Description LDN Chip ID Byte 1 — Index 20h This register is the Chip ID Byte 1 and is read only. Bits [7:0]=87h when read. Bit R/W Default 7-0 R 87h 6.2.4 Description Chip ID 1 Chip ID Byte 2 — Index 21h This register is the Chip ID Byte 2 and is read only. Bits [7:0]=06h when read. Bit R/W Default 7-0 R 06h 6.2.5 Description Chip ID 2 Chip Version — Index 22h Bit R/W 7-6 - 5-4 W 3-0 R www.ite.com.tw www.iteusa.com Default Description 0h Reserved Multi-chips selection. These two bits can be written. When these bits are written, the MB PnP mode will be forced to exit if the given values do not match the MCI[1:0]. The MB PnP will be remained if the given values match the MCI[1:0]. Chip Version. Read only. 11 IT8706R V0.1 IT8706R 6.2.6 Test Mode Register — Index 2Fh This register is the Test Mode Register and is reserved for ITE. It should not be set. 6.2.7 Simple I/O Base Address MSB Register — Index 60h Bit R/W Default 7-4 R 0h READ only as “0h” for Base Address [15:12]. 3-0 R/W 0h READ/WRITE, mapped as Base Address [11:8]. 6.2.8 Simple I/O Base Address LSB Register — Index 61h Bit R/W Default 7-0 R/W 00h 6.2.9 Description Description Mapped as Base Address [7:0]. Panel Button De-bounce Base Address MSB Register — Index 62h Bit R/W Default Description 7-4 R 0h Read only as “0h” for Base Address [15:12]. 3-0 R/W 0h READ/WRITE, mapped as Base Address [11:8]. 6.2.10 Panel Button De-bounce Base Address LSB Register — Index 63h Bit R/W Default 7-0 R/W 00h Description Mapped as Base Address [7:0] 6.2.11 GPIO Pin Set 1, 2 and 3 Polarity Registers — Index F0h, F1h and F2h These registers are used to program the GPIO pin type as polarity inverting or non-inverting. Bit R/W Default 7-0 R/W 00h Description 1: Inverting 0: Non-inverting 6.2.12 Simple I/O Set 1, 2, and 3 Output Enable Registers — Index F3h, F4h and F5h These registers are used to determine the direction of the Simple I/O. Bit R/W Default 7-0 R/W 00h www.ite.com.tw www.iteusa.com Description 0: Input mode 1: Output mode 12 IT8706R V0.1 System Configuration 6.2.13 Panel Button De-bounce Control Register — Index F6h Bit R/W Default 7-3 R/W 0h 2 R/W 0b 1-0 R/W 00b Description Reserved SMI# Output Enable. 0: Disable 1: Enable De-bounce Time Selection 00: 8ms (6ms ignored, 8ms passed) 01: 16ms (12ms ignored, 16ms passed) 10: 32ms (24ms ignored, 21ms passed) 11: 64ms (48ms ignored, 64ms passed) 6.2.14 Panel Button De-bounce Set 1, 2, and 3 Enable Registers — Index F7h, F8h and F9h These registers are used to enable Panel Button De-bounce for each pin. Bit R/W Default 7-0 R/W 00h www.ite.com.tw www.iteusa.com Description 1: Enable 0: Disable 13 IT8706R V0.1 IT8706R www.ite.com.tw www.iteusa.com 14 IT8706R V0.1 Functional Description 7. Functional Description 7.1 LPC Interface The IT8706R supports the peripheral site of the LPC I/F as described in the LPC Interface Specification Rev.1.0 (Sept. 29, 1997). The IT8706R supports the required signals LAD3-0, LFRAME#, LRESET#, LCLK (LCLK is the same as PCICLK.). 7.1.1 LPC Transactions The IT8706R supports some parts of the cycle types described in the LPC I/F specification. I/O read and I/O write cycles are used for the programmed I/O cycles. All of these cycles are characteristic of the single byte transfer. For LPC host I/O read or write transactions, the IT8706R processes a positive decoding, and the LPC interface can respond to the result of the current transaction by sending out SYNC values on LAD[3:0] signals or leave LAD[3:0] tri-state depending on the result. 7.2 General Purpose I/O The IT8706R provides three sets of flexible I/O control and special functions for the system designers via a set of multi-functional General Purpose I/O pins (GPIO). The GPIO functions include the simple I/O function and Panel Button De-bounce. The Simple I/O function includes a set of registers, which correspond to the GPIO pins. All control bits are divided into three registers. The accessed I/O ports are programmable and are three consecutive I/O ports (Base Address+0, Base Address+1, and Base Address+2). The Base Address is programmed on the registers of Simple I/O Base Address LSB and MSB registers (LDN=10h, Index=60h and 61h). The Panel Button De-bounce is an input function. After the panel button de-bounce is enabled, a related status bit will be set when an active pulse is detected on the GPIO pin. The status bits will be cleared by writing 1’s to them. SMI# will be issued if any one of the status bit is set. However, the new setting status will not issue another interrupt unless the previous status bit is cleared before being set. When an active pulse is continuous active after status bits are cleared, another de-bounce operation will be started. www.ite.com.tw www.iteusa.com 15 IT8706R V0.1 IT8706R Simple I/O Register Bit-n Internal-bus Write Polarity DTYPE Output enable 1 GPIO PIN 0 Read SMI# Internal-bus status De-bounce enable De-bounce circuit Panel Button De-bounce Bit-n Read Figure 7-1. General Logic of GPIO Function 7.3 Power On Strapping Options Description Symbol MCI[1:0] Multi-Chips Identification These two power-on strapping bits are used to clarify multiple [1:0] IT8706Rs in a system. Please refer to the register description for details. www.ite.com.tw www.iteusa.com 16 IT8706R V0.1 DC Characteristics 8. DC Characteristics Absolute Maximum Ratings *Comments Power Supply (VCC) -0.5V to 7.0V Input Voltage -0.5V to VCC + 0.5V Output Voltage -0.5V to VCC + 0.5V Storage Temperature -55°C to 125°C Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied, and exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Electrical Characteristics (Operation Condition Vcc=5V ± 5%, Ta = 0°°C to + 70°°C) SYMBOL PARAMETER CONDITION MIN. TYP. MAX. UNIT DIO8 Type Buffer VIL Input Low Voltage - - 0.8 V VIH Input High Voltage 2.2 - - V VOL Output Low Voltage IOL=8mA - - 0.4 V VOH Output High Voltage IOH=-8mA 2.4 - - V VIN=0 - 10 - uA VIN=VCC - - -10 uA - - 20 uA IIL Input Leakage current IIH High Input Leakage current IOZ Tri-state leakage current DIOD8 Type Buffer VIL Input Low Voltage - - 0.8 V VIH Input High Voltage 2.2 - - V VOL Output Low Voltage IOL=8mA - - 0.4 V IIL Low Input Leakage current VIN=0 - 10 uA IIH High Input Leakage current VIN=VCC - - -10 uA IOZ Tri-state leakage current - - 20 uA DI Type Buffer VIL Input Low Voltage - - 0.8 V VIH Input High Voltage 2.2 - - V IIL Input Leakage current VIN=0 - 10 - uA IIH High Input Leakage current VIN=VCC - - -10 uA www.ite.com.tw www.iteusa.com 17 IT8706R V0.1 IT8706R www.ite.com.tw www.iteusa.com 18 IT8706R V0.1 AC Characteristics 9. AC Characteristics t2 0.6VCC t3 0.4VCC p-to-p (minimum) 0.2VCC t1 Figure 9-1. LCLK Waveform Table 9-1. LCLK and LRESET# AC Table Parameter Symbol Min. Typ. Max. Unit t1 LCLK Cycle Time 28 nsec t2 LCLK High Time 11 nsec t3 LCLK Low Time 11 nsec t4 LRESET# Low Pulse Width 1.5 µsec LCLK t2 t3 t1 LPC Signals (Output) LPC Signals (Input) Input Valid t4 t5 Figure 9-2. LPC Waveform Table 9-2. LPC AC Table Parameter Symbol Min. Typ. Max. Unit t1 Float to Active Delay t2 Output Valid Delay 12 nsec t3 Active to Float Delay 6 nsec t4 Input Setup Time 9 nsec t5 Input Hold Time 3 nsec www.ite.com.tw www.iteusa.com nsec 3 19 IT8706R V0.1 IT8706R www.ite.com.tw www.iteusa.com 20 IT8706R V0.1 Package Information 10. Package Information SOP 28 Outline Dimensions unit: inches/mm E HE 15 28 θ L 1 b Detail F 14 D L1 A1 e S A A2 C D y Seating Plane See Detail F Symbol www.ite.com.tw www.iteusa.com Dimension in inches Dimension in mm Min Nom Max Min Nom Max A — — 0.112 — — 2.85 A1 0.004 — — 0.10 — — A2 0.093 0.098 0.103 2.36 2.49 2.62 b 0.014 0.016 0.020 0.36 0.41 0.51 C 0.008 0.010 0.012 0.20 0.25 0.30 D — 0.713 0.728 — 18.11 18.49 E 0.326 0.331 0.336 8.28 8.41 8.53 e 0.044 0.050 0.056 1.12 1.27 1.42 HE 0.453 0.465 0.477 11.51 11.81 12.12 L 0.028 0.036 0.044 0.71 0.91 1.12 L1 0.059 0.067 0.075 1.50 1.70 1.91 S — — 0.047 — — 1.19 y — — 0.004 — — 0.10 θ 0 8 0 21 8 IT8706R V0.1 IT8706R www.ite.com.tw www.iteusa.com 22 IT8706R V0.1 Ordering Information 11. Ordering Information Part No. Package IT8706R 28 SOP www.ite.com.tw www.iteusa.com 23 IT8706R V0.1