INTEL 81341

Intel
®
81341 and Intel
®
81342 I/O
Processors
Datasheet
Product Features
Intel® 81341 I/O Processor contains one
integrated Intel XScale processor
Intel® 81342 I/O Processor contains two
integrated Intel XScale processors
Processor features
— 800 MHz and 1.2 GHz
— ARM* V5TE Compliant
— Instruction/Data Cache: 32 KByte, 4-way
Set Associative, NRU Replacement
Algorithm, Lockable
— Unified Level 2 Cache: 512 KByte Set
Associative, NRU Replacement Algorithm
— 128-Entry Branch Target Buffer
— 8-Entry Write Buffer
— 8-Entry Fill and Pend Buffer
Internal Bus 400 MHz/128-bit
Can support either PCI-X or PCI Express* as
an endpoint
Support for PCI Express* Lane Widths of x1,
x2, x4, x8
Multi-ported Memory Controller
— Intel XScale® processor inputs and north
internal bus, south internal bus and ADMA
input ports
— PC3200 and PC4300 Double Data Rate
(DDR2 400, DDR2 533)
— Up to 4 GB of 64-bit DDR2 400, DDR2 533
— Optional Single-bit Error Correction, Multibit Detection ECC Support
— Supports Registered and Unbuffered DDR2
Memory
— 36-bit Addressable
— 32-bit Memory Support
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Integrated SRAM Memory Controller (1 MB)
Address Translation Unit
— 2 KB or 4 KB Outbound Read Queue
— 4 KB Outbound Write Queue
— 4 KB Inbound Read and Write Queue
Two Programmable 32-bit Timers and
Watchdog Timer
Sixteen General Purpose I/O Pins
Three I C Bus Interface Units
Two UART (16550) Units
— 64 Byte Receive and Transmit FIFOs
— 4 pin Master/Slave Capable
Peripheral Bus Interface
— 8-, 16-bit Data Bus with Two Chip Selects
— 25 Demultiplexed Address Lines
Interrupt Controller Unit
— Four Priority Levels
— Interrupt Pending Register
— Vector Generation
— 16 External Interrupt Pins with High Priority
Interrupt (HPI#)
1357-ball, Flip Chip Ball Grid Array (FCBGA),
37.5 mm x 37.5 mm and 1.0 mm ball pitch
Application DMA Controller
— Three Independent Channels Connected to
the MCU and the South Internal Bus
— 4 KByte Data Transfer Queue
— CRC 32C Calculation
— Performs Optional XOR on Read Data
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December 2007
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Corporation in the U.S. and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2007, Intel Corporation. All rights reserved.
Legal Lines and Disclaimers
Intel® 81341 and 81342 I/O Processors
Datasheet
2
December 2007
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Contents—Intel® 81341 and 81342
Contents
1.0 Introduction ..............................................................................................................7
1.1
About This Document...........................................................................................7
1.1.1 Terminology ............................................................................................7
1.1.2 Other Relevant Documents ........................................................................7
2.0 Features ....................................................................................................................9
2.1 Intel 81341 and Intel 81342 I/O Processors Features...........................................9
2.1.1 Host Interface........................................................................................ 11
2.1.2 Internal Busses...................................................................................... 12
2.1.3 Application DMA Controllers ..................................................................... 12
2.1.4 Address Translation Unit ......................................................................... 12
2.1.5 Messaging Unit ...................................................................................... 12
2.1.6 DDR2 Memory Controller......................................................................... 13
2.1.7 SRAM Memory Controller......................................................................... 13
2.1.8 Peripheral Bus Interface .......................................................................... 13
2.1.9 I C Bus Interface Units ........................................................................... 13
2.1.10 UART Units ............................................................................................ 13
2.1.11 Interrupt Controller Unit.......................................................................... 13
2.1.12 XSI System Controller............................................................................. 14
2.1.13 Inter-Processor Communication................................................................ 14
2.1.14 Timers .................................................................................................. 14
2.1.15 GPIO .................................................................................................... 14
3.0 Package Information ............................................................................................... 15
3.1 Package Introduction ......................................................................................... 15
3.2 Functional Signal Definitions ............................................................................... 15
3.2.1 Signal Pin Descriptions............................................................................ 15
4.0 Electrical Specifications ........................................................................................... 64
4.1 V
Pin Requirements .................................................................................... 66
4.2 Targeted DC Specifications ................................................................................. 67
4.3 Targeted AC Specifications ................................................................................. 69
4.3.1 Clock Signal Timings............................................................................... 69
4.3.2 DDR2 SDRAM Interface Signal Timings...................................................... 72
4.3.3 Peripheral Bus Interface Signal Timings..................................................... 73
4.3.4 I C/SMBus Interface Signal Timings.......................................................... 74
4.3.5 PCI Bus Interface Signal Timings .............................................................. 75
4.3.6 PCI Express* Differential Transmitter (Tx) Output Specifications................... 76
4.3.7 PCI Express* Differential Receiver (Rx) Input Specifications ......................... 78
4.3.8 Boundary Scan Test Signal Timings .......................................................... 79
4.4 AC Timing Waveforms........................................................................................ 80
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CCPLL
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Intel® 81341 and 81342 I/O Processors
Datasheet
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Intel® 81341 and 81342—Contents
Figures
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Intel® 81341 I/O Processor Functional Block Diagram (Single processor).........................10
Intel® 81342 I/O Processor Functional Block Diagram (Two processor) ...........................11
1357-Lead FCBGA Package (Top and Bottom Views) .....................................................36
Intel® 81341 and 81342 I/O processors Ballout— Package Top (Left Side) ......................38
Intel® 81341 and 81342 I/O processors Ballout— Package Top (Right Side) ....................39
Intel® 81341 and 81342 I/O processors Ballout — Package Bottom (Left Side) ................40
Intel® 81341 and 81342 I/O processors Ballout — Package Bottom (Right Side) ..............41
V
Low-Pass Filter..........................................................................................66
V
,V
Low-Pass Filter .........................................................................66
Clock Timing Measurement Waveforms........................................................................80
Output Timing Measurement Waveforms .....................................................................80
Input Timing Measurement Waveforms........................................................................81
I C Interface Signal Timings ......................................................................................81
DDR2 SDRAM Write Timings ......................................................................................82
DQS Falling Edge Output Access Time to/from M_CK Rising Edge ....................................82
DDR2 SDRAM Read Timings .......................................................................................83
AC Test Load for all Signals Except PCI, PCI-Express and DDR2 ......................................83
AC Test Load for DDR2 SDRAM Signals........................................................................83
PCI/PCI-X TOV(max) Rising Edge AC Test Load ............................................................84
PCI/PCI-X TOV(max) Falling Edge AC Test Load............................................................84
PCI/PCI-X TOV(min) AC Test Load ..............................................................................84
Transmitter Test Load (100 Ω diff Load) ......................................................................84
Transmitter Eye Diagram...........................................................................................85
Receiver Eye Opening (Differential).............................................................................85
PBI Output Timings...................................................................................................86
PBI External Device Timings (Flash) ............................................................................87
CC3P3PLLX
CC1P2PLLD
CC1P2PLLP
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Intel® 81341 and 81342 I/O Processors
Datasheet
4
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Contents—Intel® 81341 and 81342
Tables
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3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Pin Description Nomenclature .................................................................................... 15
DDR2 SDRAM Signals ............................................................................................... 16
Peripheral Bus Interface Signals................................................................................. 18
Compact PCI Hot Swap Signals .................................................................................. 19
PCI Bus Signals ....................................................................................................... 20
PCI Express* Signals ................................................................................................ 23
Interrupt Signals...................................................................................................... 24
I C and SM Bus Signals ............................................................................................ 25
UART Signals........................................................................................................... 26
Miscellaneous Signals ............................................................................................... 28
Power and Ground Signals......................................................................................... 29
Reset Strap Signals .................................................................................................. 30
Functional Pin Mode Behavior .................................................................................... 33
Intel® 81341 and 81342 I/O processors 1357-Lead Package—Alphabetical Ball Listings .... 42
Intel® 81341 and 81342 I/O processors 1357-Lead Package—Alphabetical Signal Listings. 53
Absolute Maximum Ratings ....................................................................................... 64
Operating Conditions ................................................................................................ 65
DC Characteristics.................................................................................................... 67
I Characteristics.................................................................................................... 68
PCI Clock Timings .................................................................................................... 69
PCI Express* Clock Timings....................................................................................... 70
DDR2 Output Clock Timings....................................................................................... 71
DDR2 SDRAM Signal Timings ..................................................................................... 72
Peripheral Bus Interface Signal Timings....................................................................... 73
I C/SMBus Signal Timings ......................................................................................... 74
PCI Signal Timings ................................................................................................... 75
PCI Express* Rx Input Specifications .......................................................................... 76
PCI Express* Tx Output Specifications ........................................................................ 77
PCI Express* Rx Input Specifications .......................................................................... 78
Boundary Scan Test Signal Timings ............................................................................ 79
AC Measurement Conditions ...................................................................................... 83
2
CC
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Datasheet
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Intel® 81341 and 81342—Contents
Revision History
Date
Revision Description
December 2007
003
Revised for 4 GB memory support.
Updated Legal page 2.
Edited text in Section 2.1.2.
Revise PCIXCAP description in Table 5.
March 2007
002
Updated Table 18 for Cgp, Cpcix, Cddr2 and Lpin values.
Revised Table 17 for Tcase (Tc) maximum value to 100C.
Revised Figure 27.
October 2006
001
Initial release
Intel® 81341 and 81342 I/O Processors
Datasheet
6
December 2007
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Introduction—Intel® 81341 and 81342
1.0
Introduction
1.1
About This Document
This document is a reference guide for the external architecture of the
Intel 81341 and 81342 I/O Processors (also known as the 81341 and 81342).
®
1.1.1
Terminology
To aid the discussion of the Intel 81341 and 81342 I/O Processors architecture, the
following terminology is used:
Downstream
At or toward a PCI bus with a higher number (after
configuration)
Word
16 bits of data
Dword
32 bits of data
Qword
64 bits of data
Host processor
Processor located upstream from the Intel 81341 and 81342
I/O Processors
Local processor
Intel XScale processor within the Intel 81341 and 81342 I/O
Processors
Local bus
Intel 81341 and 81342 I/O Processors internal bus
Local memory
Memory subsystem on the Intel XScale processor, DDR2
SDRAM or Peripheral Bus Interface busses
Upstream
At or toward a PCI bus with a lower number (after configuration)
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1.1.2
Other Relevant Documents
1. Intel XScale Microarchitecture Developer’s Manual (Order Number 273473)—Intel
Corporation
2. PCI Local Bus Specification, Revision 2.3—PCI Special Interest Group
3. PCI Hot-Plug Specification, Revision 1.0—PCI Special Interest Group
4. PCI Bus Power Management Interface Specification, Revision 1.1—PCI Special
Interest Group
5. PCI Express Specification, Revision 1.0a—PCI Special Interest Group
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Datasheet
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Intel® 81341 and 81342—Introduction
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Intel® 81341 and 81342 I/O Processors
Datasheet
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Features—Intel® 81341 and 81342
2.0
Features
81341 and 81342 I/O Processors are a single- or dual-function PCI device that
integrates one or two Intel XScale processor(s) with intelligent peripherals including a
PCI bus bridge. The 81341 and 81342 I/O Processors also support two internal busses:
North XSI bus and South XSI bus. With the two internal busses, transactions can take
place simultaneously on each bus. The north XSI bus provides one or two Intel XScale
processor(s) with low-latency access to either the DDR2 SDRAM Memory Controller or
the on-chip SRAM Memory Controller. Peripherals that generate large burst transactions
are located on the south XSI bus, thus allowing the two Intel XScale processors
exclusive access to the north XSI bus.
81341 and 81342 I/O Processors consolidate the following features into a single
system:
• PCI–Local Memory Bus Address Translation Unit, function 0 programming interface
• Messaging Unit, function 0 programming interface
• Application Direct Memory Access (DMA) Controller (including offload for up to a
16-source XOR operation)
• Peripheral Bus Interface Unit
• Integrated DDR2 Memory Controller
• Integrated SRAM Memory Controller
• Two programmable timers per Intel XScale processor
• Watchdog timer per Intel XScale processor
• Three I C Bus Interface Units
• Two Serial Port Units
• Sixteen General-Purpose Input/Output (GPIO) ports
• Internal North Bus–South Bus Bridge
It is an integrated processor that addresses the needs of intelligent I/O storage
applications and helps reduce intelligent I/O system costs.
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2.1
Intel® 81341 and 81342 I/O Processors Features
Figure 1 shows the Intel® 81341 I/O Processor single-processor block diagram.
Figure 2 shows the Intel® 81342 I/O Processor two-processor block diagram.
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Intel® 81341 and 81342—Features
Figure 1.
Intel® 81341 I/O Processor Functional Block Diagram (Single processor)
Intel
XScale
Core
Interrupt
( Core ID = 0H )
Controller 512K L 2 Cache
Timers
128 - Bit North Internal Bus
Multi - Port
SRAM
Memory
Controller
Multi - Port
DDR II SDRAM
Memory Controller
72- Bit
I/F
Bridge
PCI- X or PCI - E
PCI - E
Host Interface
( ATU, CHAP ) ,
Host Interface
( ATU, CHAP )
Three
Application
DMA
Channels
128 - Bit South Internal Bus
PBI
Unit
( Flash)
SMBus
Unit
APB
Three I 2 C
Bus
Interface
Two
UARTs
Intel® 81341
I/ O Processor
16 - Bit I /F
Datasheet
10
SMBus
I 2 C Bus
Serial Bus
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Features—Intel® 81341 and 81342
Figure 2.
Intel® 81342 I/O Processor Functional Block Diagram (Two processor)
Intel
XScale
Core
(coreID = 1H)
512K L2 Cache
Timers
Timers
Interrupt
Controller
Interrupt
Controller
Inter-Core
Interrupt
Inter-Core
Interrupt
Intel
XScale
Core
(coreID = 0H)
512K L2 Cache
128-Bit North Internal Bus
Multi-Port
SRAM
Memory
Controller
Multi-Port
DDR II SDRAM
Memory Controller
72-Bit
I/F
Three
Application
DMA
Channels
Bridge
PCI-X or PCI-E
PCI-E
Host Interface
(ATU, TPMI,
CHAP)
128-Bit South Internal Bus
PBI
Unit
(Flash)
Host Interface
(ATU, TPMIs,
CHAP)
SMBus
Unit
APB
Three I2 C
Bus
Interface
Two
UARTs
I2 C Bus
Serial Bus
Intel® 81342
I/O Processor
16-Bit I/F
SMBus
Note:
The subsections that follow give a brief overview of each feature. Refer to the
appropriate chapter in the Intel 81341 and 81342 I/O Processors Developer’s Manual
for full technical descriptions.
2.1.1
Host Interface
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81341 and 81342 I/O Processors can be set up as either a single or dual-function PCI
device, providing PCI-X or PCI Express* interface or both PCI-X and PCI Express*
interfaces. The PCI interface is selected as a reset option. Each function is
independently controlled and provides the TPMI interface.
Intel 81341 and 81342 I/O Processors are a single-function PCI device that provides
either a PCI-X or PCI Express* host interface. The Address Translation Unit (ATU) and
the Messaging Unit (MU) provide the programming interface between the host
processor and the Intel 81341 and 81342 I/O Processors. When PCI-X 1.0b is
selected as the upstream (host) I/O interface, PCI Express* is available as a private
(not visible to the host), downstream I/O interface. Likewise, when PCI Express* is
selected as the upstream I/O interface, PCI-X 1.0b is available as a private,
downstream I/O interface. The selection of the upstream I/O interface is a reset strap
option.
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Intel® 81341 and 81342—Features
2.1.2
Internal Busses
The 81341 and 81342 I/O Processors are built around two internal busses: north
internal bus and south internal bus. The two busses use the same bus protocol. The
north internal bus is 128 bits wide and operates at 400 MHz. The north bus connects
the two Intel XScale processors, which have direct access to the DDR2 SDRAM and
SRAM. The north XSI bus is designed to provide the two Intel XScale processors with
low-latency access.
The south internal bus is 128 bits wide and operates at 400 MHz. The south XSI bus
provides the data paths for burst transactions generated by the DMAs. The south XSI
bus internal address and data busses are parity-protected on a byte-wise basis. Agents
on the south XSI bus can generate and check address and data parity. The point-topoint interfaces between the agents and the DDR2 and SRAM Memory Controllers are
also parity-protected on a byte-wise basis.
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2.1.3
Application DMA Controllers
There are three Application DMA Controllers. The Application DMA Controller is dualported—with one of its ports connected to the south XSI bus and the other port to the
DDR2 SDRAM Memory Controller. This Application DMA Controller allows low-latency,
high-throughput data transfers between PCI bus agents and the DDR2 memory. The
DMA controller also allows data transfer between DDR2 Memory. The DMA Controller
supports chaining and unaligned data transfers. It is programmable through the Intel
XScale processor and the host processor.
In addition to simple data transfers, the ADMA performs XOR operations with up to 16
sources.
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2.1.4
Address Translation Unit
The Address Translation Unit (ATU) allows PCI transactions direct access to the 81341
and 81342 I/O Processors local memory. The ATU provides interface for the RAID
Controller PCI function. The ATU supports transactions between PCI address space and
the 81341 and 81342 I/O Processors address space. Address translation is controlled
through programmable registers accessible from both the PCI interface and the Intel
XScale processor. Dual access to registers allows flexibility in mapping the two
address spaces. The ATU also supports the following extended capability configuration
headers:
1. Power Management header, as defined by PCI Bus Power Management Interface
Specification, Revision 1.1.
2. Message Signaled Interrupt capability structure, as specified in PCI Local Bus
Specification, Revision 2.3.
3. PCI-X Capabilities List Item, as specified in the PCI-X Addendum to the Local Bus
Specification, Revision 1.0b.
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2.1.5
Datasheet
12
Messaging Unit
The Messaging Unit (MU) provides data transfer between the PCI system and the
81341 and 81342 I/O Processors. It uses interrupts to notify each system when new
data arrives. The MU has four messaging mechanisms: Message Registers, Doorbell
Registers, Circular Queues, and Index Registers. Each allows a host processor or
external PCI device and the 81341 and 81342 I/O Processors to communicate through
message passing and interrupt generation. The MU, in conjunction with the ATU, exists
as the PCI interface for PCI function 0 when function 0 is set up as a RAID controller.
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Features—Intel® 81341 and 81342
2.1.6
DDR2 Memory Controller
2.1.7
SRAM Memory Controller
2.1.8
Peripheral Bus Interface
2.1.9
I2C Bus Interface Units
The DDR2 Memory Controller allows direct control of the 400/533 MHz DDR2 SDRAM
memory subsystem. It features programmable chip selects and support for errorcorrection codes (ECC). The DDR2 Memory Controller is multi-ported with the following
interfaces: south internal bus, ADMA controllers, north internal bus. The memory
controller interface configuration support includes unbuffered DIMMs, registered
DIMMs, and discrete DDR2 SDRAM devices.
The SRAM Memory Controller allows direct control of a 1.0 MByte SRAM memory
subsystem. It supports error correction codes (ECC). The SRAM is used to store
firmware code, I/O exchange contexts and for general-purpose data storage.
The Peripheral Bus Interface Unit is a data communication path to the flash memory
components or other peripherals of a 81341 and 81342 I/O Processors hardware
system. The PBI includes support for either 8- or 16-bit devices. To perform these tasks
at high bandwidth, the bus features a burst-transfer capability which allows successive
8/16-bit data transfers.
There are three I C (Inter-Integrated Circuit) Bus Interface Units that allow the Intel
XScale processor to serve as a master and slave device residing on the I C bus. The
I C0 allows the I/O processor to interface to a Storage Enclosure Processor (SEP). The
bus allows the 81341 and 81342 I/O Processors to interface to other I C peripherals
and
microcontrollers for system management functions. For more information, refer to
I2C Peripherals for Microcontrollers (Philips Semiconductor) .
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2
1
2.1.10
UART Units
The 81341 and 81342 I/O Processors includes two UART units. The UART units allow
the two Intel XScale processors to serve as a master and slave device residing on the
UART bus. The UART units use a serial bus consisting of a two-pin interface. UART0
allows the 81341 and 81342 I/O Processors to interface to a console port for
debugging. Also refer to the National Semiconductor* 16550 device specification .
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2.1.11
Interrupt Controller Unit
Each Intel XScale processor supports an Interrupt Controller Unit (ICU). The ICU
aggregates interrupt sources both external and internal sources of the 81341 and
81342 I/O Processors to the Intel XScale processor. The ICU supports highperformance interrupt processing with direct interrupt service routine vector generation
on a per-source basis. Each source has programmability for masking, processor
interrupt input, and priority.
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2.1.12
XSI System Controller
Each XSI bus (north and south) employs an XSI system controller. The XSI system
controller observes all the address or data bus requests from requestors and
completors connected to the XSI bus. The XSI system controller handles XSI address
1. http://www.semiconductors.philips.com/buses/i2c/
2. http://www.national.com/pf/PC/PC16550D.html
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Intel® 81341 and 81342—Features
bus arbitration, XSI data bus arbitration, framing Address bus cycles, and framing Data
bus cycles. The XSI system controller provides the shared address and shared data
paths from/to units.
2.1.13
Inter-Processor Communication
Each Intel XScale processor can interrupt or issue a reset to the second Intel XScale
processor. Each processor can generate up to 32 interrupts to the second processor.
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2.1.14
Timers
2.1.15
GPIO
Datasheet
14
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The 81341 and 81342 I/O Processors support two programmable 32-bit timers per
processor. The 81341 and 81342 I/O Processors also support one watchdog timer per
processor.
The 81341 and 81342 I/O Processors includes sixteen General-Purpose
I/O (GPIO) pins.
December 2007
Order Number: 315038-003US
Package Information—Intel® 81341 and 81342
3.0
Package Information
3.1
Package Introduction
The Intel 81341 and Intel 81342 I/O Processors is offered in a 1357-ball FCBGA5
package.
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3.2
Functional Signal Definitions
3.2.1
Signal Pin Descriptions
Table 1.
Pin Description Nomenclature
This section defines the pins and signals.
Symbol
Description
I
O
I/O
OD
PWR
GND
—
Input pin only
Output pin only
Pin can be either an input or an output
Open-drain pin
Power pin
Ground pin
Pin must be connected as described
Synchronous. Signal meets timings relative to a clock.
• Sync (P): Synchronous to P_CLKIN
• Sync (M): Synchronous to M_CK[2:0] / M_CK#[2:0]
• Sync (T): Synchronous to TCK
Asynchronous. Inputs can be asynchronous relative to all clocks. All asynchronous signals
are level-sensitive.
Indicates read or write capability.
The pin is reset with WARM_RST# or P_RST#.
The pin is reset with M_RST#. M_RST# is asserted when the memory subsystem is reset.
The pin is reset with PB_RSTOUT#. PB_RSTOUT# is asserted when the Peripheral Bus
Interface subsystem is reset.
The pin is reset with TRST#.
The pin is an active-low signal.
The pin is a differential signal pair.
• “P” at the end of a differential pin name indicates “positive”.
• “N” at the end of a differential pin name indicates “negative”.
Sync (...)
Async
R/W
Rst (P)
Rst (M)
Rst (PB)
Rst (T)
ActLow
Diff
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Datasheet
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Intel® 81341 and 81342—Package Information
Table 2.
Datasheet
16
DDR2 SDRAM Signals (Sheet 1 of 2)
Name
Count
Type
Description
M_CK[2:0],
M_CK#[2:0]
6
O
Diff
Memory Clockout: is used to provide the three differential clock
pairs to the unbuffered DIMM for the external SDRAM memory
subsystem. Registered DIMMs use only the M_CK[0]/M_CK#[0]
pair, which drives the input to the on-DIMM PLL.
M_RST#
1
MA[14:0]a
14
BA[2:0]
3
RAS#
1
CAS#
1
WE#
1
CS[1:0]#
2
CKE[1:0]
2
DQ[63:0]
64
CB[7:0]
8
DQS[8:0],
DQS#[8:0]
18
DM[8:0]
9
M_VREF
1
I
ODT[1:0]
2
O
Sync (M)
Rst (M)
O
Async
ActLow
O
Sync (M)
Rst (M)
O
Sync (M)
Rst (M)
O
Sync (M)
Rst (M)
ActLow
O
Sync (M)
Rst (M)
ActLow
O
Sync (M)
Rst (M)
ActLow
O
Sync (M)
Rst (M)
ActLow
O
Sync (M)
Rst (M)
I/O
Sync (M)
Rst (M)
I/O
Sync (M)
Rst (M)
I/O
Sync (M)
Rst (M)
Diff
O
Sync (M)
Rst (M)
Memory Reset: indicates that the memory subsystem has been
reset. It is used to re-initialize registered DIMMs.
Memory Address Bus: carries the multiplexed row and column
addresses to the SDRAM memory banks. Auto-precharge is not
supported.
SDRAM Bank Address: controls which of the internal banks to read
or write. BA[1:0] are used for 512 Mbit technology memory.
BA[2:0] are used for 1 Gbit technology memory.
SDRAM Row Address Strobe: indicates the presence of a valid row
address on the Multiplexed Address Bus MA[13:0].
SDRAM Column Address Strobe: indicates the presence of a valid
column address on the Multiplexed Address Bus MA[13:0].
SDRAM Write Enable: indicates whether the current memory
transaction is a read or write operation.
SDRAM Chip Select: enables the SDRAM devices for a memory
access. One for each physical bank.
SDRAM Clock Enable enables: the clocks for the SDRAM memory.
Deasserting places the SDRAM in self-refresh mode. One for each
physical bank.
SDRAM Data Bus: carries 64-bit data to and from memory. During
the data cycle, read or write data is present on one or more
contiguous bytes. During write operations, unused pins drive to
determinate values.
SDRAM ECC Check Bits: carry the 8-bit ECC code to and from
memory during data cycles.
SDRAM Data Strobes: carry differential or single-ended strobe
signals, output in write mode, and input in read mode for source
synchronous data transfer.
SDRAM Data Mask: controls which bytes on the data bus are to be
written. When DM[8:0] is asserted, the SDRAM devices do not
accept valid data from the byte lanes.
SDRAM Voltage Reference: is used to supply the input switching
reference voltage for the memory input signals.
On-Die Termination: is used to turn on SDRAM on-die termination
during writes.
December 2007
Order Number: 315038-003US
Package Information—Intel® 81341 and 81342
Table 2.
DDR2 SDRAM Signals (Sheet 2 of 2)
Name
Count
Type
M_CAL[0]
1
O
M_CAL[1]
1
O
Description
Memory Calibration: Connected to an external calibration resistor.
Memory output drivers reference the resistor to dynamically adjust
drive strength to compensate for temperature and voltage
variations. This pin connected through a 24.9 ohm 1% resistor to
ground.
Memory Calibration: Connected to an external calibration resistor.
Memory output drivers reference the resistor to dynamically adjust
ODT resistance to compensate for temperature and voltage
variations. This pin connected through a 301 ohm 1% resistor to
ground.
Total
135
a. MA[14] was added for 4GB memory support. When 4GB memory is not used this pin is NC.
December 2007
Order Number: 315038-003US
Datasheet
17
Intel® 81341 and 81342—Package Information
Table 3.
Peripheral Bus Interface Signals
Name
Datasheet
18
Count
A[24:0]
25
D[15:0]
16
POE#
1
PWE#
1
PCE[1:0]#
2
PB_RSTOUT#
1
Total
46
Type
Description
O
Peripheral Address Bus: carries the address bits for the current
Rst (PB) access. The PBI interface can address up to 32 MBytes.
Peripheral Data Bus: carries read or write data to and from
I/O
During write operations to 8-bit wide memory regions, the
Rst (PB) memory.
PBI drives unused bus pins to determinate values.
Peripheral Output Enable: indicates whether bus access is write or
read with respect to I/O processor and is valid during entire bus
O
This pin can be used to control output enable on a
Rst (PB) access.
device.
ActLow peripheral
0 = Read
1 = Write
Peripheral Write Enable: indicates to the peripheral device whether
or not to write data to the addressed space. This pin can be used to
O
Rst (PB) control the write enable on the peripheral device.
ActLow 0 = Write
1 = Read
Peripheral Chip Enable: Specifies which of the two memory address
ranges are associated with the current bus access. The pin remains
O
Rst (PB) valid during the entire bus access.
ActLow Note: These pins must be pulled up to VCC3P3 with external 8.2K
ohm 5%, 1/16 W resistors for proper operation.
O
Peripheral Bus Reset Out: can be used to reset the peripheral
ActLow device. It has the same timing as the internal bus reset.
December 2007
Order Number: 315038-003US
Package Information—Intel® 81341 and 81342
Table 4.
Compact PCI Hot Swap Signals
Name
Count
HS_ENUM#
1
HS_LSTAT
1
HS_LED_OUT
1
HS_FREQ[1:0]
/
CR_FREQ[1:0]
2
Type
Description
Hot Swap Event: Conditionally asserted to notify system host that
OD either a board has been freshly inserted or is about to be extracted.
Rst (P) This signal informs the system host that the configuration of the
ActLow system has changed. The system host then performs any necessary
maintenance such as installing or quiesing a device driver.
Hot Swap Latch Status: Input indicating state of the ejector switch.
I
0 = Indicates the ejector switch is closed.
Rst (P) 1 = Indicates the ejector switch is open.
If Compact PCI Hot Swap not supported, tie this signal low.
O
Hot Swap LED Output: outputs a logic one to illuminate the Hot
Rst (P) Swap blue LED.
Hot Swap Frequency: In Hot Swap mode, these pins are inputs,
determining the bus frequency and mode during a PCI-X hot swap
event. These are valid only when PCIX_EP# = 0 and
HS_SM# = 0.
00 =133 MHz PCI-X
01 =100 MHz PCI-X
10 = 66 MHz PCI-X
I/O 11 = 33 or 66 MHz. PCI (frequency depends on P_M66EN)
Rst (P) Central Resource Frequency: While in Central Resource mode,
these pins are outputs, which control the external PCI-X clock
generator. These are valid only when PCIX_EP# = 1.
00 = 133 MHz
Total
December 2007
Order Number: 315038-003US
5
01 =100 MHz
10 =66 MHz
11 =33 MHz
• These pins have internal pull-ups.
Datasheet
19
Intel® 81341 and 81342—Package Information
Table 5.
Datasheet
20
PCI Bus Signals (Sheet 1 of 3)
Name
Count
P_AD[63:32]
32
P_AD[31:0]
32
P_CBE[7]#
1
P_CBE[6]#
1
P_CBE[5]#
1
P_CBE[4]#
1
P_CBE[3]#
1
P_CBE[2]#
1
P_CBE[1]#
1
P_CBE[0]#
1
P_PAR64
1
P_REQ64#
1
P_ACK64#
1
P_PAR
1
P_FRAME#
1
Type
I/O
Sync (P)
Rst (P)
I/O
Sync (P)
Rst (P)
I/O
Sync (P)
Rst (P)
ActLow
I/O
Sync (P)
Rst (P)
ActLow
I/O
Sync (P)
Rst (P)
ActLow
I/O
Sync (P)
Rst (P)
ActLow
I/O
Sync (P)
Rst (P)
ActLow
I/O
Sync (P)
Rst (P)
ActLow
I/O
Sync (P)
Rst (P)
ActLow
I/O
Sync (P)
Rst (P)
ActLow
I/O
Sync (P)
Rst (P)
I/O
Sync (P)
Rst (P)
ActLow
I/O
Sync (P)
Rst (P)
ActLow
I/O
Sync (P)
Rst (P)
I/O
Sync (P)
Rst (P)
ActLow
Description
PCI Address/Data: is the upper 32 bits of the PCI data bus driven
during the data phase.
PCI Address/Data: is the multiplexed PCI address and lower 32 bits
of the data bus.
PCI Bus Command and Byte Enables: are multiplexed on the same
PCI pins. During the address phase, they define the bus command.
During the data phase, they are used as byte enables.
PCI Bus Command and Byte Enables: are multiplexed on the same
PCI pins. During the address phase, they define the bus command.
During the data phase, they are used as byte enables.
PCI Bus Command and Byte Enables: are multiplexed on the same
PCI pins. During the address phase, they define the bus command.
During the data phase, they are used as byte enables.
PCI Bus Command and Byte Enables: are multiplexed on the same
PCI pins. During the address phase, they define the bus command.
During the data phase, they are used as byte enables.
PCI Bus Command and Byte Enables: are multiplexed on the same
PCI pins. During the address phase, they define the bus command.
During the data phase, they are used as byte enables.
PCI Bus Command and Byte Enables: are multiplexed on the same
PCI pins. During the address phase, they define the bus command.
During the data phase, they are used as byte enables.
PCI Bus Command and Byte Enables: are multiplexed on the same
PCI pins. During the address phase, they define the bus command.
During the data phase, they are used as byte enables.
PCI Bus Command and Byte Enables: are multiplexed on the same
PCI pins. During the address phase, they define the bus command.
During the data phase, they are used as byte enables.
PCI Bus Upper DWORD Parity is even parity across P_AD[63:32]
and P_CBE_#[7:4].
PCI Bus Request 64-Bit Transfer indicates the attempt of a 64-bit
transaction on the PCI bus. When the target is 64-bit capable, the
target acknowledges the attempt with the assertion of P_ACK64_#.
PCI Bus Acknowledge 64-Bit Transfer indicates that the device has
positively decoded its address as the target of the current access
and the target is willing to transfer data using the full 64-bit data
bus.
PCI Bus Parity is even parity across P_AD[31:0] and
P_CBE_#[3:0].
PCI Bus Cycle Frame is asserted to indicate the beginning and
duration of an access.
December 2007
Order Number: 315038-003US
Package Information—Intel® 81341 and 81342
Table 5.
PCI Bus Signals (Sheet 2 of 3)
Name
Count
Type
Description
P_IRDY#
1
I/O
Sync (P)
Rst (P)
ActLow
P_TRDY#
1
I/O
Sync (P)
Rst (P)
ActLow
PCI Bus Initiator Ready indicates the initiating agent’s ability to
complete the current data phase of the transaction. During a write,
it indicates that valid data is present on the address/data bus.
During a read, it indicates that the processor is ready to accept the
data.
PCI Bus Target Ready indicates the target agent’s ability to
complete the current data phase of the transaction. During a read,
it indicates that valid data is present on the address/data bus.
During a write, it indicates that the target is ready to accept the
data.
P_STOP#
1
P_DEVSEL#
1
P_SERR#
1
I/O
Sync (P)
Rst (P)
ActLow
I/O
Sync (P)
Rst (P)
ActLow
I/O
OD
Sync (P)
Rst (P)
ActLow
P_RSTOUT#
1
O
Async
ActLow
P_PERR#
1
I/O
Sync (P)
Rst (P)
ActLow
P_M66EN
1
I
P_IDSEL
1
I
Sync (P)
P_GNT[0]# /
P_REQ#
1
O
Sync (P)
ActLow
P_REQ[0]# /
P_GNT#
1
I
Sync (P)
Rst (P)
ActLow
December 2007
Order Number: 315038-003US
PCI Bus Stop indicates a request to stop the current transaction on
the PCI bus.
PCI Bus Device Select is driven by a target agent that has
successfully decoded the address. As an input, it indicates whether
or not an agent has been selected.
PCI Bus System Error is driven for address parity errors on the PCI
bus.
PCI Reset Out is based on P_RST# and WARM_RST#. It brings
PCI-specific registers, sequencers, and signals to a consistent state.
When either P_RST# or WARM_RST# is asserted, it causes
P_RSTOUT# to assert and:
• PCI output signals are driven to a known consistent state.
• PCI bus interface output signals are three-stated.
• Open-drain signals such as P_SERR_# are floated.
P_RSTOUT# can be asynchronous to P_CLK when asserted or
deasserted.
PCI Bus Parity Error is asserted when a data parity error occurs
during a PCI bus transaction.
PCI Bus 66 MHz Enable indicates the speed of the PCI bus. When
this signal is sampled high, the PCI bus speed is 66 MHz; when low,
the bus speed is 33 MHz.
PCI Bus Initialization
Device Select is used to select the Intel®
81341 and Intel® 81342 I/O Processors during a configuration read
or write.
Note: In central resource mode this pin must be pulled down to
VSS with an external 4.7K ohm 5%, 1/16 W resistor for
proper operation.
PCI Bus Grant:
• Internal arbiter mode: This is one of four output grant signals
from the internal arbiter.
PCI Bus Request:
• External arbiter mode: This is the output request signal for the
ATU.
PCI Bus Request:
• Internal arbiter mode: This is one of four input request signals
to the internal arbiter.
PCI Bus Grant:
• External arbiter mode: This is the input grant signal to the ATU.
Datasheet
21
Intel® 81341 and 81342—Package Information
Table 5.
PCI Bus Signals (Sheet 3 of 3)
Name
Count
Type
P_GNT[3:1]#
3
O
Sync (P)
ActLow
P_REQ[3:1]#
3
I
Sync (P)
Rst (P)
ActLow
P_PCIXCAP
1
I
P_BMI
1
O
Sync (P)
Rst (P)
P_CAL[0]
1
O
P_CAL[1]
1
O
P_CAL[2]
1
O
P_CLKIN
1
I
P_CLKOUT
1
O
P_CLKO[3:0]
4
O
Total
Datasheet
22
105
Description
PCI Bus Grant:
• External arbiter mode: Not used
• Internal arbiter mode: These are three of four output grant
signals from the internal arbiter.
PCI Bus Request:
• External arbiter mode: Not used
• Internal arbiter mode: These are three of four input request
signals to the internal arbiter.
PCI-X Capability: Refer to the Intel® 81341 and Intel® 81342 I/O
Processors Specification Update for more details.
PCI Bus Master Indicator indicates that the I/O processor is
mastering a transaction on the PCI bus.
PCI Calibration is connected to an external calibration resistor. The
VCCVIO PCI output drivers reference the resistor to dynamically
adjust the drive strength to compensate for voltage and
temperature variations. This pin is connected through a 22.1 ohm
1% resistor to ground.
PCI Calibration is connected to an external calibration resistor. The
PCI output drivers reference the resistor to dynamically adjust the
ODT resistance to compensate for voltage and temperature
variations. This pin is connected through a 121 ohm 1% resistor to
ground.
PCI Calibration is connected to an external calibration resistor. The
VCC3P3 PCI output drivers reference the resistor to dynamically
adjust the drive strength to compensate for voltage and
temperature variations. This pin is connected through a 22.1 ohm
1% resistor to ground.
PCI Bus Input Clock provides the AC timing reference for all PCI
transactions.
PCI Bus Output Clock: When REFCLKN/REFCLKP are used, the I/O
processor can generate the PCI output clocks. This pin is then
connected to P_CLKIN and trace length matched to
P_CLKO[3:0].
PCI Bus Output Clocks: When REFCLKN/REFCLKP are used, the I/
O processor can generate the PCI output clocks. These pins then
provide the PCI clocks to devices on the PCI bus.
December 2007
Order Number: 315038-003US
Package Information—Intel® 81341 and 81342
Table 6.
PCI Express* Signals
Name
REFCLKP,
REFCLKN
PETP[7:0],
PETN[7:0]
PERP[7:0],
PERN[7:0]
Count
Type
Description
2
16
I
Diff
O
Diff
I
Diff
PE_CALP,
PE_CALN
2
I/O
Total
36
PCI Express* Clock is the 100 MHz differential input reference clock
for the PCI Express* interface.
PCI Express* Transmit carries the differential output serial data and
embedded clock for the PCI Express* interface.
PCI Express* Receive carries the differential input serial data and
embedded clock for the PCI Express* interface.
PCI Express* Calibration pins are connected to an external
calibration resistor. The PCI Express* output drivers can reference
the resistor to dynamically adjust their slew rate and drive strength
to compensate for voltage and temperature variations. A 1.4K ohm
1% resistor is connected between these two pins.
December 2007
Order Number: 315038-003US
16
Datasheet
23
Intel® 81341 and 81342—Package Information
Table 7.
Interrupt Signals
Name
Type
4
OD
I
I/O
Async
Rst (P)
ActLow
4
I
I/O
Async
ActLow
GPIO[7:0] /
XINT[15:8]# /
PMONOUT
8
I/O
I
O
Async
Rst (P)
HPI#
1
NMI0#
1
NMI1#
1
Total
19
P_INT[D:A]# /
XINT[3:0]# /
GPIO[11:8]
XINT[7:4]# /
GPIO[15:12]
Datasheet
24
Count
I
Async
ActLow
I
Async
ActLow
I
Async
ActLow
Description
When PCIX_EP# = 0:
• PCI Interrupt requests an interrupt from the central resource.
The assertion and deassertion is asynchronous. A device
asserts its XINT[3:0]# / P_INT[D:A]# line when requesting
attention from its device driver. As soon as the XINT[3:0]# /
P_INT[D:A]# signal is asserted, it remains asserted until the
device driver clears the pending request.
When PCIX_EP# = 1:
• External Interrupt requests are used by external devices to
request interrupt service. These pins are level-detect inputs
and are internally synchronized. These pins go to the
XINT[3:0]# inputs of the interrupt controller. The interrupt
controller can steer the interrupt to either®the FIQ or the IRQ
internal interrupt input of the Intel XScale processor.
General Purpose I/O pins can be selected on a per-pin basis as
general-purpose inputs or outputs. The default mode is a generalpurpose input.
External Interrupt Requests are used by external devices to request
interrupt service. These pins are level-detect and are internally
synchronized. These pins go to the XINT[7:4]# inputs of the
interrupt controller. The interrupt controller can steer the interrupt
to either
the FIQ or the IRQ internal interrupt input of the Intel
XScale® processor.
General Purpose I/O pins can be selected on a per-pin basis as
general-purpose inputs or outputs. The default mode is a generalpurpose input.
General Purpose I/O pins can be selected on a per-pin basis as
general-purpose inputs or outputs. The default mode is a generalpurpose input.
External Interrupts are used by external devices to request
interrupt service. These pins are level-detect and are internally
synchronized. These pins go to the XINT[15:8]# inputs of the
interrupt
controller. These interrupts are dedicated to the Intel
XScale® processor. To enable a given pin as an interrupt, it needs to
be unmasked in the INTCTL[3:0] register.
Performance Monitor Out: The PMON unit output indicator will
generate a signal on the GPIO[7] pin when enabled in the
PMONEN register. When enabled it will override the normal
GPIO[7] function.
High-Priority Interrupt causes a high-priority interrupt to the I/O
processor. This pin is level-detect only and is internally
synchronized.
Non-Maskable
Interrupt causes a non-maskable data abort to the
Intel XScale® processor 0 in the I/O processor. This pin is falling
edge-detect only and is internally synchronized.
Non-Maskable
Interrupt causes a non-maskable data abort to the
Intel XScale® processor 1 in the I/O processor. This pin is falling
edge-detect only and is internally synchronized.
Note: This signal not applicable to the 81341 processor.
December 2007
Order Number: 315038-003US
Package Information—Intel® 81341 and 81342
Table 8.
I2C and SM Bus Signals
Name
Count
Type
SCL0
1
SDA0
1
SCL1
1
SDA1
1
SCL2
1
SDA2
1
SMBCLK
1
SMBDAT
1
Total
8
I/O
OD
I/O
OD
I/O
OD
I/O
OD
I/O
OD
I/O
OD
I/O
OD
I/O
OD
Description
I2C 0 Clock provides synchronous operation of the I2C bus.
I2C 0 Data is used for data transfer and arbitration of the I2C bus.
I2C 1 Clock provides synchronous operation of the I2C bus.
I2C 1 Data is used for data transfer and arbitration of the I2C bus.
I2C 2 Clock provides synchronous operation of the I2C bus.
I2C 2 Data is used for data transfer and arbitration of the I2C bus.
SM Bus Clock provides synchronous operation of the SM bus.
SM Bus Data is used for data transfer and arbitration of the bus.
Note: Open drain outputs require an external pull-up resistor to pull up the signal to 3.3 V. The value of the
pull-up resistor depends on the bus loading.
December 2007
Order Number: 315038-003US
Datasheet
25
Intel® 81341 and 81342—Package Information
Table 9.
UART Signals (Sheet 1 of 2)
Name
Count
Type
Description
U0_RXD
1
Async
I
U0_TXD
1
Async
UART 0 Serial Input: Serial data input from device pin to the receive
shift register.
UART 0 Serial Output: Composite serial data output to the
communications link-peripheral, modem, or data set. The TXD
signal is set to the MARKING (logic 1) state upon a reset operation.
O
UART 0 Clear to Send: When low, this pin indicates that the receiving UART
is ready to receive data. When the receiving UART deasserts
high, the
transmitting UART must stop transmission to prevent overflow of the
receiving UART buffer. The
signal is a modem-status input whose
condition can be tested by the host processor or by the UART when in
Autoflow Mode as described below:
CTS#
CTS#
Datasheet
26
U0_CTS#
1
U0_RTS#
1
U1_RXD
1
• Non-Autoflow Mode:
When not in Autoflow Mode, bit[4] (CTS) of the Modem Status
Register (MSR) indicates the state of CTS#. Bit[4] is the
complement of the CTS# signal. Bit[0] (DCTS) of the Modem
Status Register indicates whether the CTS# input has changed
state since the previous reading of the Modem Status Register.
I
CTS# has no effect on the transmitter. The user can program
ActLow
the UART to interrupt the processor when DCTS changes state.
Async
The programmer can then stall the outgoing data stream by
starving the transmit FIFO or disabling the UART with the IER
register.
Note: When UART transmission is stalled by disabling the UART,
the user does not receive an MSR interrupt when CTS#
reasserts. This is because disabling the UART also disables
interrupts. To work around this, the user can use Auto CTS
in Autoflow Mode, or program the CTS# pin to interrupt.
• Autoflow Mode:
In Autoflow Mode, the UART transmit circuity checks the state of
CTS# before transmitting each byte. When CTS# is high, no
data is transmitted.
UART 0 Request to Send: This bit indicates to the remote device
whether the UART is ready to receive data. When this bit is low, the
UART is ready to receive data. A reset operation sets this signal to
its inactive (high) state. LOOP Mode operation holds this signal in
its inactive state.
• Non-Autoflow Mode:
O
The RTS# output signal can be asserted by setting bit[1] (RTS)
ActLow
of the Modem Control Register to 1. The RTS bit is the
Async
complement of the RTS# signal.
• Autoflow Mode:
RTS# is automatically asserted by the autoflow circuitry when
the receive buffer exceeds its programmed threshold. It is
deasserted when enough bytes are removed from the buffer to
lower the data level back to the threshold.
I
UART 1 Serial Input: Serial data input from the device pin to the
receive shift register.
Async
December 2007
Order Number: 315038-003US
Package Information—Intel® 81341 and 81342
Table 9.
UART Signals (Sheet 2 of 2)
Name
U1_TXD
Count
Type
Description
1
Async
O
UART 1 Serial Output: Composite serial data output to the
communications link-peripheral, modem, or data set. The TXD
signal is set to the MARKING (logic 1) state upon a reset operation.
UART 1 Clear to Send: When low, this pin indicates that the receiving UART
is ready to receive data. When the receiving UART deasserts
high, the
transmitting UART must stop transmission to prevent overflow of the
receiving UART buffer. The
signal is a modem-status input whose
condition can be tested by the host processor or by the UART when in
Autoflow Mode as described below:
CTS#
CTS#
U1_CTS#
1
U1_RTS#
1
Total
8
December 2007
Order Number: 315038-003US
• Non-Autoflow Mode:
When not in Autoflow Mode, bit[4] (CTS) of the Modem Status
Register (MSR) indicates the state of CTS#. Bit[4] is the
complement of the CTS# signal. Bit[0] (DCTS) of the Modem
Status Register indicates whether the CTS# input has changed
state since the previous reading of the Modem Status Register.
I
CTS# has no effect on the transmitter. The user can program
ActLow
the UART to interrupt the processor when DCTS changes state.
Async
The programmer can then stall the outgoing datastream by
starving the transmit FIFO or disabling the UART with the IER
register.
Note: When UART transmission is stalled by disabling the UART,
the user does not receive an MSR interrupt when CTS#
reasserts. This is because disabling the UART also disables
interrupts. To get around this, the user can use Auto CTS in
Autoflow Mode, or program the CTS# pin to interrupt.
• Autoflow Mode:
In Autoflow Mode, the UART transmit circuity checks the state of
CTS# before transmitting each byte. When CTS# is high, no
data is transmitted.
UART 1 Request to Send: This bit indicates to the remote device
whether the UART is ready to receive data. When low, the UART is
ready to receive data. A reset operation sets this signal to its
inactive (high) state. LOOP Mode operation holds this signal in its
inactive state.
• Non-Autoflow Mode:
O
The RTS# output signal can be asserted by setting bit[1] (RTS)
ActLow
of the Modem Control Register to 1. The RTS bit is the
Async
complement of the RTS# signal.
• Autoflow Mode:
RTS# is automatically asserted by the autoflow circuitry when
the receive buffer exceeds its programmed threshold. It is
deasserted when enough bytes are removed from the buffer to
lower the data level back to the threshold.
Datasheet
27
Intel® 81341 and 81342—Package Information
Table 10.
Miscellaneous Signals
Name
Count
TCK
1
TDI
1
TDO
1
TRST#
1
TMS
1
NC
106
P_RST#
1
1
WARM_RST#
THERMDA
THERMDC
PUR1
Total
Datasheet
28
1
1
1
Type
Description
Test Clock provides clock input for IEEE 1149.1 Boundary Scan
Testing (JTAG). State information and data are clocked into the
device on the rising clock edge, and data is clocked out on the
falling clock edge.
Test Data Input is the JTAG serial input pin. TDI is sampled on the
rising edge of TCK, during the SHIFT-IR and SHIFT-DR states of
I
Sync (T) the Test Access Port. This signal has a weak internal pull-up to
ensure proper operation when this pin is not being driven.
Test Data Output is the serial output pin for the JTAG feature. TDO
O
driven on the falling edge of TCK during the SHIFT-IR and
Sync (T) isSHIFT-DR
of the Test Access Port. At other times, TDO
Rst (T) floats. Thestates
behavior of TDO is independent of other resets.
Test Reset asynchronously resets the Test Access Port controller
I
of IEEE 1149 Boundary Scan Testing (JTAG). This pin has
Async function
weak internal pull-up.
ActLow aNote:
This pin must be tied low when not used.
Test Mode Select is sampled on the rising edge of TCK to select
I
operation of the test logic for IEEE 1149 Boundary Scan
Sync (T) the
testing. This pin has a weak internal pull-up.
No Connect: Pins have no usable function and must not be
I/O
connected to any signal, power, or ground.
Cold Reset is used to asynchronously reset the I/O processor
when it is low. This signal must be asserted whenever the power
I
supplies are outside of the specified ranges.
Async
are reset to default values.
ActLow •• Registers
Pins are driven to known states.
• Sticky configuration bits are reset.
Warm Reset is the same as a cold reset, except sticky
I
configuration bits are not reset. This pin should only be used when
Async
the sticky bit functionality is required. In this scenario, the
ActLow
WARM_RST# pin must be tied to the system reset PCI_RST#
signal while the P_RST# pin can be tied to the system power good
signal. If the sticky bit functionality is not required, the
WARM_RST# pin should not be used and must be tied to Vcc.
When the PCI Express interface is used as an endpoint, the PCI
Express inband Hot Reset Mechanism can also be used to provide
the sticky bit functionality.
Note: Driving WARM_RST# using any other methods than
suggested above may result in unpredictable behavior of
the device.
I
Thermal Diode Anode is the anode of the thermal diode.
O
Thermal Diode Cathode is the cathode of the thermal diode.
Pull-Up Required 1: This pin must be pulled up to VCC3P3 with an
I
external 8.2K ohm 5%, 1/16 W resistor for proper operation.
I
116
December 2007
Order Number: 315038-003US
Package Information—Intel® 81341 and 81342
Table 11.
Power and Ground Signals
Name
Count
Type
Description
VCC1P2PLLP
1
PWR
VCC1P2PLLD
1
PWR
VCC3P3PLLX
1
PWR
VSSPLLP
VSSPLLD
VSSPLLX
VCC1P2
1
204
GND
GND
GND
PWR
VCC1P2AE
8
PWR
VCC1P2E
6
PWR
VCC1P2X
119
PWR
VCCVIO
21
PWR
VCC1P8
36
PWR
VCC1P8E
14
PWR
VCC3P3
42
PWR
VSS
VSSE
403
20
880
GND
GND
VCC PLL PCI-X: Ball connected to a 1.2 V filtered board supply.
Provides power to PLL that controls the PCI-X logic and interface.
VCC PLL DDR: Ball connected to a 1.2 V filtered board supply.
Provides power to the PLL that controls the DDR2 SDRAM interface
and processor digital logic.
VCC PLL X: Ball to be connected to a 3.3 V filtered board supply.
This pin provides power to a voltage regulator,®which supplies
power to the PLL that controls the Intel XScale processor and XSI
processor logic.
VSS PLL PCI-X: Ball connected to capacitor of the VCC1P2PLLP filter.
VSS PLL DDR2 SDRAM: Ball connected to capacitor of VCC1P2PLLD
filter.
VSS PLL X: Ball connected to capacitor of VCC3P3PLLX filter.
1.2 V Power: Balls to be connected to a 1.2 V board power plane.
These pins provide power to the processor logic.
1.2 V Power: Balls to be connected to a 1.2 V board power plane.
These pins provide power to the PCI Express* analog logic.
1.2 V Power: Balls to be connected to a 1.2 V board power plane.
These pins provide power to the PCI Express* digital logic.
1.2 V Power: Balls to be connected to a 1.2 V®board power plane.
These pins provide power to the Intel XScale processors.
VIO Power: Balls to be connected to a 3.3 V board power plane.
These pins provide 3.3 V power to the PCI-X I/Os.
1.8 V Power: Balls to be connected to a 1.8 V board power plane.
These pins provide power to the DDR2 SDRAM interface I/Os.
1.8 V Power: Balls to be connected to a 1.8 V board power plane.
These pins provide power to the PCI Express* interface I/Os.
3.3 V Power: Balls to be connected to a 3.3 V board power plane.
These pins provide power to the PBI, miscellaneous pins, and PCI-X
I/Os in Mode 1.
Ground: Balls to be connected to a board ground plane.
PCI Express* Ground: Balls connected to a board ground plane.
Total
December 2007
Order Number: 315038-003US
1
1
Datasheet
29
Intel® 81341 and 81342—Package Information
Table 12.
Reset Strap Signals (Sheet 1 of 3)
Name
Count
Type
BOOT_WIDTH_8#
1
Reset
Strap
DF_SEL[2:0]
3
Reset
Strap
Description
PBI Boot Bus Width: Sets the default bus width for the PBI
Memory Boot window.
0 = 8 bits wide
1 = 16 bits wide (default mode)
Note: Muxed onto signal A[0].
Device Function Select: These straps select the number®of
storage ports assigned
to each function within the Intel
81341 and Intel® 81342 I/O Processors.
Note: DF_SEL[2] muxed onto signal A[9]
Note: DF_SEL[1] muxed onto signal A[8]
Note: DF_SEL[0] muxed onto signal A[7]
See the “Device Function Select” of the Intel 81341 and
Intel 81342 I/O Processors Developer's Manual for
additional details.
Configuration Cycle Enable: Determines whether PCI
interface retries configuration cycles until Host Lockout Bit is
cleared in all enabled TPMI functions (TCFGR[5]).
0 = Configuration cycles enabled
1 = Configuration retry enabled (default mode)
• PCI-X Interface: Configuration cycles are claimed and
terminated with a retry status.
• PCI Express* Interface: Configuration requests result in
a completion TLP with Configuration Retry Status (CRS).
Note: Muxed onto signal A[1]
Hold Intel XScale® Microprocessor
0 in Reset: Determines
whether the Intel XScale® microprocessor number 0 is held
in reset until the reset bit is cleared in the PCI Configuration
and Status Register.
0 = Hold in reset
1 = Do not hold in reset (default mode)
Note: Muxed onto signal A[2]
Hold Intel XScale® Microprocessor 1 in Reset: Determines
whether the Intel XScale® microprocessor number 1 is held
in reset until the reset bit is cleared in the PCI Configuration
and Status Register.
0 = Hold in reset
1 = Do not hold in reset (default mode)
Note: Muxed onto signal A[3]
Note: This signal not applicable to the 81341 processor.
Memory Frequency: Determines frequency at which DDR2
memory subsystem runs.
l®
l®
Datasheet
30
CFG_CYCLE_EN#
1
Reset
Strap
HOLD_X0_IN_RST#
1
Reset
Strap
HOLD_X1_IN_RST#
1
Reset
Strap
MEM_FREQ[1:0]
2
Reset
Strap
EXT_ARB#
1
Reset
Strap
INTERFACE_SEL_PCIX#
1
Reset
Strap
PCIX_EP#
1
Reset
Strap
00 = Reserved
01 =Reserved
10 =533 MHz
11 =400 MHz (Default mode)
Note: MEM_FREQ[1] muxed onto signal A[5]
Note: MEM_FREQ[0] muxed onto signal A[4]
External Arbiter: Determines whether the PCI interface
enables the integrated arbiter, or use an external arbiter.
0 = External arbiter
1 = Internal arbiter (default mode)
Note: Muxed onto signal A[6]
0 = PCI-X is active
1 = PCI Express is active (default mode)
When both interfaces are active, this strap selects the ATU
that is function 0 in the internal address map.
Note: Muxed onto signal A[10]
PCI-X End Point: Determines whether the PCI-X interface
operates as an endpoint or a central resource.
0 = Endpoint
1 = Central resource (default mode)
Note: Muxed onto signal A[11]
Note: Setting both PCIX_EP# and PCIE_RC# to endpoint
is unsupported.
December 2007
Order Number: 315038-003US
Package Information—Intel® 81341 and 81342
Table 12.
Reset Strap Signals (Sheet 2 of 3)
Name
Count
Type
PCIE_RC#
1
Reset
Strap
SMB_A5,
SMB_A3,
SMB_A2,
SMB_A1
4
Reset
Strap
PCIX_PULLUP#
1
Reset
Strap
PCIX_32BIT#
1
Reset
Strap
PCIXM1_100#
1
Reset
Strap
HS_SM#
1
Reset
Strap
FW_TIMER_OFF#
1
Reset
Strap
CONTROLLER_ONLY#
1
Reset
Strap
LK_DN_RST_BYPASS#
1
Reset
Strap
December 2007
Order Number: 315038-003US
Description
PCI-E Root Complex: Determines whether PCI Express*
interface operates as an endpoint or a root complex.
0 = Root complex
1 = Endpoint (default mode)
Note: Muxed onto signal A[12]
Setting both PCIX_EP# and PCIE_RC# to endpoint is
unsupported.
SM Bus Address: Maps to address bit[5], bit[3], bit[2], and
bit[1] where bits[7:0] represent address SMBus slave port
responds to when access is attempted.
0 = Address bit is low
1 = Address bit is high (default mode)
Note: SMB_A5 muxed onto signal A[16]
Note: SMB_A3 muxed onto signal A[15]
Note: SMB_A2 muxed onto signal A[14]
Note: SMB_A1 muxed onto signal A[13]
PCI-X Pull Up: Determines whether PCI interface has on-die
pull-ups enabled. These may be used for the central
resource bus keepers.
0 = Enable PCI pull-up resistors
1 = Disable PCI pull-up resistors (default mode)
Note: Muxed onto signal A[17]
32-Bit PCI-X Bus: Indicates width of the PCI-X bus to PCI-X
Status Register. Enables pull-ups for upper half of bus when
in 32-bit mode.
0 = 32-bit wide PCI-X bus
1 = 64-bit wide PCI-X bus (default mode)
Note: Muxed onto signal A[18]
PCI-X Mode 1 100 MHz Enable: In Central Resource Mode,
this bit limits PCI-X bus to 100 MHz while in mode 1:
0 = Limit PCI-X mode 1 to 100 MHz
1 = 133 MHz enabled (default mode)
Note: Muxed onto signal A[19]
Hot Swap Startup Mode: In End Point Mode, this bit
determines whether Hot Swap mode is enabled.
0 = Hot Swap Mode enabled
1 = Hot Swap Mode disabled (default mode)
Note: Muxed onto signal A[21]
Firmware Timer Off: Disables 400 mS firmware timer for
development and debug. When enabled, timer automatically
clears Configuration Cycle Retry (CCR) bit in PCSR after
400 mS regardless of processor state. When disabled, CCR
bit functions as normal based on state of CFG_CYCLE_EN#
pin at rising edge of P_RST#.
0 = Firmware timer disabled
1 = Firmware timer enabled (default mode)
Note: Muxed onto signal A[22]
Controller-Only Enable:
0 = Controller only, RAID disabled
1 = RAID enabled (default mode)
Note: Muxed onto signal A[23]
Link Down Reset Bypass: Disables the full chip reset that
would normally be caused by a Link Down or hot reset.
0 = Do not reset on Link Down
1 = Reset on Link Down (default mode)
Note: Muxed onto signal A[24]
Datasheet
31
Intel® 81341 and 81342—Package Information
Table 12.
Reset Strap Signals (Sheet 3 of 3)
Name
CLK_SRC_PCIE#
Count
Type
1
Reset
Strap
Description
Clock Source PCI-E: Selects PCI Express* Refclk pair as the
input clock to the PLLs that control most internal logic.
0 = Source clock is REFCLKP/REFCLKN
1 = Source clock is P_CLKIN (default mode)
Note: When P_CLKO[3:0] are used this pin must be
pulled low.
Note: Muxed onto signal PWE#
Total
25
Reset strap signals are latched on the rising edge of P_RST#. All reset strap signals are internally pulled to
logic 1 by default. An external 4.7K ohm 5%, 1/16 W pull-down resistor is required to force a logic 0 on these
pins.
Datasheet
32
December 2007
Order Number: 315038-003US
Package Information—Intel® 81341 and 81342
Table 13.
Functional Pin Mode Behavior (Sheet 1 of 4)
Pin
M_CK[2:0],
M_CK#[2:0]
M_RST#
MA[14:0]a
BA[2:0]
RAS#
CAS#
WE#
CS[1:0]#
CKE[1:0]
DQ[63:32]
DQ[31:0]
CB[7:0]
DQS[8],
DQS#[8]
DQS[7:4],
DQS#[7:4]
DQS[3:0],
DQS#[3:0]
DM[8]
DM[7:4]
DM[3:0]
M_VREF
ODT[1:0]
M_CAL[1:0]
A[24:0]
D[15:0]
POE#
PWE#
PB_RSTOUT#
PCE[1:0]#
HS_ENUM#
HS_LSTAT
HS_LED_OUT
HS_FREQ[1:0] /
CR_FREQ[1:0]
Notes:
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)t
te nio
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R dn
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la
trn )e
eC cru
(t o
es seR
eR
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
VO
0*
VO
VO
VO
VO
VO
VO
0*
Z*
Z*
Z*
Z*
VO
0*
VO
VO
VO
VO
VO
VO
0*
Z*
Z*
Z*
Z*
Z
Z*
Z
Z
Z
Z
–
Z
Z
Z
Z
Z
Z
Z
Z
Z
–
Z
Z
Z*
VO*
VO*
VO*
AI
0*
Z*
H
H
H
H
0
H
Z
VI
1
H
M
AR
DS
itB
-2
3
#T
IB
23
_X
IC
P
#P
UL
LU
P_
XI
CP
VO
VO
VO
VO
VO
VO
VO
VO
VO
VB
VB
VB
VB
–
–
–
–
–
–
–
–
–
Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Z*
VB
Z
–
–
–
–
Z*
VO*
VO*
VO*
AI
0*
Z*
H
H
H
H
0
H
Z
VI
1
H
VB
VO
VO
VO
AI
VO
AO
VO
VB
VO
VO
VO
VO
VO
VI
VO
H
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
la
m
ro
N
y
nol X eca ev
ne -IC rfe itc
h P tnI A
W
yl *ss e
no er ca ev
ne px rfe itc
h EI tnI A
WCP
EA = External Arbiter mode
IA = Internal Arbiter mode
Z = output, pull-up/down disabled
VB = acts like a Valid Bidirectional pin
VO = a Valid Output level is driven.
VI = need to drive a Valid Input level.
AO = Analog Output level
AI = Analog Input level
* = after power fail sequence completes
“-” = unaffected by this mode
a. MA[14] is only needed for 4GB memory support. When 4GB memory is not used this pin is NC.
1 = driven to VCC
0 = driven to VSS
X = driven to unknown state
ID = The input is disabled.
H = pulled up to VCC
PD = pull-up disabled
L = pulled down to VSS
ODT = On Die Termination
GND = Tie to Ground.
December 2007
Order Number: 315038-003US
Datasheet
33
Intel® 81341 and 81342—Package Information
Table 13.
Functional Pin Mode Behavior (Sheet 2 of 4)
Pin
P_AD[63:32]
P_AD[31:0]
P_CBE[7:4]#
P_CBE[3:0]#
P_PAR64
P_REQ64#
P_ACK64#
P_PAR
P_FRAME#
P_IRDY#
P_TRDY#
P_STOP#
P_DEVSEL#
P_SERR#
P_RSTOUT#
P_PERR#
P_M66EN
P_IDSEL
P_GNT[0]# / P_REQ#
P_REQ[0]# / P_GNT#
P_GNT[3:1]#
P_REQ[3:1]#
P_CLKIN
P_CLKOUT
P_CLKO[3:0]
P_PCIXCAP
P_BMI
P_CAL[2:0]
REFCLKP,
REFCLKN
PETP[7:0],
PETN[7:0]
Notes:
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cS
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ad gi
nu H
oB
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
–
–
)t
te nio
se P
R dn
E(
Z
–
–
Z
Z
–
Z
Z
–
Z(EA)
H(IA)
VI(EA)
H(IA)
H
H
VI
Z
Z
AI
VO
AO
VI
Z
0
Z
0
Z
0
Z
0
VO
VO
VO
VO
VO
Z
0
VO
VI
VI
Z(EA)
H(IA)
VI(EA)
H(IA)
H
H
VI
VO
VO
AI
VO
AO
VI
–
Z
Z
Z
–
Z
Z
Z
Z
Z
VI
Z
Z
VI
VI
VI
VI
VI
Z
0
VI
VI
VI
la
trn )e
eC cru
(t o
es seR
eR
la
m
ro
N
M
AR
DS
itB
-2
3
#T
IB
23
_X
IC
P
#P
UL
LU
P_
XI
CP
y
nol X eca ev
ne -IC rfe itc
h P tnI A
W
yl *ss e
no er ca ev
ne px rfe itc
h EI tnI A
WCP
VB
VB
VB
VB
VB
VB
VB
VB
VB
VB
VB
VB
VB
VB
VO
VB
VI
VI
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
H
–
H
–
H
–
–
–
–
–
–
–
–
–
–
–
–
–
H
–
H
–
H
H
H
–
H
H
H
H
H
H
–
H
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
H
H
H
H
H
H
H
H
H
H
H
H
H
H
VO
H
H
H
VO
–
–
–
–
H
VI(EA)
H(IA)
VO
H
VI
VO
VO
AI
VO
AO
VI
–
–
–
–
H
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
H
H
GND
Z
Z
GND
VO
VO
–
VO
–
–
–
–
–
–
–
–
–
–
–
GND/
VI
Z
–
EA = External Arbiter mode
IA = Internal Arbiter mode
Z = output, pull-up/down disabled
VB = acts like a Valid Bidirectional pin
VO = a Valid Output level is driven.
VI = need to drive a Valid Input level.
AO = Analog Output level
AI = Analog Input level
* = after power fail sequence completes
“-” = unaffected by this mode
a. MA[14] is only needed for 4GB memory support. When 4GB memory is not used this pin is NC.
1 = driven to VCC
0 = driven to VSS
X = driven to unknown state
ID = The input is disabled.
H = pulled up to VCC
PD = pull-up disabled
L = pulled down to VSS
ODT = On Die Termination
GND = Tie to Ground.
Datasheet
34
December 2007
Order Number: 315038-003US
Package Information—Intel® 81341 and 81342
Table 13.
Functional Pin Mode Behavior (Sheet 3 of 4)
Pin
PERP[7:0],
PERN[7:0]
PE_CALP
PE_CALN
P_INT[D:A]# /
XINT[3:0]#
XINT[7:4]#
GPIO[7:0] /
XINT[15:8]# /
PMONOUT
HPI#
NMI0#
NMI1#
SCL0
SDA0
SCL1
SDA1
SCL2
SDA2
SMBCLK
SMBDAT
U0_RXD
U0_TXD
U0_CTS#
U0_RTS#
U1_RXD
U1_TXD
U1_CTS#
U1_RTS#
TCK
TDI
Notes:
)t
te nio
se P
R dn
E(
la
trn )e
eC cru
(t o
es seR
eR
la
m
ro
N
–
–
–
Z
–
ID
AO
AO
Z/VI
VI
ID
AO
AO
Z/VI
VI
Z
VI
VI
–
–
–
Z
Z
Z
Z
Z
Z
Z
Z
–
Z
–
Z
–
Z
–
Z
–
–
VI
VI
VI
Z
Z
Z
Z
Z
Z
Z
Z
VI
1
VI
1
VI
1
VI
1
VI
H
VI
VI
VI
Z
Z
Z
Z
Z
Z
Z
Z
VI
1
VI
1
VI
1
VI
1
VI
H
na
cS
yr Zh
ad gi
nu H
oB
#P
UL
LU
P_
XI
CP
#T
IB
23
_X
IC
P
VI
AO
AO
VB
VI
–
–
–
–
–
–
–
–
–
–
–
–
–
H
–
Z
Z
Z
–
–
–
–
–
–
–
VB
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
VI
–
–
–
VI
–
–
–
VI
–
–
–
VB
–
–
–
VB
–
–
–
VB
–
–
–
VB
–
–
–
VB
–
–
–
VB
–
–
–
VB
–
–
–
VB
–
–
–
VI
–
–
–
VO
–
–
–
VI
–
–
–
VO
–
–
–
VI
–
–
–
VO
–
–
–
VI
–
–
–
VO
–
–
–
VI
–
–
–
H
–
–
–
EA = External Arbiter mode
1 = driven to VCC
IA = Internal Arbiter mode
0 = driven to VSS
Z = output, pull-up/down disabled
X = driven to unknown state
VB = acts like a Valid Bidirectional pin
ID = The input is disabled.
VO = a Valid Output level is driven.
H = pulled up to VCC
VI = need to drive a Valid Input level.
PD = pull-up disabled
AO = Analog Output level
L = pulled down to VSS
AI = Analog Input level
ODT = On Die Termination
* = after power fail sequence completes
GND = Tie to Ground.
“-” = unaffected by this mode
a. MA[14] is only needed for 4GB memory support. When 4GB memory is not used this pin is NC.
December 2007
Order Number: 315038-003US
yl *ss e
no er ca ev
ne px rfe itc
h EI tnI A
WCP
M
AR
DS
itB
-2
3
y
nol X eca ev
ne -IC rfe itc
h P tnI A
W
Datasheet
35
Intel® 81341 and 81342—Package Information
Table 13.
Pin
TDO
TRST#
TMS
P_RST#
WARM_RST#
NC
THERMDA
THERMDC
Notes:
Functional Pin Mode Behavior (Sheet 4 of 4)
na
cS
yr Zh
ad gi
nu H
oB
Z
H
H
VI
VI
Z/H
AI
AO
la
trn )e
eC cru
(t o
es seR
eR
Z
H
H
VI
VI
Z/H
AI
AO
la
m
ro
N
M
AR
DS
itB
-2
3
#T
IB
23
_X
IC
P
#P
UL
LU
P_
XI
CP
y
nol X eca ev
ne -IC rfe itc
h P tnI A
W
VO
–
–
–
H
–
–
–
H
–
–
–
VI
–
–
–
VI
–
–
–
Z/H
–
–
–
AI
–
–
–
AO
–
–
–
EA = External Arbiter mode
1 = driven to VCC
IA = Internal Arbiter mode
0 = driven to VSS
Z = output, pull-up/down disabled
X = driven to unknown state
VB = acts like a Valid Bidirectional pin
ID = The input is disabled.
VO = a Valid Output level is driven.
H = pulled up to VCC
VI = need to drive a Valid Input level.
PD = pull-up disabled
AO = Analog Output level
L = pulled down to VSS
AI = Analog Input level
ODT = On Die Termination
* = after power fail sequence completes
GND = Tie to Ground.
“-” = unaffected by this mode
a. MA[14] is only needed for 4GB memory support. When 4GB memory is not used this pin is NC.
Datasheet
36
–
–
–
–
–
-/Z
–
–
)t
te nio
se P
R dn
E(
–
–
–
–
–
–
–
–
yl *ss e
no er ca ev
ne px rfe itc
h EI tnI A
WCP
–
–
–
–
–
–
–
–
December 2007
Order Number: 315038-003US
Package Information—Intel® 81341 and 81342
Figure 3.
1357-Lead FCBGA Package (Top and Bottom Views)
December 2007
Order Number: 315038-003US
Datasheet
37
Intel® 81341 and 81342—Package Information
Datasheet
38
December 2007
Order Number: 315038-003US
Package Information—Intel® 81341 and 81342
The following figures show the Intel® 81341 and 81342 I/O processors ballout
diagrams:
• Figure 4, “Intel® 81341 and 81342 I/O processors Ballout— Package Top (Left
Side)” on page 40
• Figure 5, “Intel® 81341 and 81342 I/O processors Ballout— Package Top (Right
Side)” on page 41
• Figure 6, “Intel® 81341 and 81342 I/O processors Ballout — Package Bottom (Left
Side)” on page 42
• Figure 7, “Intel® 81341 and 81342 I/O processors Ballout — Package Bottom
(Right Side)” on page 43
The following tables show the Intel® 81341 and 81342 I/O processors ball and signal
listings:
• Table 14, “Intel® 81341 and 81342 I/O processors 1357-Lead Package—
Alphabetical Ball Listings” on page 44
• Table 15, “Intel® 81341 and 81342 I/O processors 1357-Lead Package—
Alphabetical Signal Listings” on page 55
December 2007
Order Number: 315039-003US
Intel® 81341 and 81342 I/O Processors
Datasheet
39
Intel® 81341 and 81342—Package Information
Figure 4.
Intel® 81341 and 81342 I/O processors Ballout— Package Top
(Left Side)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
vss
dq[63]
dqs[7]
dqs#
[7]
dq[57]
dq[56]
dq[60]
dq[43]
dq[47]
dqs[5]
dqs#
[5]
dq[41]
dq[40]
dq[44]
cb[2]
cb[6]
dqs#
[8]
vss
dq[59]
dq[58]
dq[62]
vss
dm[7]
dq[61]
vss
vss
dq[42]
dq[46]
vss
dm[5]
dq[45]
vss
cb[3]
cb[7]
dqs[8]
nc
dq[51]
dq[50]
dqs[6]
dqs#
[6]
dm[6]
dq[53]
dq[52]
dq[35]
dq[34]
dqs[4]
dqs#
[4]
dm[4]
dq[37]
dq[36]
m_ck#
[2]
vss
dm[8]
m_ck#
[0]
m_ck
[0]
37
36
35
vss
34
nc
nc
vss
dq[55]
dq[54]
vss
dq[49]
dq[48]
33
nc
nc
ma[14]a
nc
vss
odt[1]
vcc3
p3
vcc1
p8
cs#[1] ma[13]
vss
vss
odt[0]
cas#
vcc1
p8
vcc1
p8
dq[39]
dq[33]
dq[32]
vss
m_ck
[2]
cs#[0]
ras#
ba[0]
ma[10]
ba[1]
ma[0]
vss
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
dq[38]
vss
we#
vss
vcc1
p8
vcc1
p8
32
nc
nc
nc
nc
nc
vcc3
p3
31
nc
nc
nc
nc
nc
nc
vcc3
p3
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vsspllx
therm
da
nc
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
therm
dc
vcc1
p2x
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vss
vcc1
p2x
vss
vcc1
p2x
vcc1
p2
vss
vcc1
p2
vss
vss
vcc1
p2
vcc1
p2
vss
vcc1
p2
30
nc
vss
nc
vss
nc
nc
vcc3
p3
29
nc
nc
nc
nc
nc
nc
vcc3
p3
vss
vcc1
p2x
vcc1
p2x
vss
vss
vcc1
p2x
vcc1
p2x
vss
vss
vcc1
p2x
vcc1
p2x
vss
vss
vcc1
p2x
vcc1
p2
vss
vss
vcc1
p2
vcc1
p2
vss
vss
vcc1
p2
vss
vcc1
p2
28
nc
nc
nc
nc
nc
nc
vcc3
p3
27
nc
vss
nc
vss
nc
nc
vcc3
p3
vss
vcc1
p2x
vcc1
p2x
vss
vss
vcc1
p2x
vcc1
p2x
vss
vss
vcc1
p2x
vcc1
p2
vss
vss
vcc1
p2
vcc1
p2
vss
vss
vcc1
p2
vcc1
p2
vss
vss
vcc1
p2
vss
vcc1
p2
26
nc
nc
nc
nc
nc
nc
vcc3
p3
25
nc
nc
nc
nc
nc
nc
vcc3
p3
vcc1
p2
vcc1
p2
vss
vcc1
p2
vcc1
p2
vss
vss
vcc1
p2x
vcc1
p2
vss
vss
vcc1
p2
vcc1
p2
vss
vss
vcc1
p2
vcc1
p2
vss
vss
vcc1
p2
vcc1
p2
vss
vss
vcc1
p2
vss
vcc1
p2
24
vss
vss
vss
vss
vcc1
p2
23
nc
nc
nc
nc
vcc1
p2
vcc1
p2
vcc1
p2
vcc1
p2
vcc1
p2
vss
vcc1
p2
nc
nc
vss
vss
vss
vcc1
p2
vcc1
p2
vss
vss
vcc1
p2
vcc1
p2
vss
vss
vcc1
p2
vcc1
p2
vss
vss
vcc1
p2
vcc1
p2
vss
vss
vcc1
p2
vss
vcc1
p2
22
nc
nc
nc
nc
vcc1
p2
21
vss
vss
vss
vss
nc
20
nc
nc
nc
nc
nc
nc
nc
vss
vcc1
p2
19
nc
nc
nc
nc
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p2
vss
vcc1
p8
vcc1
p8
vss
vcc1
p2
vss
vcc1
p2
vss
vss
vcc1
p2
vss
vcc1
p2
vss
vss
vcc1
p2
vcc1
p2
vss
vss
vcc1
p2
vcc1
p2
vss
vss
vcc1
p2
vcc1
p2
vss
vss
vcc1
p2
vss
vcc1
p2
18
vss
vss
vss
vss
vcc1
p8
17
nc
nc
nc
nc
vcc1
p2
16
nc
nc
nc
nc
nc
nc
nc
vss
vss
vss
vcc1
p2
15
vss
vss
vss
vss
nc
nc
nc
vss
vcc1
p2
vcc1
p2
vss
vss
vcc1
p2
vss
vcc1
p2
vcc1
p2
vss
vcc1
p2
vss
vss
vcc1
p2
vss
vcc1
p2
vcc1
p2
vsspllp
vcc1
p2pllp
vss
vss
vcc1
p2
vss
vcc1
p2
vcc1
p2
vss
vcc1
p2
vss
vss
14
nc
nc
nc
nc
vss
vcc1
p2
vss
vss
vcc1
p2
13
nc
nc
nc
nc
vcc1
p2
vss
vcc1
p2
vcc1
p2
vss
vss
vcc1
p2
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
gpio[1] gpio[3] gpio[7] gpio[5] gpio[6]
vcc3
p3
vss
vcc1
p2
vss
vcc1
p2
vss
10
gpio[0]
vss
gpio[2]
vss
gpio[4]
vcc3
p3
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
9
xint#
[1]
xint#
[3]
xint#
[5]
xint#
[4]
xint#
[7]
vcc3
p3
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
8
xint#
[2]
xint#
[0]
xint#
[6]
vcc3
p3
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
7
hs_enu
m#
vss
hpi#
vcc3
p3
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
6
u0_
rts#
u0_
rxd
vcc3
p3
vcc3
p3
vccvio
vcc3
p3
vcc3
p3
vccvio
vccvio
vcc3
p3
vccvio
vcc3
p3
vcc3
p3
vccvio
vcc3
p3
vcc3
p3
5
u0_
cts#
u0_
txd
u1_
rxd
p_ad
[31]
vccvio
p_ad
[26]
p_idsel vccvio
p_ad
[16]
p_ad
[13]
p_ad
[9]
4
u1_
cts#
u1_
txd
u1_
rts#
vss
p_ad
[24]
vss
3
vss
p_clko
[3]
p_clko
[2]
p_cal
[2]
nc
p_cal
[1]
vss
p_clko
[0]
p_
clkout
vss
p_rst#
12
11
vss
2
vss
1
A
B
vss
vss
hs_led_
nmi0#
out
vss
nmi1#
hs_freq[ hs_freq[
hs_lstat
1]
0]
nc
vss
p_clkin
C
D
vcc3
p3
p_cal
[0]
p_gnt#[ vccvio p_gnt#[
3]
0]
warm_r
p_bmi
st#
p_
p_gnt#[
req#[3]
1]
p_clko p_rstout
[1]
#
E
F
vss
p_
p_gnt#[
req#[2]
2]
vss
nc
G
nc
vss
p_ad
[30]
nc
p_ad
[27]
p_ad
[28]
p_ad
[23]
p_ad
[22]
nc
vss
p_ad
[25]
p_ad
[21]
vss
p_ad
[29]
p_
cbe#
[3]
p_ad
[19]
p_ad
[17]
K
L
M
N
p_
p_
req#[1] req#[0]
H
J
p_ad p_frame
[20]
#
p_trdy# vccvio
p_
par
p_ad
[11]
vss
p_ad p_devse
p_stop#
[18]
l#
p_ad
[15]
p_ad
[12]
p_
cbe#
[0]
p_
cbe#
[2]
p_
cbe#
[1]
p_ad
[10]
vss
p_ad
[14]
p_m66e
n
vss
U
V
W
p_pcixc
ap
vss
vss
p_irdy# p_perr# p_serr#
P
R
T
a. MA[14] only needed for 4GB memory support, otherwise this pin is NC.
Intel® 81341 and 81342 I/O Processors
Datasheet
40
December 2007
Order Number: 315039-003US
Package Information—Intel® 81341 and 81342
Figure 5.
December 2007
Order Number: 315039-003US
Intel® 81341 and 81342 I/O processors Ballout— Package Top
(Right Side)
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
AL
AM
AN
AP
AR
cb[1]
cb[0]
dq[27]
dq[31]
dqs[3]
dqs#
[3]
dq[25]
dq[24]
dq[28]
dq[11]
dq[15]
dqs[1]
dqs#
[1]
dq[9]
dm[1]
vss
AT
AU
37
cb[5]
cb[4]
vss
dq[26]
dq[30]
vss
dm[3]
dq[29]
vss
vss
dq[10]
dq[14]
vss
dq[8]
dq[13]
dq[12]
vss
vss
m_ck
[1]
dq[19]
dq[18]
dqs[2]
dqs#
[2]
dm[2]
dq[21]
dq[20]
dq[3]
dq[2]
dqs[0]
dqs#
[0]
dm[0]
dq[5]
dq[4]
m_cal
[0]
vss
35
ma[2]
m_ck#
[1]
vss
dq[23]
dq[22]
vss
dq[17]
dq[16]
vss
vss
m_cal
[1]
vss
34
ma[1]
ma[3]
ma[4]
ma[6]
vss
ma[5]
ma[8]
ma[7]
ma[9]
m_rst# m_vref
vss
33
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vcc3
p3pllx
vss
vcc1
p2x
vssplld
vcc1
p2plld
vss
vcc1
p2x
vss
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vss
vcc1
p2x
vss
vcc1
p2x
vcc1
p2x
vss
vcc1
p2x
vss
vss
vcc1
p2x
vcc1
p2x
vss
vss
vss
dq[7]
36
dq[6]
vss
dq[1]
dq[0]
vss
ba[2]
cke[0]
cke[1]
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
32
vcc1
p2x
vss
vcc3
p3
vcc3
p3
vss
tck
vss
trst#
31
vss
vcc1
p2x
vss
vcc1
p2x
vcc3
p3
vcc3
p3
vcc3
p3
tdo
tms
tdi
30
vcc1
p2x
vss
vcc1
p2x
vss
vcc3
p3
scl1
sda2
sda1
scl0
smb
clk
29
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vcc3
p3
scl2
vss
sda0
vss
smb
dat
28
vcc1
p2x
vss
vcc1
p2x
vcc1
p2x
vcc1
p2x
vcc1
p2x
vcc1
p2x
vcc1
p2x
vcc1
p2x
vcc1
p2x
vcc1
p2x
vcc1
p2x
27
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vcc1
p8e
vcc1
p8e
vcc1
p8e
vcc1
p8e
vcc1
p8e
vcc1
p8e
26
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p8e
vcc1
p8e
vsse
vsse
vsse
vsse
25
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vcc1
p2ae
vcc1
p8e
petn
[7]
petp
[7]
pern
[7]
perp
[7]
24
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2
vss
vcc1
p2ae
vcc1
p8e
petn
[6]
petp
[6]
pern
[6]
perp
[6]
23
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2
vss
vcc1
p2
vcc1
p2ae
vcc1
p8e
vsse
vsse
vsse
vsse
22
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2ae
vcc1
p8e
petn
[5]
petp
[5]
pern
[5]
perp
[5]
21
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
refclkp
nc
nc
pe_
calp
petn
[4]
petp
[4]
pern
[4]
perp
[4]
20
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
refclkn
nc
nc
pe_
caln
vsse
vsse
vsse
vsse
19
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vcc1
p2ae
vcc1
p8e
petn
[3]
petp
[3]
pern
[3]
perp
[3]
18
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2ae
vcc1
p8e
petn
[2]
petp
[2]
pern
[2]
perp
[2]
17
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vcc1
p2ae
vcc1
p2e
vsse
vsse
vsse
vsse
16
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2ae
vcc1
p2e
petn
[1]
petp
[1]
pern
[1]
perp
[1]
15
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vcc1
p2e
vcc1
p2e
petn
[0]
petp
[0]
pern
[0]
perp
[0]
14
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2e
vcc1
p2e
vsse
vsse
vsse
vsse
13
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vcc1
p2
vcc1
p2
vcc1
p2
vcc1
p2
vcc1
p2
vcc1
p2
12
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc3
p3
pce#
[1]
a[21]
a[19]
a[18]
a[22]
11
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vcc3
p3
a[20]
vss
pce#
[0]
vss
a[13]
10
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc3
p3
nc
a[9]
a[12]
a[8]
a[14]
9
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vcc3
p3
PUR1
a[10]
pb_
rstout#
a[1]
a[6]
8
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc3
p3
a[11]
vss
a[15]
vss
a[2]
7
vccvio
vccvio
vcc3
p3
vccvio
vccvio
vcc3
p3
vccvio
vccvio
vcc3
p3
vccvio
vccvio
vcc3
p3
vcc3
p3
d[15]
a[16]
a[17]
a[3]
a[7]
6
p_ad
[4]
vccvio
p_
cbe#
[7]
p_
par64
vccvio
p_ad
[56]
p_ad
[52]
vccvio
p_ad
[44]
p_ad
[40]
vccvio
p_ad
[32]
d[10]
vcc3
p3
d[9]
d[4]
a[4]
a[5]
5
p_ad
[6]
p_ad
[0]
vss
p_
cbe#
[5]
p_ad
[60]
vss
p_ad
[54]
p_ad
[48]
vss
p_ad
[42]
p_ad
[36]
vss
poe#
d[2]
vss
d[3]
d[8]
d[1]
4
p_ad
[5]
p_ad
[2]
p_
req64#
p_ad
[63]
p_ad
[62]
p_ad
[58]
p_ad
[51]
p_ad
[50]
p_ad
[46]
p_ad
[39]
p_ad
[38]
p_ad
[34]
pwe#
d[12]
d[11]
a[23]
d[0]
vss
3
p_ad
[7]
p_ad
[1]
vss
p_
cbe#
[4]
p_ad
[59]
vss
p_ad
[53]
p_ad
[47]
vss
p_ad
[41]
p_ad
[35]
vss
d[14]
d[6]
d[5]
a[0]
vss
p_ad
[8]
p_ad
[3]
p_
ack64#
p_
cbe#
[6]
p_ad
[61]
p_ad
[57]
p_ad
[55]
p_ad
[49]
p_ad
[45]
p_ad
[43]
p_ad
[37]
p_ad
[33]
a[24]
d[7]
d[13]
vss
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
AL
AM
AN
AP
AR
ma[11] ma[12]
2
1
AT
AU
Intel® 81341 and 81342 I/O Processors
Datasheet
41
Intel® 81341 and 81342—Package Information
Figure 6.
Intel® 81341 and 81342 I/O processors Ballout — Package Bottom (Left Side)
AU
AT
AR
AP
AN
AM
AL
AK
AJ
AH
dqs[1]
dq[15]
dq[11]
dq[28]
dq[14]
dq[10]
vss
vss
AG
AF
AE
dq[24]
dq[25]
dqs#
[3]
AD
AC
AB
dqs[3]
dq[31]
dq[27]
dq[29]
dm[3]
vss
dq[30]
dq[26]
vss
dqs[2]
dq[18]
dq[22]
dq[23]
AA
Y
W
cb[0]
cb[1]
dqs#
[8]
cb[4]
cb[5]
dqs[8]
dq[19]
m_ck
[1]
vss
dm[8]
vss
m_ck#
[1]
ma[2]
m_ck
[0]
vss
dm[1]
dq[9]
dqs#
[1]
dq[12]
dq[13]
dq[8]
vss
dq[5]
dm[0]
dqs#
[0]
dqs[0]
dq[2]
dq[3]
dq[20]
dq[21]
dm[2]
dqs#
[2]
dq[0]
dq[1]
vss
dq[6]
dq[7]
vss
vss
dq[16]
dq[17]
vss
m_vref m_rst# cke[1]
cke[0]
ba[2]
vss
ma[9]
ma[7]
ma[8]
ma[5]
vss
ma[6]
ma[4]
ma[3]
ma[1]
vss
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vss
vcc3
p3
vcc3
p3
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
tdo
vcc3
p3
vcc3
p3
vcc3
p3
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
scl0
sda1
sda2
scl1
vcc3
p3
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc3
p3pllx
nc
smb
dat
vss
sda0
vss
scl2
vcc3
p3
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
27
vcc1
p2x
vcc1
p2x
vcc1
p2x
vcc1
p2x
vcc1
p2x
vcc1
p2x
vcc1
p2x
vcc1
p2x
vcc1
p2x
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
26
vcc1
p8e
vcc1
p8e
vcc1
p8e
vcc1
p8e
vcc1
p8e
vcc1
p8e
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
25
vsse
vsse
vsse
vsse
vcc1
p8e
vcc1
p8e
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
24
perp
[7]
pern
[7]
petp
[7]
petn
[7]
vcc1
p8e
vcc1
p2ae
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
23
perp
[6]
pern
[6]
petp
[6]
petn
[6]
vcc1
p8e
vcc1
p2ae
vss
vcc1
p2
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
22
vsse
vsse
vsse
vsse
vcc1
p8e
vcc1
p2ae
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
21
perp
[5]
pern
[5]
petp
[5]
petn
[5]
vcc1
p8e
vcc1
p2ae
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
20
perp
[4]
pern
[4]
petp
[4]
petn
[4]
pe_
calp
nc
nc
refclkp
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
19
vsse
vsse
vsse
vsse
pe_
caln
nc
nc
refclkn
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
18
perp
[3]
pern
[3]
petp
[3]
petn
[3]
vcc1
p8e
vcc1
p2ae
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
17
perp
[2]
pern
[2]
petp
[2]
petn
[2]
vcc1
p8e
vcc1
p2ae
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
16
vsse
vsse
vsse
vsse
vcc1
p2e
vcc1
p2ae
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
15
perp
[1]
pern
[1]
petp
[1]
petn
[1]
vcc1
p2e
vcc1
p2ae
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
14
perp
[0]
pern
[0]
petp
[0]
petn
[0]
vcc1
p2e
vcc1
p2e
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
13
vsse
vsse
vsse
vsse
vcc1
p2e
vcc1
p2e
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
12
vcc1
p2
vcc1
p2
vcc1
p2
vcc1
p2
vcc1
p2
vcc1
p2
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
11
a[22]
a[18]
a[19]
a[21]
pce#
[1]
vcc3
p3
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
10
a[13]
vss
pce#
[0]
vss
a[20]
vcc3
p3
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
9
a[14]
a[8]
a[12]
a[9]
nc
vcc3
p3
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
8
a[6]
a[1]
pb_
rstout#
a[10]
PUR1
vcc3
p3
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
7
a[2]
vss
a[15]
vss
a[11]
vcc3
p3
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
6
a[7]
a[3]
a[17]
a[16]
d[15]
vcc3
p3
vcc3
p3
vccvio
vccvio
vcc3
p3
vccvio
vccvio
vcc3
p3
vccvio
vccvio
vcc3
p3
vccvio
vccvio
vcc3
p3
5
a[5]
a[4]
d[4]
d[9]
vcc3
p3
d[10]
p_ad
[32]
vccvio
p_ad
[40]
p_ad
[44]
vccvio
p_ad
[52]
p_ad
[56]
vccvio
p_
par64
p_
cbe#
[7]
vccvio
p_ad
[4]
p_ad
[9]
37
36
vss
35
vss
m_cal
[0]
dq[4]
34
vss
m_cal
[1]
vss
33
vss
32
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
31
trst#
vss
tck
30
tdi
tms
29
smb
clk
28
4
3
d[1]
vss
2
d[8]
d[0]
vss
1
AU
AT
d[3]
a[23]
a[0]
vss
d[11]
d[5]
d[2]
d[12]
d[6]
vcc1 vssplld
p2plld
poe#
vss
p_ad
[36]
p_ad
[42]
vss
p_ad
[48]
p_ad
[54]
vss
p_ad
[60]
p_
cbe#
[5]
vss
p_ad
[0]
p_ad
[6]
vss
pwe#
p_ad
[34]
p_ad
[38]
p_ad
[39]
p_ad
[46]
p_ad
[50]
p_ad
[51]
p_ad
[58]
p_ad
[62]
p_ad
[63]
p_
req64#
p_ad
[2]
p_ad
[5]
p_
cbe#
[0]
d[14]
vss
p_ad
[35]
p_ad
[41]
vss
p_ad
[47]
p_ad
[53]
vss
p_ad
[59]
p_
cbe#
[4]
vss
p_ad
[1]
p_ad
[7]
vss
p_ad
[37]
p_ad
[43]
p_ad
[45]
p_ad
[49]
p_ad
[55]
p_ad
[57]
p_ad
[61]
p_
cbe#
[6]
p_
ack64#
p_ad
[3]
p_ad
[8]
vss
AK
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Y
W
vss
d[13]
d[7]
a[24]
p_ad
[33]
AR
AP
AN
AM
AL
Intel® 81341 and 81342 I/O Processors
Datasheet
42
ma[12] ma[11]
December 2007
Order Number: 315039-003US
Package Information—Intel® 81341 and 81342
Figure 7.
Intel® 81341 and 81342 I/O processors Ballout — Package Bottom (Right
Side)
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
cb[6]
cb[2]
dq[44]
dq[40]
dq[41]
dqs#
[5]
dqs[5]
dq[47]
dq[43]
dq[60]
dq[56]
dq[57]
dqs#
[7]
dqs[7]
dq[63]
vss
cb[3]
vss
cb[7]
vss
m_ck# dq[36]
[2]
B
37
dq[45]
dm[5]
vss
dq[46]
dq[42]
vss
vss
dq[61]
dm[7]
vss
dq[62]
dq[58]
dq[59]
vss
dq[37]
dm[4]
dqs#
[4]
dqs[4]
dq[34]
dq[35]
dq[52]
dq[53]
dm[6]
dqs#
[6]
dqs[6]
dq[50]
dq[51]
nc
dq[48]
dq[49]
m_ck#
[0]
m_ck
[2]
vss
dq[32]
dq[33]
vss
dq[38]
dq[39]
vss
vss
ma[0]
ba[1]
ma[10]
ba[0]
ras#
cs#[0]
vss
we#
cas#
odt[0]
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
therm
da
vsspllx
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
therm
dc
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vss
vcc1
p2x
vcc1
p2x
vss
vss
A
36
vss
35
vss
dq[54]
dq[55]
vss
nc
nc
34
odt[1]
vss
nc
ma[14] a
nc
nc
33
vcc3
p3
vcc3
p3
nc
nc
nc
nc
nc
32
vcc1
p2x
vcc3
p3
nc
nc
nc
nc
nc
nc
31
vss
vcc1
p2x
vss
vcc3
p3
nc
nc
vss
nc
vss
nc
30
vcc1
p2x
vss
vcc1
p2x
vcc3
p3
nc
nc
nc
nc
nc
nc
29
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc3
p3
nc
nc
nc
nc
nc
nc
28
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vcc3
p3
nc
nc
vss
nc
vss
nc
27
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc3
p3
nc
nc
nc
nc
nc
nc
26
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vcc3
p3
nc
nc
nc
nc
nc
nc
25
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2
vss
vcc1
p2
vcc1
p2
vcc1
p2
vss
vss
vss
vss
24
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2
vcc1
p2
vcc1
p2
vcc1
p2
nc
nc
nc
nc
23
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2
vss
vcc1
p2
vcc1
p2
vcc1
p2
nc
nc
nc
nc
22
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vss
nc
nc
nc
vss
vss
vss
vss
21
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
nc
nc
nc
nc
nc
nc
nc
20
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vcc1
p8
vcc1
p8
vcc1
p8
nc
nc
nc
nc
19
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p8
vcc1
p8
vcc1
p8
vss
vss
vss
vss
18
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vss
vcc1
p2
nc
nc
nc
nc
17
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vss
vss
nc
nc
nc
nc
nc
nc
nc
16
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vcc1
p2
vss
nc
nc
nc
vss
vss
vss
vss
15
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vss
vcc1
p2
vss
nc
nc
nc
nc
14
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vcc1
p2
vss
vcc1
p2
nc
nc
nc
nc
13
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vcc1
p2
vss
vss
vss
vss
vss
12
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc3
p3
gpio[6] gpio[5] gpio[7] gpio[3] gpio[1]
11
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vcc3
p3
gpio[4]
vss
gpio[2]
vss
gpio[0]
10
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc3
p3
xint#
[7]
xint#
[4]
xint#
[5]
xint#
[3]
xint#
[1]
9
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vcc3
p3
xint#
[6]
xint#
[0]
xint#
[2]
8
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc3
p3
hpi#
vss
hs_enu
m#
7
vcc3
p3
vccvio
vcc3
p3
vcc3
p3
vccvio
vcc3
p3
vccvio
vccvio
vcc3
p3
vcc3
p3
vccvio
vcc3
p3
vcc3
p3
u0_
rxd
u0_
rts#
6
p_ad
[13]
vccvio p_trdy# p_ad
[16]
p_ad
[26]
vccvio
p_ad
[31]
vss
p_ad
[24]
p_ad
[30]
vss
p_ad
[22]
p_ad
[23]
p_ad
[28]
p_ad
[27]
vss
p_ad
[21]
p_ad
[25]
vss
p_ad
[17]
p_ad
[19]
p_
cbe#
[3]
p_ad
[29]
N
M
L
K
p_ad
[11]
p_
par
vss
p_ad
p_devs
[15] p_stop# el#
p_ad
[10]
p_
cbe#
[1]
V
U
vss
vccvio p_idsel
p_frame p_ad
#
[20]
p_ad
[12]
p_m66e p_ad
n
[14]
vcc1
p2pllp vsspllp
p_ad
[18]
p_
p_pcixc cbe#
ap
[2]
p_serr# p_perr# p_irdy#
T
R
P
ma[13] cs#[1]
p_gnt#[ vccvio p_gnt#[ p_cal
0]
3]
[0]
p_gnt#[
p_
1]
req#[3]
nc
nc
p_gnt#[
p_
2]
req#[2]
nc
p_
p_
req#[0] req#[1]
J
vss
H
vss
nc
G
hs_led_ nmi0#
out
nmi1#
vss
hs_freq[ hs_freq[
hs_lstat
0]
1]
vcc3
p3
nc
u1_
rxd
u0_
txd
u0_
cts#
5
p_bmi
warm_r
st#
vss
u1_
rts#
u1_
txd
u1_
cts#
4
p_cal
[1]
nc
p_cal
[2]
vss
3
p_rst#
vss
p_clkout p_clko
[0]
p_rstout p_clko p_clkin
#
[1]
F
E
p_clko p_clko
[2]
[3]
D
vss
2
vss
C
1
B
A
a. MA[14] only needed for 4GB memory support, otherwise this pin is NC.
December 2007
Order Number: 315039-003US
Intel® 81341 and 81342 I/O Processors
Datasheet
43
Intel® 81341 and 81342—Package Information
Table 14.
Intel® 81341 and 81342 I/O processors 1357-Lead Package—Alphabetical
Ball Listings (Sheet 1 of 11)
Ball
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
B1
B2
B3
B4
B5
B6
Signal
–
–
vss
u1_cts#
u0_cts#
u0_rts#
hs_enum#
xint#[2]
xint#[1]
gpio[0]
gpio[1]
vss
nc
nc
vss
nc
nc
vss
nc
nc
vss
nc
nc
vss
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
vss
–
–
–
vss
p_clko[3]
u1_txd
u0_txd
u0_rxd
Intel® 81341 and 81342 I/O Processors
Datasheet
44
Ball
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
Signal
vss
xint#[0]
xint#[3]
vss
gpio[3]
vss
nc
nc
vss
nc
nc
vss
nc
nc
vss
nc
nc
vss
nc
nc
vss
nc
nc
vss
nc
nc
nc
nc
nc
vss
–
vss
p_clko[0]
p_clko[2]
u1_rts#
u1_rxd
hs_lstat
hpi#
xint#[6]
xint#[5]
gpio[2]
gpio[7]
vss
Ball
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35
C36
C37
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
Signal
nc
nc
vss
nc
nc
vss
nc
nc
vss
nc
nc
vss
nc
nc
nc
nc
nc
nc
nc
nc
ma[14]a
vss
dq[51]
dq[59]
vss
p_clkin
p_clkout
p_cal[2]
vss
nc
hs_freq[1]
vss
nmi0#
xint#[4]
vss
gpio[5]
vss
nc
nc
vss
nc
nc
vss
December 2007
Order Number: 315039-003US
Package Information—Intel® 81341 and 81342
Table 14.
Intel® 81341 and 81342 I/O processors 1357-Lead Package—Alphabetical
Ball Listings (Sheet 2 of 11)
Ball
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
December 2007
Order Number: 315039-003US
Signal
nc
nc
vss
nc
nc
vss
nc
nc
vss
nc
nc
vss
nc
nc
nc
dq[55]
dq[50]
dq[58]
dq[63]
p_clko[1]
vss
nc
warm_rst#
vcc3p3
hs_freq[0]
nmi1#
hs_led_out
xint#[7]
gpio[4]
gpio[6]
vss
vcc1p2
vss
nc
nc
vcc1p2
vcc1p8
vcc1p8
nc
nc
vcc1p2
vcc1p2
vcc1p2
Ball
E25
E26
E27
E28
E29
E30
E31
E32
E33
E34
E35
E36
E37
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
F26
F27
F28
F29
F30
Signal
nc
nc
nc
nc
nc
nc
nc
nc
vss
dq[54]
dqs[6]
dq[62]
dqs[7]
p_rstout#
p_rst#
p_cal[1]
p_bmi
p_cal[0]
vcc3p3
vcc3p3
vcc3p3
vcc3p3
vcc3p3
vcc3p3
vcc1p2
vss
vcc1p2
nc
nc
vss
vcc1p8
vcc1p8
nc
nc
vcc1p2
vcc1p2
vcc1p2
nc
nc
nc
nc
nc
nc
Ball
F31
F32
F33
F34
F35
F36
F37
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
G23
G24
G25
G26
G27
G28
G29
G30
G31
G32
G33
G34
G35
G36
Signal
nc
vcc3p3
odt[1]
vss
dqs#[6]
vss
dqs#[7]
nc
vss
p_req#[2]
vss
p_gnt#[3]
vcc3p3
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vcc1p2
vss
nc
nc
vss
vcc1p8
vcc1p8
nc
nc
vcc1p2
vcc1p2
vcc1p2
vcc3p3
vcc3p3
vcc3p3
vcc3p3
vcc3p3
vcc3p3
vcc3p3
vcc3p3
cs#[1]
dq[49]
dm[6]
dm[7]
Intel® 81341 and 81342 I/O Processors
Datasheet
45
Intel® 81341 and 81342—Package Information
Table 14.
Intel® 81341 and 81342 I/O processors 1357-Lead Package—Alphabetical
Ball Listings (Sheet 3 of 11)
Ball
G37
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
H21
H22
H23
H24
H25
H26
H27
H28
H29
H30
H31
H32
H33
H34
H35
H36
H37
J1
J2
J3
J4
J5
Signal
dq[57]
p_req#[1]
nc
p_gnt#[2]
p_req#[3]
vccvio
vccvio
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vss
vss
vcc1p2
vss
vcc1p2
vss
vss
vss
vcc1p2
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vcc1p8
ma[13]
dq[48]
dq[53]
dq[61]
dq[56]
p_req#[0]
nc
nc
p_gnt#[1]
p_gnt#[0]
Intel® 81341 and 81342 I/O Processors
Datasheet
46
Ball
J6
J7
J8
J9
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
J21
J22
J23
J24
J25
J26
J27
J28
J29
J30
J31
J32
J33
J34
J35
J36
J37
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
Signal
vcc3p3
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vcc1p2
vss
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p8
odt[0]
vss
dq[52]
vss
dq[60]
p_ad[29]
vss
p_ad[27]
vss
p_ad[31]
vcc3p3
vcc1p2
vss
vcc1p2
vss
vcc1p2
Ball
K12
K13
K14
K15
K16
K17
K18
K19
K20
K21
K22
K23
K24
K25
K26
K27
K28
K29
K30
K31
K32
K33
K34
K35
K36
K37
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
L12
L13
L14
L15
L16
L17
Signal
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vcc1p8
cas#
vss
dq[35]
vss
dq[43]
p_cbe#[3]
p_ad[25]
p_ad[28]
p_ad[30]
vccvio
vccvio
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
December 2007
Order Number: 315039-003US
Package Information—Intel® 81341 and 81342
Table 14.
Intel® 81341 and 81342 I/O processors 1357-Lead Package—Alphabetical
Ball Listings (Sheet 4 of 11)
Ball
L18
L19
L20
L21
L22
L23
L24
L25
L26
L27
L28
L29
L30
L31
L32
L33
L34
L35
L36
L37
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
M15
M16
M17
M18
M19
M20
M21
M22
M23
December 2007
Order Number: 315039-003US
Signal
vcc1p2
vss
vcc1p2
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p8
we#
dq[39]
dq[34]
dq[42]
dq[47]
p_ad[19]
p_ad[21]
p_ad[23]
p_ad[24]
p_ad[26]
vccvio
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2x
Ball
M24
M25
M26
M27
M28
M29
M30
M31
M32
M33
M34
M35
M36
M37
N1
N2
N3
N4
N5
N6
N7
N8
N9
N10
N11
N12
N13
N14
N15
N16
N17
N18
N19
N20
N21
N22
N23
N24
N25
N26
N27
N28
N29
Signal
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vcc1p8
vss
dq[38]
dqs[4]
dq[46]
dqs[5]
p_ad[17]
vss
p_ad[22]
vss
p_idsel
vcc3p3
vss
vcc1p2
vss
vcc1p2
vsspllp
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
Ball
N30
N31
N32
N33
N34
N35
N36
N37
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P31
P32
P33
P34
P35
Signal
vcc1p2x
vss
vcc1p8
cs#[0]
vss
dqs#[4]
vss
dqs#[5]
p_irdy#
p_cbe#[2]
p_ad[18]
p_ad[20]
vccvio
vccvio
vcc1p2
vss
vcc1p2
vss
vcc1p2pllp
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vcc1p8
ras#
dq[33]
dm[4]
Intel® 81341 and 81342 I/O Processors
Datasheet
47
Intel® 81341 and 81342—Package Information
Table 14.
Intel® 81341 and 81342 I/O processors 1357-Lead Package—Alphabetical
Ball Listings (Sheet 5 of 11)
Ball
P36
P37
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
R26
R27
R28
R29
R30
R31
R32
R33
R34
R35
R36
R37
T1
T2
T3
T4
Signal
dm[5]
dq[41]
p_perr#
p_pcixcap
p_devsel#
p_frame#
p_ad[16]
vcc3p3
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p8
ba[0]
dq[32]
dq[37]
dq[45]
dq[40]
p_serr#
vss
p_stop#
vss
Intel® 81341 and 81342 I/O Processors
Datasheet
48
Ball
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
T26
T27
T28
T29
T30
T31
T32
T33
T34
T35
T36
T37
U1
U2
U3
U4
U5
U6
U7
U8
U9
U10
Signal
p_trdy#
vcc3p3
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vcc1p8
ma[10]
vss
dq[36]
vss
dq[44]
p_ad[14]
p_cbe#[1]
p_ad[15]
p_par
vccvio
vccvio
vss
vcc1p2
vss
vcc1p2
Ball
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
U23
U24
U25
U26
U27
U28
U29
U30
U31
U32
U33
U34
U35
U36
U37
V1
V2
V3
V4
V5
V6
V7
V8
V9
V10
V11
V12
V13
V14
V15
V16
Signal
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vsspllx
vcc1p2x
vss
vcc1p8
ba[1]
m_ck[2]
m_ck#[2]
cb[3]
cb[2]
p_m66en
p_ad[10]
p_ad[12]
p_ad[11]
p_ad[13]
vcc3p3
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
December 2007
Order Number: 315039-003US
Package Information—Intel® 81341 and 81342
Table 14.
Intel® 81341 and 81342 I/O processors 1357-Lead Package—Alphabetical
Ball Listings (Sheet 6 of 11)
Ball
V17
V18
V19
V20
V21
V22
V23
V24
V25
V26
V27
V28
V29
V30
V31
V32
V33
V34
V35
V36
V37
W1
W2
W3
W4
W5
W6
W7
W8
W9
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22
December 2007
Order Number: 315039-003US
Signal
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
thermdc
thermda
vss
vcc1p2x
vcc1p8
ma[0]
m_ck#[0]
vss
cb[7]
cb[6]
vss
vss
p_cbe#[0]
vss
p_ad[9]
vcc3p3
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2x
Ball
W23
W24
W25
W26
W27
W28
W29
W30
W31
W32
W33
W34
W35
W36
W37
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
Y23
Y24
Y25
Y26
Y27
Y28
Signal
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
nc
vcc1p2x
vss
vcc1p8
vss
m_ck[0]
dm[8]
dqs[8]
dqs#[8]
p_ad[8]
p_ad[7]
p_ad[5]
p_ad[6]
p_ad[4]
vccvio
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
Ball
Y29
Y30
Y31
Y32
Y33
Y34
Y35
Y36
Y37
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
AA9
AA10
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AA24
AA25
AA26
AA27
AA28
AA29
AA30
AA31
AA32
AA33
AA34
Signal
vcc3p3pllx
vss
vcc1p2x
vcc1p8
ma[1]
ma[2]
vss
cb[5]
cb[1]
p_ad[3]
p_ad[1]
p_ad[2]
p_ad[0]
vccvio
vccvio
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p8
ma[3]
m_ck#[1]
Intel® 81341 and 81342 I/O Processors
Datasheet
49
Intel® 81341 and 81342—Package Information
Table 14.
Intel® 81341 and 81342 I/O processors 1357-Lead Package—Alphabetical
Ball Listings (Sheet 7 of 11)
Ball
AA35
AA36
AA37
AB1
AB2
AB3
AB4
AB5
AB6
AB7
AB8
AB9
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
AB23
AB24
AB25
AB26
AB27
AB28
AB29
AB30
AB31
AB32
AB33
AB34
AB35
AB36
AB37
AC1
AC2
AC3
Signal
m_ck[1]
cb[4]
cb[0]
p_ack64#
vss
p_req64#
vss
p_cbe#[7]
vcc3p3
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vcc1p8
ma[4]
vss
dq[19]
vss
dq[27]
p_cbe#[6]
p_cbe#[4]
p_ad[63]
Intel® 81341 and 81342 I/O Processors
Datasheet
50
Ball
AC4
AC5
AC6
AC7
AC8
AC9
AC10
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
AC24
AC25
AC26
AC27
AC28
AC29
AC30
AC31
AC32
AC33
AC34
AC35
AC36
AC37
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
Signal
p_cbe#[5]
p_par64
vccvio
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vssplld
vcc1p2x
vss
vcc1p8
ma[6]
dq[23]
dq[18]
dq[26]
dq[31]
p_ad[61]
p_ad[59]
p_ad[62]
p_ad[60]
vccvio
vccvio
vcc1p2
vss
vcc1p2
Ball
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
AD32
AD33
AD34
AD35
AD36
AD37
AE1
AE2
AE3
AE4
AE5
AE6
AE7
AE8
AE9
AE10
AE11
AE12
AE13
AE14
AE15
Signal
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2plld
vss
vcc1p2x
vcc1p8
vss
dq[22]
dqs[2]
dq[30]
dqs[3]
p_ad[57]
vss
p_ad[58]
vss
p_ad[56]
vcc3p3
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
December 2007
Order Number: 315039-003US
Package Information—Intel® 81341 and 81342
Table 14.
Intel® 81341 and 81342 I/O processors 1357-Lead Package—Alphabetical
Ball Listings (Sheet 8 of 11)
Ball
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AE26
AE27
AE28
AE29
AE30
AE31
AE32
AE33
AE34
AE35
AE36
AE37
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
AF16
AF17
AF18
AF19
AF20
AF21
December 2007
Order Number: 315039-003US
Signal
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p8
ma[5]
vss
dqs#[2]
vss
dqs#[3]
p_ad[55]
p_ad[53]
p_ad[51]
p_ad[54]
p_ad[52]
vccvio
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
Ball
AF22
AF23
AF24
AF25
AF26
AF27
AF28
AF29
AF30
AF31
AF32
AF33
AF34
AF35
AF36
AF37
AG1
AG2
AG3
AG4
AG5
AG6
AG7
AG8
AG9
AG10
AG11
AG12
AG13
AG14
AG15
AG16
AG17
AG18
AG19
AG20
AG21
AG22
AG23
AG24
AG25
AG26
AG27
Signal
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vcc1p8
ma[8]
dq[17]
dm[2]
dm[3]
dq[25]
p_ad[49]
p_ad[47]
p_ad[50]
p_ad[48]
vccvio
vccvio
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
Ball
AG28
AG29
AG30
AG31
AG32
AG33
AG34
AG35
AG36
AG37
AH1
AH2
AH3
AH4
AH5
AH6
AH7
AH8
AH9
AH10
AH11
AH12
AH13
AH14
AH15
AH16
AH17
AH18
AH19
AH20
AH21
AH22
AH23
AH24
AH25
AH26
AH27
AH28
AH29
AH30
AH31
AH32
AH33
Signal
vcc1p2x
vss
vcc1p2x
vss
vcc1p8
ma[7]
dq[16]
dq[21]
dq[29]
dq[24]
p_ad[45]
vss
p_ad[46]
vss
p_ad[44]
vcc3p3
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vcc1p8
ma[9]
Intel® 81341 and 81342 I/O Processors
Datasheet
51
Intel® 81341 and 81342—Package Information
Table 14.
Intel® 81341 and 81342 I/O processors 1357-Lead Package—Alphabetical
Ball Listings (Sheet 9 of 11)
Ball
AH34
AH35
AH36
AH37
AJ1
AJ2
AJ3
AJ4
AJ5
AJ6
AJ7
AJ8
AJ9
AJ10
AJ11
AJ12
AJ13
AJ14
AJ15
AJ16
AJ17
AJ18
AJ19
AJ20
AJ21
AJ22
AJ23
AJ24
AJ25
AJ26
AJ27
AJ28
AJ29
AJ30
AJ31
AJ32
AJ33
AJ34
AJ35
AJ36
AJ37
AK1
AK2
Signal
vss
dq[20]
vss
dq[28]
p_ad[43]
p_ad[41]
p_ad[39]
p_ad[42]
p_ad[40]
vccvio
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2x
vss
vcc1p2x
vcc1p2x
vcc1p2x
vss
vcc1p2x
vss
vcc1p8
ma[11]
vss
dq[3]
vss
dq[11]
p_ad[37]
p_ad[35]
Intel® 81341 and 81342 I/O Processors
Datasheet
52
Ball
AK3
AK4
AK5
AK6
AK7
AK8
AK9
AK10
AK11
AK12
AK13
AK14
AK15
AK16
AK17
AK18
AK19
AK20
AK21
AK22
AK23
AK24
AK25
AK26
AK27
AK28
AK29
AK30
AK31
AK32
AK33
AK34
AK35
AK36
AK37
AL1
AL2
AL3
AL4
AL5
AL6
AL7
AL8
Signal
p_ad[38]
p_ad[36]
vccvio
vccvio
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
refclkn
refclkp
vcc1p2
vss
vcc1p2
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vcc1p8
ma[12]
dq[7]
dq[2]
dq[10]
dq[15]
p_ad[33]
vss
p_ad[34]
vss
p_ad[32]
vcc3p3
vss
vcc1p2
Ball
AL9
AL10
AL11
AL12
AL13
AL14
AL15
AL16
AL17
AL18
AL19
AL20
AL21
AL22
AL23
AL24
AL25
AL26
AL27
AL28
AL29
AL30
AL31
AL32
AL33
AL34
AL35
AL36
AL37
AM1
AM2
AM3
AM4
AM5
AM6
AM7
AM8
AM9
AM10
AM11
AM12
AM13
AM14
Signal
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
nc
nc
vss
vcc1p2
vss
vcc1p2x
vss
vcc1p2x
vcc1p2x
vcc1p2x
vss
vcc1p2x
vss
vcc1p8
vss
dq[6]
dqs[0]
dq[14]
dqs[1]
a[24]
d[14]
pwe#
poe#
d[10]
vcc3p3
vcc3p3
vcc3p3
vcc3p3
vcc3p3
vcc3p3
vcc1p2
vcc1p2e
vcc1p2e
December 2007
Order Number: 315039-003US
Package Information—Intel® 81341 and 81342
Table 14.
Intel® 81341 and 81342 I/O processors 1357-Lead Package—Alphabetical
Ball Listings (Sheet 10 of 11)
Ball
AM15
AM16
AM17
AM18
AM19
AM20
AM21
AM22
AM23
AM24
AM25
AM26
AM27
AM28
AM29
AM30
AM31
AM32
AM33
AM34
AM35
AM36
AM37
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10
AN11
AN12
AN13
AN14
AN15
AN16
AN17
AN18
AN19
AN20
December 2007
Order Number: 315039-003US
Signal
vcc1p2ae
vcc1p2ae
vcc1p2ae
vcc1p2ae
nc
nc
vcc1p2ae
vcc1p2ae
vcc1p2ae
vcc1p2ae
vcc1p8e
vcc1p8e
vcc1p2x
vcc3p3
vcc3p3
vcc3p3
vcc3p3
vcc1p8
ba[2]
vss
dqs#[0]
vss
dqs#[1]
d[7]
d[6]
d[12]
d[2]
vcc3p3
d[15]
a[11]
PUR1
nc
a[20]
pce#[1]
vcc1p2
vcc1p2e
vcc1p2e
vcc1p2e
vcc1p2e
vcc1p8e
vcc1p8e
pe_caln
pe_calp
Ball
AN21
AN22
AN23
AN24
AN25
AN26
AN27
AN28
AN29
AN30
AN31
AN32
AN33
AN34
AN35
AN36
AN37
AP1
AP2
AP3
AP4
AP5
AP6
AP7
AP8
AP9
AP10
AP11
AP12
AP13
AP14
AP15
AP16
AP17
AP18
AP19
AP20
AP21
AP22
AP23
AP24
AP25
AP26
Signal
vcc1p8e
vcc1p8e
vcc1p8e
vcc1p8e
vcc1p8e
vcc1p8e
vcc1p2x
scl2
scl1
vcc3p3
vcc3p3
vcc1p8
cke[0]
dq[1]
dm[0]
dq[8]
dq[9]
d[13]
d[5]
d[11]
vss
d[9]
a[16]
vss
a[10]
a[9]
vss
a[21]
vcc1p2
vsse
petn[0]
petn[1]
vsse
petn[2]
petn[3]
vsse
petn[4]
petn[5]
vsse
petn[6]
petn[7]
vsse
vcc1p8e
Ball
AP27
AP28
AP29
AP30
AP31
AP32
AP33
AP34
AP35
AP36
AP37
AR1
AR2
AR3
AR4
AR5
AR6
AR7
AR8
AR9
AR10
AR11
AR12
AR13
AR14
AR15
AR16
AR17
AR18
AR19
AR20
AR21
AR22
AR23
AR24
AR25
AR26
AR27
AR28
AR29
AR30
AR31
AR32
Signal
vcc1p2x
vss
sda2
vcc3p3
vss
vcc1p8
cke[1]
dq[0]
dq[5]
dq[13]
dm[1]
vss
a[0]
a[23]
d[3]
d[4]
a[17]
a[15]
pb_rstout#
a[12]
pce#[0]
a[19]
vcc1p2
vsse
petp[0]
petp[1]
vsse
petp[2]
petp[3]
vsse
petp[4]
petp[5]
vsse
petp[6]
petp[7]
vsse
vcc1p8e
vcc1p2x
sda0
sda1
tdo
tck
vcc1p8
Intel® 81341 and 81342 I/O Processors
Datasheet
53
Intel® 81341 and 81342—Package Information
Table 14.
Intel® 81341 and 81342 I/O processors 1357-Lead Package—Alphabetical
Ball Listings (Sheet 11 of 11)
Ball
Signal
Ball
Signal
Ball
Signal
AR33
m_rst#
AT23
pern[6]
AU13
vsse
AR34
vss
AT24
pern[7]
AU14
perp[0]
AR35
dq[4]
AT25
vsse
AU15
perp[1]
AR36
dq[12]
AT26
vcc1p8e
AU16
vsse
AR37
vss
AT27
vcc1p2x
AU17
perp[2]
AT1
–
AT28
vss
AU18
perp[3]
AT2
vss
AT29
scl0
AU19
vsse
AT3
d[0]
AT30
tms
AU20
perp[4]
AT4
d[8]
AT31
vss
AU21
perp[5]
AT5
a[4]
AT32
vcc1p8
AU22
vsse
AT6
a[3]
AT33
m_vref
AU23
perp[6]
AT7
vss
AT34
m_cal[1]
AU24
perp[7]
AT8
a[1]
AT35
m_cal[0]
AU25
vsse
AT9
a[8]
AT36
vss
AU26
vcc1p8e
AT10
vss
AT37
–
AU27
vcc1p2x
AT11
a[18]
AU1
–
AU28
smbdat
AT12
vcc1p2
AU2
–
AU29
smbclk
AT13
vsse
AU3
vss
AU30
tdi
AT14
pern[0]
AU4
d[1]
AU31
trst#
AT15
pern[1]
AU5
a[5]
AU32
vcc1p8
AT16
vsse
AU6
a[7]
AU33
vss
AT17
pern[2]
AU7
a[2]
AU34
vss
AT18
pern[3]
AU8
a[6]
AU35
vss
AT19
vsse
AU9
a[14]
AU36
–
AT20
pern[4]
AU10
a[13]
AU37
–
AT21
pern[5]
AU11
a[22]
AT22
vsse
AU12
vcc1p2
a. MA[14] is only needed for 4GB memory support. When 4GB memory is not used this pin can be a NC.
Intel® 81341 and 81342 I/O Processors
Datasheet
54
December 2007
Order Number: 315039-003US
Package Information—Intel® 81341 and 81342
Table 15.
Intel® 81341 and 81342 I/O processors 1357-Lead Package—Alphabetical
Signal Listings (Sheet 1 of 11)
Signal
Ball
Signal
Ball
Signal
Ball
–
A1
cb[2]
U37
dq[8]
AN36
–
A2
cb[3]
U36
dq[9]
AN37
–
A36
cb[4]
AA36
dq[10]
AK36
–
A37
cb[5]
Y36
dq[11]
AJ37
–
B1
cb[6]
V37
dq[12]
AR36
–
B37
cb[7]
V36
dq[13]
AP36
–
AT1
cke[0]
AN33
dq[14]
AL36
–
AT37
cke[1]
AP33
dq[15]
AK37
–
AU1
cs#[0]
N33
dq[16]
AG34
–
AU2
cs#[1]
G33
dq[17]
AF34
–
AU36
d[0]
AT3
dq[18]
AC35
–
AU37
d[1]
AU4
dq[19]
AB35
a[0]
AR2
d[2]
AN4
dq[20]
AH35
a[1]
AT8
d[3]
AR4
dq[21]
AG35
a[2]
AU7
d[4]
AR5
dq[22]
AD34
a[3]
AT6
d[5]
AP2
dq[23]
AC34
a[4]
AT5
d[6]
AN2
dq[24]
AG37
a[5]
AU5
d[7]
AN1
dq[25]
AF37
AC36
a[6]
AU8
d[8]
AT4
dq[26]
a[7]
AU6
d[9]
AP5
dq[27]
AB37
a[8]
AT9
d[10]
AM5
dq[28]
AH37
a[9]
AP9
d[11]
AP3
dq[29]
AG36
a[10]
AP8
d[12]
AN3
dq[30]
AD36
a[11]
AN7
d[13]
AP1
dq[31]
AC37
a[12]
AR9
d[14]
AM2
dq[32]
R34
a[13]
AU10
d[15]
AN6
dq[33]
P34
a[14]
AU9
dm[0]
AN35
dq[34]
L35
a[15]
AR7
dm[1]
AP37
dq[35]
K35
a[16]
AP6
dm[2]
AF35
dq[36]
T35
a[17]
AR6
dm[3]
AF36
dq[37]
R35
M34
a[18]
AT11
dm[4]
P35
dq[38]
a[19]
AR11
dm[5]
P36
dq[39]
L34
a[20]
AN10
dm[6]
G35
dq[40]
R37
a[21]
AP11
dm[7]
G36
dq[41]
P37
a[22]
AU11
dm[8]
W35
dq[42]
L36
a[23]
AR3
dq[0]
AP34
dq[43]
K37
a[24]
AM1
dq[1]
AN34
dq[44]
T37
ba[0]
R33
dq[2]
AK35
dq[45]
R36
ba[1]
U33
dq[3]
AJ35
dq[46]
M36
ba[2]
AM33
dq[4]
AR35
dq[47]
L37
cas#
K33
dq[5]
AP35
dq[48]
H34
cb[0]
AA37
dq[6]
AL34
dq[49]
G34
cb[1]
Y37
dq[7]
AK34
dq[50]
D35
December 2007
Order Number: 315039-003US
Intel® 81341 and 81342 I/O Processors
Datasheet
55
Intel® 81341 and 81342—Package Information
Table 15.
Intel® 81341 and 81342 I/O processors 1357-Lead Package—Alphabetical
Signal Listings (Sheet 2 of 11)
Signal
Ball
Signal
Ball
Signal
Ball
dq[51]
C35
hs_led_out
E8
nc
A34
dq[52]
J35
hs_lstat
C6
nc
B13
dq[53]
H35
m_cal[0]
AT35
nc
B14
dq[54]
E34
m_cal[1]
AT34
nc
B16
dq[55]
D34
m_ck#[0]
V34
nc
B17
dq[56]
H37
m_ck#[1]
AA34
nc
B19
dq[57]
G37
m_ck#[2]
U35
nc
B20
dq[58]
D36
m_ck[0]
W34
nc
B22
dq[59]
C36
m_ck[1]
AA35
nc
B23
dq[60]
J37
m_ck[2]
U34
nc
B25
dq[61]
H36
m_rst#
AR33
nc
B26
dq[62]
E36
m_vref
AT33
nc
B28
dq[63]
D37
ma[0]
V33
nc
B29
dqs#[0]
AM35
ma[1]
Y33
nc
B31
dqs#[1]
AM37
ma[2]
Y34
nc
B32
dqs#[2]
AE35
ma[3]
AA33
nc
B33
dqs#[3]
AE37
ma[4]
AB33
nc
B34
dqs#[4]
N35
ma[5]
AE33
nc
B35
dqs#[5]
N37
ma[6]
AC33
nc
C13
dqs#[6]
F35
ma[7]
AG33
nc
C14
dqs#[7]
F37
ma[8]
AF33
nc
C16
dqs#[8]
W37
ma[9]
AH33
nc
C17
dqs[0]
AL35
ma[10]
T33
nc
C19
dqs[1]
AL37
ma[11]
AJ33
nc
C20
dqs[2]
AD35
ma[12]
AK33
nc
C22
dqs[3]
AD37
ma[13]
H33
nc
C23
dqs[4]
M35
nc
A13
nc
C25
dqs[5]
M37
nc
A14
nc
C26
dqs[6]
E35
nc
A16
nc
C27
dqs[7]
E37
nc
A17
nc
C28
dqs[8]
W36
nc
A19
nc
C29
gpio[0]
A10
nc
A20
nc
C30
gpio[1]
A11
nc
A22
nc
C31
gpio[2]
C10
nc
A23
nc
C32
a
C33
gpio[3]
B11
nc
A25
ma[14]
gpio[4]
E10
nc
A26
nc
D5
gpio[5]
D11
nc
A27
nc
D13
gpio[6]
E11
nc
A28
nc
D14
gpio[7]
C11
nc
A29
nc
D16
hpi#
C7
nc
A30
nc
D17
hs_enum#
A7
nc
A31
nc
D19
hs_freq[0]
E6
nc
A32
nc
D20
hs_freq[1]
D6
nc
A33
nc
D22
Intel® 81341 and 81342 I/O Processors
Datasheet
56
December 2007
Order Number: 315039-003US
Package Information—Intel® 81341 and 81342
Table 15.
Intel® 81341 and 81342 I/O processors 1357-Lead Package—Alphabetical
Signal Listings (Sheet 3 of 11)
Signal
Ball
Signal
Ball
Signal
Ball
nc
D23
nc
AM19
p_ad[35]
AK2
nc
D25
nc
AM20
p_ad[36]
AK4
nc
D26
nc
AN9
p_ad[37]
AK1
nc
D28
nmi0#
D8
p_ad[38]
AK3
nc
D29
nmi1#
E7
p_ad[39]
AJ3
nc
D31
odt[0]
J33
p_ad[40]
AJ5
nc
D32
odt[1]
F33
p_ad[41]
AJ2
nc
D33
p_ack64#
AB1
p_ad[42]
AJ4
nc
E3
p_ad[0]
AA4
p_ad[43]
AJ1
nc
E15
p_ad[1]
AA2
p_ad[44]
AH5
nc
E16
p_ad[2]
AA3
p_ad[45]
AH1
nc
E20
p_ad[3]
AA1
p_ad[46]
AH3
nc
E21
p_ad[4]
Y5
p_ad[47]
AG2
nc
E25
p_ad[5]
Y3
p_ad[48]
AG4
nc
E26
p_ad[6]
Y4
p_ad[49]
AG1
nc
E27
p_ad[7]
Y2
p_ad[50]
AG3
nc
E28
p_ad[8]
Y1
p_ad[51]
AF3
nc
E29
p_ad[9]
W5
p_ad[52]
AF5
nc
E30
p_ad[10]
V2
p_ad[53]
AF2
nc
E31
p_ad[11]
V4
p_ad[54]
AF4
nc
E32
p_ad[12]
V3
p_ad[55]
AF1
nc
F15
p_ad[13]
V5
p_ad[56]
AE5
nc
F16
p_ad[14]
U1
p_ad[57]
AE1
nc
F20
p_ad[15]
U3
p_ad[58]
AE3
nc
F21
p_ad[16]
R5
p_ad[59]
AD2
nc
F25
p_ad[17]
N1
p_ad[60]
AD4
nc
F26
p_ad[18]
P3
p_ad[61]
AD1
nc
F27
p_ad[19]
M1
p_ad[62]
AD3
nc
F28
p_ad[20]
P4
p_ad[63]
AC3
nc
F29
p_ad[21]
M2
p_bmi
F4
nc
F30
p_ad[22]
N3
p_cal[0]
F5
nc
F31
p_ad[23]
M3
p_cal[1]
F3
nc
G1
p_ad[24]
M4
p_cal[2]
D3
nc
G15
p_ad[25]
L2
p_cbe#[0]
W3
nc
G16
p_ad[26]
M5
p_cbe#[1]
U2
nc
G20
p_ad[27]
K3
p_cbe#[2]
P2
nc
G21
p_ad[28]
L3
p_cbe#[3]
L1
nc
H2
p_ad[29]
K1
p_cbe#[4]
AC2
nc
J2
p_ad[30]
L4
p_cbe#[5]
AC4
nc
J3
p_ad[31]
K5
p_cbe#[6]
AC1
nc
W29
p_ad[32]
AL5
p_cbe#[7]
AB5
nc
AL19
p_ad[33]
AL1
p_clkin
D1
nc
AL20
p_ad[34]
AL3
p_clko[0]
C2
December 2007
Order Number: 315039-003US
Intel® 81341 and 81342 I/O Processors
Datasheet
57
Intel® 81341 and 81342—Package Information
Table 15.
Intel® 81341 and 81342 I/O processors 1357-Lead Package—Alphabetical
Signal Listings (Sheet 4 of 11)
Signal
Ball
Signal
Ball
Signal
Ball
p_clko[1]
E1
perp[3]
AU18
u0_rxd
B6
p_clko[2]
C3
perp[4]
AU20
u0_txd
B5
p_clko[3]
B3
perp[5]
AU21
u1_cts#
A4
p_clkout
D2
perp[6]
AU23
u1_rts#
C4
p_devsel#
R3
perp[7]
AU24
u1_rxd
C5
p_frame#
R4
petn[0]
AP14
u1_txd
B4
p_gnt#[0]
J5
petn[1]
AP15
vcc1p2
E13
p_gnt#[1]
J4
petn[2]
AP17
vcc1p2
E17
p_gnt#[2]
H3
petn[3]
AP18
vcc1p2
E22
p_gnt#[3]
G5
petn[4]
AP20
vcc1p2
E23
p_idsel
N5
petn[5]
AP21
vcc1p2
E24
p_irdy#
P1
petn[6]
AP23
vcc1p2
F12
p_m66en
V1
petn[7]
AP24
vcc1p2
F14
p_par
U4
petp[0]
AR14
vcc1p2
F22
p_par64
AC5
petp[1]
AR15
vcc1p2
F23
p_pcixcap
R2
petp[2]
AR17
vcc1p2
F24
p_perr#
R1
petp[3]
AR18
vcc1p2
G8
p_req#[0]
J1
petp[4]
AR20
vcc1p2
G10
p_req#[1]
H1
petp[5]
AR21
vcc1p2
G12
p_req#[2]
G3
petp[6]
AR23
vcc1p2
G13
p_req#[3]
H4
petp[7]
AR24
vcc1p2
G22
p_req64#
AB3
poe#
AM4
vcc1p2
G23
G24
p_rst#
F2
pwe#
AM3
vcc1p2
p_rstout#
F1
ras#
P33
vcc1p2
H7
p_serr#
T1
refclkn
AK19
vcc1p2
H9
p_stop#
T3
refclkp
AK20
vcc1p2
H11
p_trdy#
T5
scl0
AT29
vcc1p2
H13
pb_rstout#
AR8
scl1
AN29
vcc1p2
H17
pce#[0]
AR10
scl2
AN28
vcc1p2
H19
pce#[1]
AN11
sda0
AR28
vcc1p2
H23
pe_caln
AN19
sda1
AR29
vcc1p2
J8
pe_calp
AN20
sda2
AP29
vcc1p2
J10
pern[0]
AT14
smbclk
AU29
vcc1p2
J12
pern[1]
AT15
smbdat
AU28
vcc1p2
J14
pern[2]
AT17
tck
AR31
vcc1p2
J15
pern[3]
AT18
tdi
AU30
vcc1p2
J18
AR30
vcc1p2
J20
V29
vcc1p2
J22
J24
pern[4]
AT20
tdo
pern[5]
AT21
thermda
pern[6]
AT23
thermdc
V28
vcc1p2
pern[7]
AT24
tms
AT30
vcc1p2
K7
perp[0]
AU14
trst#
AU31
vcc1p2
K9
perp[1]
AU15
u0_cts#
A5
vcc1p2
K11
perp[2]
AU17
u0_rts#
A6
vcc1p2
K13
Intel® 81341 and 81342 I/O Processors
Datasheet
58
December 2007
Order Number: 315039-003US
Package Information—Intel® 81341 and 81342
Table 15.
Intel® 81341 and 81342 I/O processors 1357-Lead Package—Alphabetical
Signal Listings (Sheet 5 of 11)
Signal
Ball
Signal
Ball
Signal
Ball
vcc1p2
K15
vcc1p2
T13
vcc1p2
AB9
vcc1p2
K17
vcc1p2
T15
vcc1p2
AB11
vcc1p2
K19
vcc1p2
T17
vcc1p2
AB13
vcc1p2
K21
vcc1p2
T19
vcc1p2
AB15
vcc1p2
L8
vcc1p2
T21
vcc1p2
AB17
vcc1p2
L10
vcc1p2
U8
vcc1p2
AB19
vcc1p2
L12
vcc1p2
U10
vcc1p2
AB21
vcc1p2
L14
vcc1p2
U12
vcc1p2
AC8
vcc1p2
L16
vcc1p2
U14
vcc1p2
AC10
vcc1p2
L18
vcc1p2
U16
vcc1p2
AC12
vcc1p2
L20
vcc1p2
U18
vcc1p2
AC14
vcc1p2
M7
vcc1p2
U20
vcc1p2
AC16
vcc1p2
M9
vcc1p2
V7
vcc1p2
AC18
vcc1p2
M11
vcc1p2
V9
vcc1p2
AC20
vcc1p2
M13
vcc1p2
V11
vcc1p2
AD7
vcc1p2
M15
vcc1p2
V13
vcc1p2
AD9
vcc1p2
M17
vcc1p2
V15
vcc1p2
AD11
vcc1p2
M19
vcc1p2
V17
vcc1p2
AD13
vcc1p2
M21
vcc1p2
V19
vcc1p2
AD15
vcc1p2
N8
vcc1p2
V21
vcc1p2
AD17
vcc1p2
N10
vcc1p2
W8
vcc1p2
AD19
vcc1p2
N12
vcc1p2
W10
vcc1p2
AD21
vcc1p2
N14
vcc1p2
W12
vcc1p2
AE8
vcc1p2
N16
vcc1p2
W14
vcc1p2
AE10
vcc1p2
N18
vcc1p2
W16
vcc1p2
AE12
vcc1p2
N20
vcc1p2
W18
vcc1p2
AE14
vcc1p2
P7
vcc1p2
W20
vcc1p2
AE16
vcc1p2
P9
vcc1p2
Y7
vcc1p2
AE18
vcc1p2
P13
vcc1p2
Y9
vcc1p2
AE20
vcc1p2
P15
vcc1p2
Y11
vcc1p2
AF7
vcc1p2
P17
vcc1p2
Y13
vcc1p2
AF9
vcc1p2
P19
vcc1p2
Y15
vcc1p2
AF11
vcc1p2
P21
vcc1p2
Y17
vcc1p2
AF13
vcc1p2
R8
vcc1p2
Y19
vcc1p2
AF15
vcc1p2
R10
vcc1p2
Y21
vcc1p2
AF17
vcc1p2
R12
vcc1p2
AA8
vcc1p2
AF19
vcc1p2
R14
vcc1p2
AA10
vcc1p2
AF21
vcc1p2
R16
vcc1p2
AA12
vcc1p2
AG8
vcc1p2
R18
vcc1p2
AA14
vcc1p2
AG10
vcc1p2
R20
vcc1p2
AA16
vcc1p2
AG12
vcc1p2
T7
vcc1p2
AA18
vcc1p2
AG14
vcc1p2
T9
vcc1p2
AA20
vcc1p2
AG16
vcc1p2
T11
vcc1p2
AB7
vcc1p2
AG18
December 2007
Order Number: 315039-003US
Intel® 81341 and 81342 I/O Processors
Datasheet
59
Intel® 81341 and 81342—Package Information
Table 15.
Intel® 81341 and 81342 I/O processors 1357-Lead Package—Alphabetical
Signal Listings (Sheet 6 of 11)
Signal
Ball
Signal
Ball
Signal
Ball
vcc1p2
AG20
vcc1p2ae
AM22
vcc1p2x
R22
vcc1p2
AH7
vcc1p2ae
AM23
vcc1p2x
R24
vcc1p2
AH9
vcc1p2ae
AM24
vcc1p2x
R26
vcc1p2
AH11
vcc1p2e
AM13
vcc1p2x
R28
vcc1p2
AH13
vcc1p2e
AM14
vcc1p2x
R30
vcc1p2
AH15
vcc1p2e
AN13
vcc1p2x
T23
vcc1p2
AH17
vcc1p2e
AN14
vcc1p2x
T25
vcc1p2
AH19
vcc1p2e
AN15
vcc1p2x
T27
vcc1p2
AH21
vcc1p2e
AN16
vcc1p2x
T29
vcc1p2
AJ8
vcc1p2plld
AD29
vcc1p2x
T31
vcc1p2
AJ10
vcc1p2pllp
P11
vcc1p2x
U22
vcc1p2
AJ12
vcc1p2x
H25
vcc1p2x
U24
vcc1p2
AJ14
vcc1p2x
H27
vcc1p2x
U26
vcc1p2
AJ16
vcc1p2x
H29
vcc1p2x
U28
vcc1p2
AJ18
vcc1p2x
H31
vcc1p2x
U30
vcc1p2
AJ20
vcc1p2x
J26
vcc1p2x
V23
vcc1p2
AJ22
vcc1p2x
J28
vcc1p2x
V25
vcc1p2
AK7
vcc1p2x
J30
vcc1p2x
V27
vcc1p2
AK9
vcc1p2x
K23
vcc1p2x
V31
vcc1p2
AK11
vcc1p2x
K25
vcc1p2x
W22
vcc1p2
AK13
vcc1p2x
K27
vcc1p2x
W24
vcc1p2
AK15
vcc1p2x
K29
vcc1p2x
W26
vcc1p2
AK17
vcc1p2x
K31
vcc1p2x
W28
vcc1p2
AK21
vcc1p2x
L22
vcc1p2x
W30
vcc1p2
AK23
vcc1p2x
L24
vcc1p2x
Y23
vcc1p2
AL8
vcc1p2x
L26
vcc1p2x
Y25
vcc1p2
AL10
vcc1p2x
L28
vcc1p2x
Y27
vcc1p2
AL12
vcc1p2x
L30
vcc1p2x
Y31
vcc1p2
AL14
vcc1p2x
M23
vcc1p2x
AA22
vcc1p2
AL16
vcc1p2x
M25
vcc1p2x
AA24
vcc1p2
AL18
vcc1p2x
M27
vcc1p2x
AA26
vcc1p2
AL22
vcc1p2x
M29
vcc1p2x
AA28
vcc1p2
AM12
vcc1p2x
M31
vcc1p2x
AA30
vcc1p2
AN12
vcc1p2x
N22
vcc1p2x
AB23
vcc1p2
AP12
vcc1p2x
N24
vcc1p2x
AB25
vcc1p2
AR12
vcc1p2x
N26
vcc1p2x
AB27
vcc1p2
AT12
vcc1p2x
N28
vcc1p2x
AB29
vcc1p2
AU12
vcc1p2x
N30
vcc1p2x
AB31
vcc1p2ae
AM15
vcc1p2x
P23
vcc1p2x
AC22
vcc1p2ae
AM16
vcc1p2x
P25
vcc1p2x
AC24
vcc1p2ae
AM17
vcc1p2x
P27
vcc1p2x
AC26
vcc1p2ae
AM18
vcc1p2x
P29
vcc1p2x
AC28
vcc1p2ae
AM21
vcc1p2x
P31
vcc1p2x
AC30
Intel® 81341 and 81342 I/O Processors
Datasheet
60
December 2007
Order Number: 315039-003US
Package Information—Intel® 81341 and 81342
Table 15.
Intel® 81341 and 81342 I/O processors 1357-Lead Package—Alphabetical
Signal Listings (Sheet 7 of 11)
Signal
Ball
Signal
Ball
Signal
Ball
vcc1p2x
AD23
vcc1p2x
AU27
vcc1p8e
AN23
vcc1p2x
AD25
vcc1p8
E18
vcc1p8e
AN24
vcc1p2x
AD27
vcc1p8
E19
vcc1p8e
AN25
vcc1p2x
AD31
vcc1p8
F18
vcc1p8e
AN26
vcc1p2x
AE22
vcc1p8
F19
vcc1p8e
AP26
vcc1p2x
AE24
vcc1p8
G18
vcc1p8e
AR26
vcc1p2x
AE26
vcc1p8
G19
vcc1p8e
AT26
vcc1p2x
AE28
vcc1p8
H32
vcc1p8e
AU26
vcc1p2x
AE30
vcc1p8
J32
vcc3p3
E5
vcc1p2x
AF23
vcc1p8
K32
vcc3p3
F6
vcc1p2x
AF25
vcc1p8
L32
vcc3p3
F7
vcc1p2x
AF27
vcc1p8
M32
vcc3p3
F8
vcc1p2x
AF29
vcc1p8
N32
vcc3p3
F9
vcc1p2x
AF31
vcc1p8
P32
vcc3p3
F10
vcc1p2x
AG22
vcc1p8
R32
vcc3p3
F11
vcc1p2x
AG24
vcc1p8
T32
vcc3p3
F32
vcc1p2x
AG26
vcc1p8
U32
vcc3p3
G6
vcc1p2x
AG28
vcc1p8
V32
vcc3p3
G25
vcc1p2x
AG30
vcc1p8
W32
vcc3p3
G26
vcc1p2x
AH23
vcc1p8
Y32
vcc3p3
G27
vcc1p2x
AH25
vcc1p8
AA32
vcc3p3
G28
vcc1p2x
AH27
vcc1p8
AB32
vcc3p3
G29
vcc1p2x
AH29
vcc1p8
AC32
vcc3p3
G30
vcc1p2x
AH31
vcc1p8
AD32
vcc3p3
G31
vcc1p2x
AJ24
vcc1p8
AE32
vcc3p3
G32
vcc1p2x
AJ26
vcc1p8
AF32
vcc3p3
J6
vcc1p2x
AJ27
vcc1p8
AG32
vcc3p3
K6
vcc1p2x
AJ28
vcc1p8
AH32
vcc3p3
N6
vcc1p2x
AJ30
vcc1p8
AJ32
vcc3p3
R6
vcc1p2x
AK25
vcc1p8
AK32
vcc3p3
T6
vcc1p2x
AK27
vcc1p8
AL32
vcc3p3
V6
vcc1p2x
AK29
vcc1p8
AM32
vcc3p3
W6
vcc1p2x
AK31
vcc1p8
AN32
vcc3p3
AB6
vcc1p2x
AL24
vcc1p8
AP32
vcc3p3
AE6
vcc1p2x
AL26
vcc1p8
AR32
vcc3p3
AH6
vcc1p2x
AL27
vcc1p8
AT32
vcc3p3
AL6
vcc1p2x
AL28
vcc1p8
AU32
vcc3p3
AM6
vcc1p2x
AL30
vcc1p8e
AM25
vcc3p3
AM7
vcc1p2x
AM27
vcc1p8e
AM26
vcc3p3
AM8
vcc1p2x
AN27
vcc1p8e
AN17
vcc3p3
AM9
vcc1p2x
AP27
vcc1p8e
AN18
vcc3p3
AM10
vcc1p2x
AR27
vcc1p8e
AN21
vcc3p3
AM11
vcc1p2x
AT27
vcc1p8e
AN22
vcc3p3
AM28
December 2007
Order Number: 315039-003US
Intel® 81341 and 81342 I/O Processors
Datasheet
61
Intel® 81341 and 81342—Package Information
Table 15.
Intel® 81341 and 81342 I/O processors 1357-Lead Package—Alphabetical
Signal Listings (Sheet 8 of 11)
Signal
Ball
Signal
Ball
Signal
Ball
vcc3p3
AM29
vss
B21
vss
H16
vcc3p3
AM30
vss
B24
vss
H18
vcc3p3
AM31
vss
B27
vss
H20
vcc3p3
AN5
vss
B30
vss
H21
PUR1
AN8
vss
B36
vss
H22
vcc3p3
AN30
vss
C1
vss
H24
vcc3p3
AN31
vss
C12
vss
H26
vcc3p3
AP30
vss
C15
vss
H28
vcc3p3pllx
Y29
vss
C18
vss
H30
vccvio
H5
vss
C21
vss
J7
vccvio
H6
vss
C24
vss
J9
vccvio
L5
vss
C34
vss
J11
vccvio
L6
vss
C37
vss
J13
vccvio
M6
vss
D4
vss
J16
vccvio
P5
vss
D7
vss
J17
vccvio
P6
vss
D10
vss
J19
vccvio
U5
vss
D12
vss
J21
vccvio
U6
vss
D15
vss
J23
vccvio
Y6
vss
D18
vss
J25
vccvio
AA5
vss
D21
vss
J27
vccvio
AA6
vss
D24
vss
J29
vccvio
AC6
vss
D27
vss
J31
vccvio
AD5
vss
D30
vss
J34
vccvio
AD6
vss
E2
vss
J36
vccvio
AF6
vss
E12
vss
K2
vccvio
AG5
vss
E14
vss
K4
vccvio
AG6
vss
E33
vss
K8
vccvio
AJ6
vss
F13
vss
K10
vccvio
AK5
vss
F17
vss
K12
vccvio
AK6
vss
F34
vss
K14
vss
A3
vss
F36
vss
K16
vss
A12
vss
G2
vss
K18
vss
A15
vss
G4
vss
K20
vss
A18
vss
G7
vss
K22
vss
A21
vss
G9
vss
K24
vss
A24
vss
G11
vss
K26
vss
A35
vss
G14
vss
K28
vss
B2
vss
G17
vss
K30
vss
B7
vss
H8
vss
K34
vss
B10
vss
H10
vss
K36
vss
B12
vss
H12
vss
L7
vss
B15
vss
H14
vss
L9
vss
B18
vss
H15
vss
L11
Intel® 81341 and 81342 I/O Processors
Datasheet
62
December 2007
Order Number: 315039-003US
Package Information—Intel® 81341 and 81342
Table 15.
Intel® 81341 and 81342 I/O processors 1357-Lead Package—Alphabetical
Signal Listings (Sheet 9 of 11)
Signal
Ball
Signal
Ball
Signal
Ball
vss
L13
vss
P16
vss
U19
vss
L15
vss
P18
vss
U21
vss
L17
vss
P20
vss
U23
vss
L19
vss
P22
vss
U25
vss
L21
vss
P24
vss
U27
vss
L23
vss
P26
vss
U31
vss
L25
vss
P28
vss
V8
vss
L27
vss
P30
vss
V10
vss
L29
vss
R7
vss
V12
vss
L31
vss
R9
vss
V14
vss
M8
vss
R11
vss
V16
vss
M10
vss
R13
vss
V18
vss
M12
vss
R15
vss
V20
vss
M14
vss
R17
vss
V22
vss
M16
vss
R19
vss
V24
vss
M18
vss
R21
vss
V26
vss
M20
vss
R23
vss
V30
vss
M22
vss
R25
vss
V35
vss
M24
vss
R27
vss
W1
vss
M26
vss
R29
vss
W2
vss
M28
vss
R31
vss
W4
vss
M30
vss
T2
vss
W7
vss
M33
vss
T4
vss
W9
vss
N2
vss
T8
vss
W11
vss
N4
vss
T10
vss
W13
vss
N7
vss
T12
vss
W15
vss
N9
vss
T14
vss
W17
vss
N13
vss
T16
vss
W19
vss
N15
vss
T18
vss
W21
vss
N17
vss
T20
vss
W23
vss
N19
vss
T22
vss
W25
vss
N21
vss
T24
vss
W27
vss
N23
vss
T26
vss
W31
vss
N25
vss
T28
vss
W33
vss
N27
vss
T30
vss
Y8
vss
N29
vss
T34
vss
Y10
vss
N31
vss
T36
vss
Y12
vss
N34
vss
U7
vss
Y14
vss
N36
vss
U9
vss
Y16
vss
P8
vss
U11
vss
Y18
vss
P10
vss
U13
vss
Y20
vss
P12
vss
U15
vss
Y22
vss
P14
vss
U17
vss
Y24
December 2007
Order Number: 315039-003US
Intel® 81341 and 81342 I/O Processors
Datasheet
63
Intel® 81341 and 81342—Package Information
Table 15.
Intel® 81341 and 81342 I/O processors 1357-Lead Package—Alphabetical
Signal Listings (Sheet 10 of 11)
Signal
Ball
Signal
Ball
Signal
Ball
vss
Y26
vss
AC27
vss
AF30
vss
Y28
vss
AC31
vss
AG7
vss
Y30
vss
AD8
vss
AG9
vss
Y35
vss
AD10
vss
AG11
vss
AA7
vss
AD12
vss
AG13
vss
AA9
vss
AD14
vss
AG15
vss
AA11
vss
AD16
vss
AG17
vss
AA13
vss
AD18
vss
AG19
vss
AA15
vss
AD20
vss
AG21
vss
AA17
vss
AD22
vss
AG23
vss
AA19
vss
AD24
vss
AG25
vss
AA21
vss
AD26
vss
AG27
vss
AA23
vss
AD28
vss
AG29
vss
AA25
vss
AD30
vss
AG31
vss
AA27
vss
AD33
vss
AH2
vss
AA29
vss
AE2
vss
AH4
vss
AA31
vss
AE4
vss
AH8
vss
AB2
vss
AE7
vss
AH10
vss
AB4
vss
AE9
vss
AH12
vss
AB8
vss
AE11
vss
AH14
vss
AB10
vss
AE13
vss
AH16
vss
AB12
vss
AE15
vss
AH18
vss
AB14
vss
AE17
vss
AH20
vss
AB16
vss
AE19
vss
AH22
vss
AB18
vss
AE21
vss
AH24
vss
AB20
vss
AE23
vss
AH26
vss
AB22
vss
AE25
vss
AH28
vss
AB24
vss
AE27
vss
AH30
vss
AB26
vss
AE29
vss
AH34
vss
AB28
vss
AE31
vss
AH36
vss
AB30
vss
AE34
vss
AJ7
vss
AB34
vss
AE36
vss
AJ9
vss
AB36
vss
AF8
vss
AJ11
vss
AC7
vss
AF10
vss
AJ13
vss
AC9
vss
AF12
vss
AJ15
vss
AC11
vss
AF14
vss
AJ17
vss
AC13
vss
AF16
vss
AJ19
vss
AC15
vss
AF18
vss
AJ21
vss
AC17
vss
AF20
vss
AJ23
vss
AC19
vss
AF22
vss
AJ25
vss
AC21
vss
AF24
vss
AJ29
vss
AC23
vss
AF26
vss
AJ31
vss
AC25
vss
AF28
vss
AJ34
Intel® 81341 and 81342 I/O Processors
Datasheet
64
December 2007
Order Number: 315039-003US
Package Information—Intel® 81341 and 81342
Table 15.
Intel® 81341 and 81342 I/O processors 1357-Lead Package—Alphabetical
Signal Listings (Sheet 11 of 11)
Signal
Ball
Signal
Ball
Signal
Ball
vss
AJ36
vss
AM36
vsse
AR22
vss
AK8
vss
AP4
vsse
AR25
vss
AK10
vss
AP7
vsse
AT13
vss
AK12
vss
AP10
vsse
AT16
vss
AK14
vss
AP28
vsse
AT19
vss
AK16
vss
AP31
vsse
AT22
vss
AK18
vss
AR1
vsse
AT25
vss
AK22
vss
AR34
vsse
AU13
vss
AK24
vss
AR37
vsse
AU16
vss
AK26
vss
AT2
vsse
AU19
vss
AK28
vss
AT7
vsse
AU22
vss
AK30
vss
AT10
vsse
AU25
vss
AL2
vss
AT28
vssplld
AC29
vss
AL4
vss
AT31
vsspllp
N11
U29
vss
AL7
vss
AT36
vsspllx
vss
AL9
vss
AU3
warm_rst#
E4
vss
AL11
vss
AU33
we#
L33
vss
AL13
vss
AU34
xint#[0]
B8
vss
AL15
vss
AU35
xint#[1]
A9
vss
AL17
vsse
AP13
xint#[2]
A8
vss
AL21
vsse
AP16
xint#[3]
B9
vss
AL23
vsse
AP19
xint#[4]
D9
vss
AL25
vsse
AP22
xint#[5]
C9
vss
AL29
vsse
AP25
xint#[6]
C8
vss
AL31
vsse
AR13
xint#[7]
E9
vss
AL33
vsse
AR16
vss
AM34
vsse
AR19
a. MA[14] is only needed for 4GB memory support. When 4GB memory is not used this pin can be a NC.
December 2007
Order Number: 315039-003US
Intel® 81341 and 81342 I/O Processors
Datasheet
65
Intel® 81341 and 81342—Electrical Specifications
4.0
Electrical Specifications
Table 16.
Absolute Maximum Ratings
Parameter
Maximum Rating
Notice: This data sheet contains information on products in the design
phase of development. Do not
finalize a design with this information. Revised information will be
published when the product
becomes available. The specifications are subject to change without
notice. Contact your local Intel representative before finalizing a
design.
Storage temperature
–10° C to +45° C
Supply voltage VCC3P3 wrt. VSS
–0.5 V to +4.1 V
Supply voltage VCC1P8E wrt. VSSE
–0.5 V to +2.5 V
Supply voltage VCC1P8 wrt. VSS
–0.5 V to +2.5 V
Supply voltage VCCVIO wrt. VSS
–0.5 V to +4.1 V
Supply voltage VCC1P2X wrt. VSS
–0.5 V to +1.8 V
Supply voltage VCC1P2 wrt. VSS
–0.5 V to +1.8 V
Supply voltage VCC1P2AE wrt. VSSE
–0.5 V to +1.8 V
Supply voltage VCC1P2E wrt. VSSE
–0.5 V to +1.8 V
Voltage on any ball wrt. VSS
–0.5 V to VCCP +0.5 V
†WARNING: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage.
These are stress ratings only. Operation beyond the “Operating Conditions” is not recommended and extended
exposure beyond the “Operating Conditions” may affect device reliability.
Intel® 81341 and 81342 I/O Processors
Datasheet
66
December 2007
Order Number: 315039-003US
Electrical Specifications—Intel® 81341 and 81342
Table 17.
Operating Conditions
Symbol
VCC3P3
VCC1P8E
VCC1P8
VCCVIO
VCC1P2X
VCC1P2
VCC1P2E
VCC1P2AE
VCC1P2PLLP
VCC1P2PLLD
VCC3P3PLLX
M_VREF
TC
December 2007
Order Number: 315039-003US
Parameter
3.3 V supply voltage for PCI-X
category 2 signals and general purpose
I/Os
1.8 V supply voltage for PCI Express*
interface
1.8 V supply voltage for DDR2 SDRAM
memory interface I/Os
3.3 V supply voltage for PCI-X
category 1 signals
1.2 V supply voltage for Intel XScale®
processors
1.2 V supply voltage for most digital
logic
1.2 V supply voltage for PCI Express*
interface digital logic
1.2 V supply voltage for PCI Express*
interface analog logic
1.2 V supply voltage for PCI-X PLL
1.2 V supply voltage for DDR2 SDRAM
PLL processor logic PLL.
3.3 V supply voltage for processor
logic PLL
Memory I/O reference voltage
Case temperature under bias
Minimum
Maximum Units
3.0
3.6
V
1.71
1.89
V
1.71
1.89
V
3.0
3.6
V
1.164
1.236
V
1.164
1.236
V
1.164
1.236
V
1.164
1.236
V
1.164
1.236
V
1.164
1.236
V
3.0
3.6
V
0.49VCC1P8
0.51VCC1P8
V
0
100
°C
Notes
Intel® 81341 and 81342 I/O Processors
Datasheet
67
Intel® 81341 and 81342—Electrical Specifications
4.1
Figure 8.
VCCPLL Pin Requirements
To reduce clock jitter, the VCC1P2PLLD, VCC1P2PLLP, and VCC3P3PLLX balls for the
phase-lock loop (PLL) circuits are isolated on the package. The low-pass filters, as
shown in the following figures, reduce noise-induced clock jitter and its effects on
timing relationships in system design.
This paragraph pertains to the VCC1P2PLLD, VCC1P2PLLP, VCC3P3PLLX filters. The filter
components must be able to handle a DC current of 30 mA. Use a shielded type
inductor to minimize magnetic pickup. The total series resistance from the board VCC
plane (before the filter) to the VCCPLL ball must be less than 1.5 ohm (including
component and trace resistance). The total series resistance from the board VCC plane
(before the filter) to the top plate of the capacitor must be greater than 0.35 ohm
(including component and trace resistance). The nodes connecting VCCPLL and VSSPLL
to the capacitor must be as short as possible (less than 0.1 W). VCCPLL and VSSPLL
must be routed close to each other to minimize loop area. The VSSPLL balls must be
connected to the filter only and not to any other ground, as shown in Figure 8 and
Figure 9. The inductor and capacitor must be placed close to each other. Any discrete
resistor must be placed between the VCC board plane and the inductor. If the trace and
component resistance is high enough, a discrete resistor might not be required.
The bypass capacitor must be placed as close to the supply pins as possible. The series
impedances to both the supply pin and the PCB analog ground plane must be an order
of magnitude lower than the ESR and ESL specified for the capacitor.
VCC3P3PLLX Low-Pass Filter
4.7 uH, ±25%
VCC3P3PLLX
3.3V
22 µF ±20%, ESR < 0.3,
6.3 V, ESL < 2.5nH
(Board Plane)
(Not connected
to board ground)
Figure 9.
VSSPLLX
VCC1P2PLLD, VCC1P2PLLP Low-Pass Filter
VCC1P2PLLD /
VCC1P2PLLP
4.7 uH, ±25%
1.2V
(Board Plane)
22 µF, ±20%, ESR < 0.3,
6.3 V, ESL < 2.5nH
(Not connected
to board ground)
Intel® 81341 and 81342 I/O Processors
Datasheet
68
VSSPLLD/
VSSPLLP
December 2007
Order Number: 315039-003US
Electrical Specifications—Intel® 81341 and 81342
4.2
Targeted DC Specifications
Table 18.
DC Characteristics
Symbol
Parameter
VIL1
VIH1
VIL2
VIL3
VIH3
VIL4
VIH4
Input Low Voltage (General Purpose).
Input High Voltage (General Purpose).
Input Low Voltage (PCI).
Input Low Voltage (PCI-X).
Input High Voltage (PCI-X/PCI).
Input Low Voltage (DDR2 SDRAM).
Input High Voltage (DDR2 SDRAM).
VOL1
VOH1
VOL2
VOH2
Maximum
Unit
s
-0.3
0.3VCC3P3
V
2.0
VCC3P3 + 0.3
V
-0.5
0.3VCC3P3
V
-0.5
0.35VCC3P3
V
Minimum
VCC3P3 + 0.5
V
-0.3
M_VREF - 0.125
V
M_VREF + 0.125
VCC1P8 + 0.3
V
Output Low Voltage (General Purpose).
–
0.4
V
Output High Voltage (General Purpose).
2.6
–
V
Output Low Voltage (PCI-X).
–
0.1VCC3P3
V
Output High Voltage (PCI-X).
0.9VCC3P3
–
V
0.28
V
IOL = 11 mA
V
IOH = -11 mA
V
IOL = 5 mA
V
IOH = -5 mA
VOL3
VOH3
Output High Voltage
(DDR2 SDRAM driver set to 21Ω).
VOL4
Output Low Voltage
(DDR2 SDRAM driver set to 50Ω).
VOH4
Output High Voltage
(DDR2 SDRAM driver set to 50Ω).
ILI1
Input Leakage Current for General Purpose
pins when internal pull up resistors are not
enabled.
±5
µ
ILI2
Input Leakage Current for PCI-X pins when
internal pull up resistors are not enabled.
±10
µ
ILI3
Input Leakage Current for DDR2 pins when
internal pull up resistors are not enabled.
Internal pull up resistor value for General
Purpose pins.
Internal pull up resistor value for PCI-X pins.
±2
µ
RPCIX
CGP
CPCIX
CDDR2
LPIN
Notes:
1.
2.
3.
2
2
0.5V CC3P3
Output Low Voltage
(DDR2 SDRAM driver set to 21Ω).
RGP
Notes
1.42
0.28
1.42
A
A
A
28.5
38.7
ΚΩ
5.9
8.1
ΚΩ
General Purpose pin Capacitance.
1
4.5
pF
PCI-X pin Capacitance.
1
4.5
pF
DDR2 pin Capacitance.
1
4.5
pF
Ball Inductance.
1
12
nH
IOL = 10 mA
2
IOH = -10 mA
2
IOL = 1.50 mA
IOH = -0.50 mA
0 ≤ VIN ≤ VCC3P3
3
0 ≤ VIN ≤ VCC3P3 (Cat . 2)
0 ≤ VIN ≤ VCCVIO (Cat. 1)
3
0 ≤ VIN ≤ VCC1P8
3
1
1
1
1
1
1
Not tested, guaranteed by design.
General Purpose signals include all signals that are not part of the DDR2, PCI-X and PCI-Express interfaces and analog
pins.
Input leakage currents include hi-Z output leakage for all bi-directional buffers with tri-state outputs.
December 2007
Order Number: 315039-003US
Intel® 81341 and 81342 I/O Processors
Datasheet
69
Intel® 81341 and 81342—Electrical Specifications
Table 19.
ICC Characteristics
Symbol
Parameter
Power Supply Current:
• PCI Express A&D
• Intel XScale® michroarchitectures
- 800MHz
- 1200MHz
Power Supply Current:
Icc12 Active
• PCI Express A&D
Single Core
• Intel XScale® michroarchitectures
(81341)
- 800MHz
(Power Supply)
- 1200MHz
Power Supply Current:
Icc18 Active
• PCI Express I/Os
(Power Supply)
• DDR-II (533)
Power
Supply Current:
Icc33 Active
•
PCI,
PBI, GPIO
(Power Supply)
• PCI-X I/Os
Thermal Current:
• PCI Express A&D
Icc12 Active
Two Cores (81342) • Intel XScale® michroarchitecture:
(Thermal)
800MHz
1200MHz
Thermal Current:
Icc12 Active
• PCI Express A&D
Single Core
• Intel XScale® michroarchitecture:
(81341)
800MHz
(Thermal)
1200MHz
Thermal Current:
Icc18 Active
• PCI Express I/Os
(Thermal)
• DDR-II (533)
Thermal
Current::
Icc33 Active
•
PCI,
PBI, GPIO
(Thermal)
• PCI-X I/Os
Typ
Icc12 Active
Two Cores (81342)
(Power Supply)
Notes:
1.
2.
3.
4.
Max Units
6.93
7.69
6.53
7.28
1.52
0.69
4.82
6.00
4.48
5.62
1.31
0.58
Notes
A
1, 2, 4
A
1, 2, 4
A
1, 2, 4
A
1, 2
A
1, 3, 4
A
1, 3, 4
A
1, 3, 4
A
1, 3
Measured with the device operating and outputs loaded to the test condition in Figure 17, “AC Test
Load for all Signals Except PCI, PCI-Express and DDR2” on page 85.
Icc Active (Power Supply) value is provided for selecting the system power supply. This is based on
the worst case data patterns and skew material at the following worst case voltages: Vcc33 = 3.63 V,
Vcc18 = 1.89 V, Vcc12 = 1.24 V and ambient temperature = 55°C.
Icc Active (Thermal) value is provided for selecting the system thermal design power (TDP). This is
based on the following typical voltages: Vcc33 = 3.3 V, Vcc18 = 1.8 V, Vcc12 = 1.2 V and ambient
temperature = 55°C.
The Customer Reference Boards use a 1.2 V switching regulator for all the 1.2 V supplies (Vcc1p2,
Vcc1p2x, Vcc1p2e, Vcc1p2ae) and a 1.8 V switching regulator for all 1.8 V supplies: (Vcc1p8,
Vcc1p8e).
Intel® 81341 and 81342 I/O Processors
Datasheet
70
December 2007
Order Number: 315039-003US
Electrical Specifications—Intel® 81341 and 81342
4.3
Targeted AC Specifications
4.3.1
Clock Signal Timings
Table 20.
PCI Clock Timings
Symbol
TC1
TC2
TCH1
TCL1
TSR1
fmod
fspread
Parameter
PCI Clock Cycle Time
Jitter Class 1
PCI Clock Cycle Time
Jitter Class 2
PCI clock High Time
PCI clock Low Time
PCI clock Period Jitter
PCI clock Slew Rate
PCI-X 133 PCI-X 100 PCI-X 66
PCI 66
PCI 33
Units Notes
Min. Max Min. Max Min. Max Min. Max Min. Max
7.5
11
10
15
15
22
15
25
30
50
7.375
11
9.875
15
14.8
22
14.8
25
29.7
50
-125
4
3
3
125
1.5
2.5
2.5
125
1.5
-125
4
ns
1
1
5.5
5.5
10
ns
5.5
5.5
10
ns
200 -200 200 -200 300 -300 ps
1.5
4
1.5
4
1
4 V/ns
3
2
PCI Spread Spectrum Requirements
PCI clock modulation
frequency
PCI clock frequency
spread
30
33
30
33
30
33
30
33
KHz
-1
0
-1
0
-1
0
-1
0
%
PCI Output Clocks
Notes:
1.
2.
3.
4.
5.
PCI output clock skew
PCI output clock period
jitter
250
100
-100
350
150
-150
350
350
350
ps
150 -150 150 -150 150 -150
ps
4, 5
The clock frequency may not change beyond the spread-spectrum limits except while P_RST# or WARM_RST# is
asserted.
This slew rate must be met across the minimum peak-to-peak portion of the clock waveform.
Period jitter is the deviation between any single period of the clock and the average period of the clock.
If a jitter class 2 input clock is used, output clocks can not support jitter class 1.
The deviation between any single period of the clock and the average period of the clock.
December 2007
Order Number: 315039-003US
Intel® 81341 and 81342 I/O Processors
Datasheet
71
Intel® 81341 and 81342—Electrical Specifications
Table 21.
Symbol
TF2
TC2
DF0
TCCJ
TPPJ
Dc
Trise
Tfall
Tvrise
Tvfall
Vca
Vcr
Tvc
Vhi
Vli
Vrb
Vovs
Vuds
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
PCI Express* Clock Timings
Parameter
PCI Express* Clock Frequency
PCI Express* Clock Cycle Time
Frequency Variation
Cycle to Cycle Jitter
Peak to Peak Jitter (5–50 MHz)
Clock Duty Cycle
REFCLK Rise Time
REFCLK Fall Time
REFCLK Rise Time Variation
REFCLK Fall Time Variation
Rise-Fall Matching
Absolute Cross Point
Relative Cross Point
Total Variation of Vc over all edges
Rising Edge Ringback
Falling Edge Ringback
High Level Voltage
Low Level Voltage
Ringback Voltage
Maximum Overshoot
Minimum Undershoot
Min.
9.872
-300
Nom.
100
300
125
50
55
350
350
125
125
20
0.55
Calc
0.14
45
175
175
0.25
Calc
0.56
0.66
-0.15
Max.
0.71
0
0.25
0.85
0.15
0.10
Vhi+0.3
-0.30
Units
MHz
ns
ppm
ps
ps
%
ps
ps
ps
ps
%
V
V
V
V
V
V
V
V
V
Notes
4
1, 2, 7
1, 2, 7
1, 3, 8, 14
5, 13
14
Absolute Min.
Absolute Max.
8, 9
8, 10
8
8, 11
8, 12
Measured at crossing point where the instantaneous voltage value of the rising edge of REFCLK equals the falling edge
of REFCLK#.
Measured from VOL = 0.175 V to VOH = 0.525 V. Valid only for rising REFCLK and falling REFCLK#. Signal must be
monotonic through the VOL to VOH region for TRISE and TFALL.
This measurement refers to the total variation from the lowest crossing point to the highest, regardless of which edge is
crossing.
The average period over any 1 µs period of time must be greater than the minimum specified period.
VCROSS(rel) Min and Max are derived using the following:
VCROSS(rel) Min = 0.5 (Vhavg - 0.710) + 0.250
VCROSS(rel) Max = 0.5 (Vhavg - 0.710) + 0.550
(see for further clarification).
Measurement taken from single-ended waveform.
Measurement taken from differential waveform.
VHIGH is defined as the statistical average High value as obtained by using the Oscilloscope VHIGH Math function.
VLOW is defined as the statistical average Low value as obtained by using the Oscilloscope VLOW Math function.
Overshoot is defined as the absolute value of the maximum voltage.
Undershoot is defined as the absolute value of the minimum voltage.
The crossing point must meet the absolute and relative crossing point specifications simultaneously.
∆VCROSS is defined as the total variation of all crossing voltages of Rising REFCLK and Falling REFCLK#. This is the
maximum allowed variance in VCROSS for any particular system.
Refer to Section 4.3.2.1 in the PCI Express Base Specification for information regarding PPM considerations.
Intel® 81341 and 81342 I/O Processors
Datasheet
72
December 2007
Order Number: 315039-003US
Electrical Specifications—Intel® 81341 and 81342
Table 22.
DDR2 Output Clock Timings
Symbol
TC2
TCH2
TCL2
TCS2
Tskew2
Tskew3
Parameter
DDR2 SDRAM clock Cycle Time
Average
DDR2 SDRAM clock High Time
DDR2 SDRAM clock LowTime
DDR2 SDRAM clock Period Jitter
DDR2 SDRAM clock skew for any
differential clock pair to any other
clock pair
DDR2 SDRAM clock skew for any
clock pair to any system memory
strobe
December 2007
Order Number: 315039-003US
DDR2-400
Min.
Max
DDR2-533
Min.
Max
5.00
3.75
ns
2.25
2.25
100
1.69
1.69
100
-100
ns
ns
ps
250
250
ps
250
250
ps
-100
Units Notes
Intel® 81341 and 81342 I/O Processors
Datasheet
73
Intel® 81341 and 81342—Electrical Specifications
4.3.2
DDR2 SDRAM Interface Signal Timings
Table 23.
DDR2 SDRAM Signal Timings
Symbol
Tvb1
Tva1
Tvb2
Tva2
Tvb3
Tva3
Tvb4
Tva4
Tvb5
Tva5
Tis6
Tih6
Tov7
Notes:
1.
2.
3.
Parameter
Min.
DQ, CB and DM write output valid time before DQS
DQ, CB and DM write output valid time after DQS
DQS write output valid time before M_CK (DQS early)
DQS write output valid time after M_CK (DQS late)
MA, BA, RAS#, CAS#, WE# write output valid before M_CK
rising edge.
MA, BA, RAS#, CAS#, WE# write output valid after M_CK
rising edge.
CS#, CKE, ODT write output valid before M_CK rising edge.
Unbuffered mode
CS#, CKE, ODT write output valid after M_CK rising edge.
Unbuffered mode
CS#, CKE, ODT write output valid before M_CK rising edge.
Registered mode
CS#, CKE, ODT write output valid after M_CK rising edge.
Registered mode
DQ, CB read input setup time before DQS rising or falling
edges.
DQ, CB read input hold time after DQS rising or falling edges.
M_CK[2:0] output valid from P_CLKIN or REFCLK
0.530
0.530
Max
Units Notes
ns
ns
ns
ns
1, 3
1, 3
1, 3
1, 3
4.900
ns
1, 3
1.530
ns
1, 3
2.090
ns
1, 3
0.590
ns
1, 3
1.150
ns
1, 3
1.530
ns
1, 3
-0.670
ns
2
1.250
0.460 1.930
ns
ns
2
0.200
0.530
See Figure 14, “DDR2 SDRAM Write Timings” on page 84.
See Figure 15, “DQS Falling Edge Output Access Time to/from M_CK Rising Edge” on page 84.
Timings valid when the DQS delay is programmed for the default 90 degree phase shift.
See Figure 18, “AC Test Load for DDR2 SDRAM Signals” on page 85.
Intel® 81341 and 81342 I/O Processors
Datasheet
74
December 2007
Order Number: 315039-003US
Electrical Specifications—Intel® 81341 and 81342
4.3.3
Peripheral Bus Interface Signal Timings
Table 24.
Peripheral Bus Interface Signal Timings
Symbol
Parameter
Min.
Nom.
Max.
Units
A2D
D2D
REC
N
Address to Data wait-states
Data to Data wait-states
Recovery wait-states
Number of Data phases
4
4
1
1
-
20
20
20
4
clks
clks
clks
phases
Tasc
Taso
Tasw
Tah
Tahw
Address setup to CE#
Address setup to OE#
Address setup to WE#
Address hold from CE#,OE#
Address hold from WE#
25
10
25
Nom - 5
Nom - 5
-
ns
ns
ns
ns
ns
Twce
CE# pulse width
Nom - 5
-
ns
Twoe
OE# pulse width
Nom - 5
-
ns
Twwe
Tdsw
Tdhw
WE# pulse width
Write Data setup to WE#
Write Data hold from WE#
Nom - 5
Nom - 5
10
30
15
30
REC × 15
(REC+1) × 15
(A2D + 2 + ((N 1)(D2D + 2))) × 15
(A2D + 3 + ((N 1)(D2D + 2))) × 15
(A2D + 1) × 15
(A2D + 1) × 15
15
ns
ns
ns
Tad1
1st Read Data access time from Address
-
(A2D + 4) × 15
TadN
Nth Read Data access time from Address
-
(D2D + 2) × 15
Tcd
Read Data access time from CE#
-
(A2D + 2) × 15
Toe
Read Data access time from OE#
0
(A2D + 3) × 15
Tdh
Read Data hold time from Address, CE#, OE#
0
(REC + 2) × 15
20
Nom 11
Nom 11
Nom 11
Nom 11
Nom - 5
Notes:
1.
ns
ns
ns
ns
ns
See Figure 25, “PBI Output Timings” on page 88 and Figure 26, “PBI External Device Timings (Flash)” on page 89.
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Intel® 81341 and 81342—Electrical Specifications
4.3.4
I2C/SMBus Interface Signal Timings
Table 25.
I2C/SMBus Signal Timings
Symbol
FSCL
Parameter
SCL Clock Frequency
Std. Mode
Min. Max
0
100
TSUDAT
Bus Free Time Between STOP and START
Condition
Hold Time (repeated) START Condition
SCL Clock Low Time
SCL Clock High Time
Setup Time for a Repeated START Condition
Data Hold Time
Data Setup Time
TSR
SCL and SDA Rise Time
1000
TSF
SCL and SDA Fall Time
300
TSUSTO
Setup Time for STOP Condition
TBUF
THDSTA
TLOW
THIGH
TSUSTA
THDDAT
Notes:
1.
2.
3.
4.
5.
Fast Mode
Units Note
s
Min.
Max
0
400
4.7
1.3
4
4.7
4
4.7
0
250
0.6
1.3
0.6
0.6
0
100
20 +
0.1Cb
20 +
0.1Cb
0.6
3.45
4
KHz
µ
s
(1)
s
s
µs
µs
µs
ns
(1,3)
(1,2)
(1,2)
(1)
(1)
(1)
300
ns
(1,4)
300
ns
(1,4)
µ
µ
0.9
µ
s
(1)
See Figure 13, “I2C Interface Signal Timings” on page 83.
Not tested.
After this period, the first clock pulse is generated.
Cb = the total capacitance of one bus line, in pF.
Std Mode I2C signal timings apply for SMBus timing.
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Electrical Specifications—Intel® 81341 and 81342
4.3.5
PCI Bus Interface Signal Timings
Table 26.
PCI Signal Timings
Symbol
TOV1
TOF
TIS1
TIH1
TRST
TRF
TIS3
TIH2
TIS4
TIH3
Notes:
1.
2.
3.
4.
Parameter
Clock to Output Valid Delay
Clock to Output Float Delay
Input Setup to clock
Input Hold time from clock
Reset Active Time
Reset Active to output float
delay
REQ64# to Reset setup time
Reset to REQ64# hold time
PCI-X initialization pattern to
Reset setup time
Reset to PCI-X initialization
pattern hold time
PCI-X 133 PCI-X 66 PCI 66
PCI 33
PCI-X 100
Units
Min. Max Min. Max Min. Max Min. Max
0.7
1.2
0.5
1
3.7
7
0.7
1.7
0.5
1
40
3.7
7
1
3
0
1
40
10
0
10
50
10
0
10
50
0
50
0
50
6
14
2
7
0
1
40
10
0
50
11
28
40
10
0
50
ns
ns
ns
ns
ms
ns
clocks
ns
clocks
Notes
1, 3
1, 4
2
2
ns
See the timing measurement conditions in; Figure 11, “Output Timing Measurement Waveforms” on page 82.
See the timing measurement conditions in: Figure 12, “Input Timing Measurement Waveforms” on page 83.
See Figure 19, “PCI/PCI-X TOV(max) Rising Edge AC Test Load” on page 86,Figure 20, “PCI/PCI-X TOV(max) Falling
Edge AC Test Load” on page 86, Figure 21, “PCI/PCI-X TOV(min) AC Test Load” on page 86.
For purposes of Active/Float timing measurements, the Hi-Z or “off” state is defined to be when the total current
delivered through the component pin is less than or equal to the leakage current specification.
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77
Intel® 81341 and 81342—Electrical Specifications
4.3.6
PCI Express* Differential Transmitter (Tx) Output
Specifications
Table 27.
PCI Express* Rx Input Specifications
Symbol
VDIFFp-p
JTOTAL
VCM-AC
TReye
RL-DiffRX
RL-CMTX
ZRX-OUT-DC
ZRX-Match-DC
VRX-SQUELCH
CinRX
LSKEW-RX
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
Parameter
Differential input voltage
Total output jitter
AC common mode
Receiver eye opening
Differential return loss
Common mode return loss
DC differential output impedance
D+/D- impedance matching
Squelch detect threshold
AC coupled
Lane to lane skew at Rx
Min.
Nom
0.175
0.35
12
6
90
-5
75
75
100
Max
Units Notes
1.200
0.65
100
V
UI
mV
UI
dB
dB
Ohm
%
mV
nf
UI
110
+5
175
20
1
2
3
4
5
5
6
7
8
9
10
Peak-Peak differential voltage. VDIFFp-p = 2 × VRMAx. Measured at the package pins of the receiver.
See Figure 12.
Max Jitter tolerated by Rx. This is the nominal value tolerated at the package pin of the receiver
device. A receiver must therefore tolerate any additional jitter generated by the package to the die.
Peak common mode value. |VD+ + VD-|/2 - VCM-DC(avg)
See Figure 24, “Receiver Eye Opening (Differential)” on page 87.
50 MHz to 1.6 GHz. The driver output impedance shall result in a differential return loss greater than
or equal to 15 dB and a common mode return loss greater than or equal to 6 dB over a frequency
range of 50 MHz to 1.8 GHz. This output impedance requirement applies to all valid output levels. The
reference impedance for return loss measurements is 100 Ω for differential return loss and 25 Ω for
common mode (i.e. as measured by a Vector Network Analyzer with 100 Ω differential probes). Note
this is based on a nominal PCI Express* interconnect differential characteristic impedance of 100 Ω.
Applicable during active (L0) and Align states only.
DC Differential Mode Impedance 100 Ω ±10% tolerance.
DC impedance matching between two lanes of a port.
Peak-to-Peak value. Measured at the pin of the receiver. Differential signal below this level will
indicate a squelch condition.
All receivers shall be AC coupled to the media.
Lane skew at the Receiver that must be tolerated.
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Table 28.
PCI Express* Tx Output Specifications
Symbol
UI
VDIFFp-p
Trise, Tfall
VTX-CM-AC
VTX-CM-DC delta
RL-DiffTX
RL-CMTX
ZTX-OUT-DC
ZTX-Match-DC
LSKEW-TX
JTOTAL
TDeye
ITX-SHORT
VTX-IDLE
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
Parameter
Unit Interval
Differential output voltage
Driver Rise/Fall Time
AC Common Mode
Common Mode Active to Sleep mode delta
Differential Return Loss
Common Mode Return Loss
DC Differential Output Impedance
D+/D- impedance matching
Lane to Lane Skew at Tx
Total Output Jitter.
Minimum Transmitter eye opening.
Short circuit Current
Sleep mode Voltage Output
Min.
0.800
0.2
-50
15
6
90
-5
0.65
-100
0
Nom
400
100
0
Max
1.200
0.4
20
+50
110
+5
500
0.35
100
20
Units Notes
ps
V
UI
mV
mV
dB
dB
Ω
%
ps
UI
UI
mA
mV
1
2
3
4
5
5
6
7
8
9
10
11
12
±300 ppm. UI does not account for SSC dictated variations. No test load is necessarily associated
with this value. This UI spec is a “before transmission” specification and represents the nominal time
of each bit transmission or width.
Peak-Peak differential voltage. VDIFFp-p = 2 × VDMAx. Specified at the package pins into a 100 Ω test
load as shown in Figure 22, “Transmitter Test Load (100 W diff Load)” on page 86. Max level set by
maximum single ended voltage after a reflection from an open. This value is for the first bit after a
transition on the data lines. Subsequent bits of the same polarity shall have an amplitude of 6 dB
(±0.5 db) less as measured differentially peak to peak than the specified value.
20–80% at transmitter. Slower rise/fall times are better.
Peak common mode value. |VD+ + VD-|/2 - VCM-DC(avg)
50 MHz to 1.6 GHz. The driver output impedance shall result in a differential return loss greater than
or equal to 15 dB and a common mode return loss greater than or equal to 6 dB over a frequency
range of 50 MHz to 1.8 GHz. This output impedance requirement applies to all valid output levels. The
reference impedance for return loss measurements is 100 Ω for differential return loss and 25 Ω for
common mode (i.e. as measured by a Vector Network Analyzer with 100 Ω differential probes). Note
this is based on a nominal PCI Express* interconnect differential characteristic impedance of 100 Ω.
Applicable during active (L0) and Align states only.
DC Differential Mode Impedance 100 Ω ±10% tolerance. All devices shall employ on-chip adaptive
impedance matching circuits to ensure the best possible termination/Zout for its Transmitters (as well
as receivers).
DC impedance matching between two lanes of a port.
Between any two lanes within a single transmitter.
Clock source PPM mismatch is in addition to this value. Measured over 250 UI.
See Figure 23, “Transmitter Eye Diagram” on page 87.
Between any voltage from max supply to gnd with power on or off.
Squelch condition. Both signals brought to VCM-DC-|VD+ - VD-|
December 2007
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Intel® 81341 and 81342 I/O Processors
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Intel® 81341 and 81342—Electrical Specifications
4.3.7
PCI Express* Differential Receiver (Rx) Input Specifications
Table 29.
PCI Express* Rx Input Specifications
Symbol
VDIFFp-p
JTOTAL
VCM-AC
TReye
RL-DiffRX
RL-CMTX
ZRX-OUT-DC
ZRX-Match-DC
VRX-SQUELCH
CinRX
LSKEW-RX
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
Parameter
Differential input voltage
Total Output Jitter.
AC Common Mode
Receiver eye opening.
Differential Return Loss
Common Mode Return Loss
DC Differential Output Impedance
D+/D- impedance matching
Squelch detect threshold
AC coupled
Lane to Lane Skew at Rx
Min.
Nom
0.175
0.35
15
6
90
0-5
75
400
Max
1.200
0.65
100
100
110
+5
175
20
Units Notes
V
UI
mV
UI
dB
dB
Ω
%
mV
pf
UI
1
2
3
4
5
5
6
7
8
9
10
Peak-Peak differential voltage. VDIFFp-p = 2 * VRMAx. Measured at the package pins of the receiver.
See Figure 12.
Max Jitter tolerated by Rx. This is the nominal value tolerated at the package pin of the receiver
device. A receiver must therefore tolerate any additional jitter generated by the package to the die.
Peak common mode value. |VD+ + VD-|/2 - VCM-DC(avg)
See Figure 24, “Receiver Eye Opening (Differential)” on page 87.
50 MHz to 1.6 GHz. The driver output impedance shall result in a differential return loss greater than
or equal to 15 dB and a common mode return loss greater than or equal to 6 dB over a frequency
range of 50 MHz to 1.8 GHz. This output impedance requirement applies to all valid output levels. The
reference impedance for return loss measurements is 100 Ω for differential return loss and 25 Ω for
common mode (i.e. as measured by a Vector Network Analyzer with 100 Ω differential probes). Note
this is based on a nominal PCI Express* interconnect differential characteristic impedance of 100 Ω.
Applicable during active (L0) and Align states only.
DC Differential Mode Impedance 100 Ω ±10% tolerance.
DC impedance matching between two lanes of a port.
Peak to Peak value. Measured at the pin of the receiver. Differential signal below this level will indicate
a squelch condition.
All receivers shall be AC coupled to the media.
Lane skew at the Receiver that must be tolerated.
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Electrical Specifications—Intel® 81341 and 81342
4.3.8
Boundary Scan Test Signal Timings
Table 30.
Boundary Scan Test Signal Timings
Symbol
TJTF
TJTCH
TJTCL
TJTCR
TJTCF
TJTIS1
TJTIH1
TJTOV1
TOF1
Notes:
1.
2.
3.
4.
Parameter
Min.
Max Units
TCK Frequency
0
66
TCK High Time
7.0
TCK Low Time
7.0
TCK Rise Time
5
TCK Fall Time
5
Input Setup to TCK—TDI, TMS
3.0
Input Hold from TCK—TDI, TMS 2.0
TDO Output Valid Delay
4.25 13.25
TDO Float Delay
4.25 13.25
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Measured at 1.5 V (1)
Measured at 1.5 V (1)
0.8 V to 2.0 V (1)
2.0 V to 0.8 V (1)
(3)
(3)
Relative to falling edge of TCK (2)
Relative to falling edge of TCK (4)
Not tested.
See Figure 11, “Output Timing Measurement Waveforms” on page 82.
See Figure 12, “Input Timing Measurement Waveforms” on page 83.
A float condition occurs when the output current becomes less than ILO. Float delay is not tested. See
Figure 11, “Output Timing Measurement Waveforms” on page 82.
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Intel® 81341 and 81342—Electrical Specifications
4.4
AC Timing Waveforms
Figure 10. Clock Timing Measurement Waveforms
Vtch
Vih(min)
Vtest
Vil(max)
Vtcl
TCH
TCL
TC
Figure 11. Output Timing Measurement Waveforms
Vth
CLK
Vtest
Vtl
TOV1
Vtfall
OUTPUT
DELAY FALL
TOV1
OUTPUT
DELAY RISE
Vtrise
TOF
OUTPUT
FLOAT
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Electrical Specifications—Intel® 81341 and 81342
Figure 12. Input Timing Measurement Waveforms
Vth
CLK
Vtest
Vtl
TIH1
TIS1
Vth
INPUT
Vtest
Valid
Vtest
Vmax
Vtl
Figure 13. I2C Interface Signal Timings
SDA
TLOW
TBUF
TSR
THDSTA
TSF
TSP
SCL
THDSTA
Stop
December 2007
Order Number: 315039-003US
Start
THDDAT
THIGH
TSUSTO
TSUDAT
TSUSTA
Repeated
Start
Stop
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Intel® 81341 and 81342—Electrical Specifications
Figure 14. DDR2 SDRAM Write Timings
ADDR/CMD
CS #
T VB3
TVB 4/ 5
TVA3
T VA4 / 5
M_CK
DQ S
DQS#
T VB1
T VA 1
DQ
Figure 15. DQS Falling Edge Output Access Time to/from M_CK Rising Edge
M_CK
TVA2
DQS Max
DQS Min
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Electrical Specifications—Intel® 81341 and 81342
Figure 16. DDR2 SDRAM Read Timings
DQS
T VB6
T VA6
DQ
Table 31.
AC Measurement Conditions
Units Note
s
Symbol
PCI-X
PCI
DDR2
PBI
Vth
0.6VCC3P3
0.6VCC3P3
M_VREF+0.25
2.0
V
0.25VCC3P3
0.4VCC3P3
0.285VCC3P3
0.615VCC3P3
0.35VCC3P3
0.2VCC3P3
0.4VCC3P3
0.285VCC3P3
0.615VCC3P3
0.4VCC3P3
M_VREF-0.250
0.5VCC1P8
0.5VCC1P8
0.5VCC1P8
1.0
0.8
1.5
1.5
1.5
1.2
V
V
V
V
V
1.5
1.5
1.0
1.0
Vtl
Vtest
Vtrise
Vtfall
Vmax
Slew
Rate
Notes:
1.
0
V/nS 1
Input signal slew rate is measured between Vil and Vih
Figure 17. AC Test Load for all Signals Except PCI, PCI-Express and DDR2
Test
Point
Output
50 pF
Figure 18. AC Test Load for DDR2 SDRAM Signals
VTT
25 Ω
Output
December 2007
Order Number: 315039-003US
Test
Point
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Intel® 81341 and 81342—Electrical Specifications
Figure 19. PCI/PCI-X TOV(max) Rising Edge AC Test Load
Test
Point
Output
25 Ω
10 pF
Figure 20. PCI/PCI-X TOV(max) Falling Edge AC Test Load
VCC33
Test
Point
25 Ω
Output
10 pF
Figure 21. PCI/PCI-X TOV(min) AC Test Load
VCC33
Test
Point
1 KΩ
Output
1 KΩ
10 pF
Figure 22. Transmitter Test Load (100 Ω diff Load)
D+
D-
50 Ω
50 Ω
+
Vcm-dc
-
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Figure 23. Transmitter Eye Diagram
UI
VDmax
TDeye
VDmin
Note: Transmitter Vdiffp-p = 2 * VDmax
Figure 24. Receiver Eye Opening (Differential)
UI
VRmax
TReye
VRmin
Note: Transmitter Vdiffp-p = 2 * VRmax
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Intel® 81341 and 81342—Electrical Specifications
Figure 25. PBI Output Timings
PBI Output Timings - READ
A2D w/s
READ
A
A
Wn ...
D2D w/s
Wo D
D
Wm ...
Recovery w/s
Wo D
D
Rn
...
Ro
pbi_clk
Address
A
Address++
Tasc
Tah
Twce
CE#
Taso
Twoe
OE#
D
DATA(rd)
D
PBI Output Timings - WRITE
WRITE
A2D w/s
A
A
Wn ...
Recovery w/s
Wo D
D
Rn
...
Ro
pbi_clk
Address
A
Tahw
CE#
Tasw
Twwe
WE#
Tdsw
Tdhw
DATA(wr)
Notes:
(1) pbi_clk is provided as a virtual clock and is not available as an external signal.
(2) Timings are based on 66 MHz PBI_CLK.
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Electrical Specifications—Intel® 81341 and 81342
Figure 26. PBI External Device Timings (Flash)
PBI External Device Timings (Flash)
A2D w/s
READ
A
A
Wn ...
D2D w/s
Wo D
D
Wm ...
Recovery w/s
Wo D
D
Rn
...
Ro
pbi_clk
Address
A
Address++
Tad1
TadN
CE#
Tcd
Tdh
OE#
Tdh
Toe
D
DATA(rd)
D
Notes:
(1) pbi_clk is provided as a virtual clock and is not available as an external signal.
(2) Timings are based on 66 MHz PBI_CLK.
Figure 27. Intel® 81341 and 81342 I/O Processors 1.2V/1.8V Power Sequencing System
Requirements
•
•
•
Signal/Ball names concerned: vcc1p8s, vcc1p2as and vcc1p2ds
1.8V supply should never exceed the 1.2V supply (analog or digital)
when vcc1p2 < nominal
The 3.3V supplies and VccVio supplies don’t have any sequencing
requirements.
1.8
1.8V unsafe
1.8V safe
1.8V safe
1.8V unsafe
1.2
0
December 2007
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