TPS65735 PMU For Active Shutter 3D Glasses Data Manual PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Literature Number: SLVSAI6 June 2011 TPS65735 SLVSAI6 – JUNE 2011 www.ti.com Contents 1 2 3 2 .................................................................................................................. 5 1.1 Features ...................................................................................................................... 5 1.2 Description ................................................................................................................... 5 1.3 Pin Descriptions ............................................................................................................. 6 1.4 Package Pin Assignments ................................................................................................. 7 POWER MANAGEMENT CORE .............................................................................................. 8 2.1 Recommended Operating Conditions .................................................................................... 8 2.2 Absolute Maximum Ratings ................................................................................................ 8 2.3 Thermal Information ........................................................................................................ 9 2.4 Quiescent Current ........................................................................................................... 9 2.5 Electrical Characteristics ................................................................................................... 9 2.6 System Operation ......................................................................................................... 13 2.6.1 System Power Up .............................................................................................. 13 2.6.2 System Operation Using Push Button Switch .............................................................. 14 2.6.3 System Operation Using Slider Switch ...................................................................... 15 2.7 Linear Charger Operation ................................................................................................ 16 2.7.1 Battery and TS Detection ...................................................................................... 16 2.7.2 Battery Charging ................................................................................................ 16 2.7.2.1 Pre-charge .......................................................................................... 17 2.7.2.2 Charge Termination ................................................................................ 17 2.7.2.3 Recharge ............................................................................................ 17 2.7.2.4 Charge Timers ...................................................................................... 17 2.7.3 Charger Status (nCHG_STAT Pin) ........................................................................... 18 2.8 LDO Operation ............................................................................................................. 18 2.8.1 LDO Internal Current Limit .................................................................................... 18 2.9 Boost Converter Operation ............................................................................................... 19 2.9.1 Boost Thermal Shutdown ...................................................................................... 19 2.9.2 Boost Load Disconnect ........................................................................................ 20 2.10 Full H-Bridge Analog Switches .......................................................................................... 20 2.10.1 H-Bridge Switch Control ....................................................................................... 20 2.11 Power Management Core Control ....................................................................................... 22 2.11.1 SLEEP / Power Control Pin Function ........................................................................ 22 2.11.2 COMP Pin Functionality ....................................................................................... 22 2.11.3 SW_SEL Pin Functionality .................................................................................... 23 2.11.4 SWITCH Pin ..................................................................................................... 23 2.11.5 Slider Switch Behavior ......................................................................................... 23 2.11.6 Push-Button Switch Behavior ................................................................................. 24 APPLICATION INFORMATION ............................................................................................. 26 3.1 Applications Schematic ................................................................................................... 26 3.2 Reducing System Quiescent Current (IQ) .............................................................................. 26 3.3 Boost Converter Application Information ............................................................................... 27 3.3.1 Setting Boost Output Voltage ................................................................................. 27 3.3.2 Boost Inductor Selection ....................................................................................... 28 3.3.3 Boost Capacitor Selection ..................................................................................... 28 3.4 Bypassing Default Push-Button SWITCH Functionality .............................................................. 28 INTRODUCTION Contents Copyright © 2011, Texas Instruments Incorporated TPS65735 SLVSAI6 – JUNE 2011 www.ti.com List of Figures 1-1 TPS65735 Functional Block Diagram ........................................................................................... 5 1-2 TPS65735 Package Pin Assignments .......................................................................................... 7 2-1 System Power Up State Diagram .............................................................................................. 14 2-2 Push Button State Diagram ..................................................................................................... 15 2-3 System Operation Using Slider Switch ........................................................................................ 15 2-4 Thermistor Detection and Circuit 2-5 Battery Charge Phases .......................................................................................................... 17 2-10 Boost Load Disconnect .......................................................................................................... 20 2-11 H-Bridge States ................................................................................................................... 21 2-12 ............................................................................................ ................................................................................... COMP Pin Internal Connection ................................................................................................. SWITCH, Slider Power On-Off Behavior ...................................................................................... SWITCH, Push-button Power On Behavior ................................................................................... SWITCH, Push-button Power Off Behavior ................................................................................... TPS65735 Applications Schematic ............................................................................................ Reducing System IQ with Addition of a FET .................................................................................. Boost Feedback Network Schematic .......................................................................................... Bypassing Default TPS65735 Push Button SWITCH Timing............................................................... SWITCH Press and SLEEP Signal to Control System Power Off ......................................................... 2-13 2-14 2-15 2-16 2-17 3-1 3-2 3-3 3-4 3-5 .............................................................................................. H-Bridge States from Oscilloscope SLEEP Signal to Force System Power Off Copyright © 2011, Texas Instruments Incorporated List of Figures 16 22 22 22 24 25 25 26 27 27 29 29 3 TPS65735 SLVSAI6 – JUNE 2011 www.ti.com List of Tables ................................................................................................................... 1-1 Pin Descriptions 1-2 Pin Absolute Maximum Ratings .................................................................................................. 7 2-1 nCHG_STAT Functionality ...................................................................................................... 18 2-2 VLDO_SET Functionality ........................................................................................................ 18 2-3 H-Bridge States from Inputs 21 2-4 Scaling Resistors for COMP Pin Function (VVLDO = 2.2 V) 23 2-5 2-6 3-1 4 .................................................................................................... ................................................................. Scaling Resistors for COMP Pin Function (VVLDO = 3.0 V) ................................................................. SW_SEL Settings ................................................................................................................ Recommended RFB1 and RFB2 Values (for IQ(FB) = 5 µA) .................................................................... List of Tables 6 23 23 28 Copyright © 2011, Texas Instruments Incorporated TPS65735 SLVSAI6 – JUNE 2011 www.ti.com PMU For Active Shutter 3D Glasses Check for Samples: TPS65735 1 INTRODUCTION 1.1 Features • Linear Charger – Three Charger Phases: Pre-charge, Fast Charge, and Charge Termination – Externally Set Charge Current, Supports up to 100 mA – LED Current Sinks for Power Good and Charger Status Indication • LDO Supply for External Modules (Microcontroller, RF Module, IR Module) – LDO Continuous Output Current up to 30 mA 1 1.2 • Boost Converter – Adjustable Output Voltage: 8 V to 16 V – Boost Output Internally Connected to H-Bridge Analog Switches • Full H-Bridge Analog Switches – Controlled by an External Microcontroller for System Operation • Output Pin for Divided Down Battery Voltage Useful for ADC or Comparator Input of an MCU Description The TPS65735 is a PMU for active shutter 3D glasses consisting of an integrated power path, linear charger, LDO, boost converter, and full H-bridge analog switches for left and right shutter operation in a pair of active shutter 3D glasses. In addition to the power devices, a typical 3D glasses system contains both a microcontroller and a communications front end (IR, RF, or other) in order to handle the communication and synchronous operation along with a 3D television. Figure 1-1. TPS65735 Functional Block Diagram 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011, Texas Instruments Incorporated TPS65735 SLVSAI6 – JUNE 2011 1.3 www.ti.com Pin Descriptions Table 1-1. Pin Descriptions PIN NAME I/O PIN NO. DESCRIPTION POWER MANAGEMENT CORE (PMIC) VIN I 20 AC or USB Adapter Input ISET I/O 15 Fast-Charge Current Setting Resistor TS I 16 Pin for 10 kΩ NTC Thermistor Connection FLOAT IF THERMISTOR / TS FUNCTION IS NOT USED nCHG_STAT O 29 Open-drain Output, Charge Status Indication CONNECT TO GROUND IF FUNCTION IS NOT USED BAT I/O 18 Charger Power Stage Output and Battery Voltage Sense Input SYS O 19 Output Terminal to System VLDO O 21 LDO Output VLDO_SET I 22 Sets LDO Output Voltage (see Table 2-2) SWITCH I 25 Switch Input for Device Power On/Off SW_SEL I 26 Selects Type of Switch Connected to SWITCH Pin (see Table 2-6) BST_SW O 11 Boost Switch Node BST_FB I 13 Boost Feedback Node BST_OUT O 10 Boost Output HBR1 I 8 H-Bridge Input 1 for Right LC Shutter HBR2 I 9 H-Bridge Input 2 for Right LC Shutter HBL1 I 32 H-Bridge Input 1 for Left LC Shutter HBL2 I 7 H-Bridge Input 2 for Left LC Shutter LCRN O 6 H-Bridge Output for Right LC Shutter, "Negative" Terminal LCRP O 5 H-Bridge Output for Right LC Shutter, "Positive" Terminal LCLN O 4 H-Bridge Output for Left LC Shutter, "Negative" Terminal LCLP O 3 H-Bridge Output for Left LC Shutter, "Positive" Terminal COMP O 23 Scaled Battery Voltage for MCU Comparator or ADC Input (Battery Voltage Monitoring) DO NOT CONNECT IF COMP FUNCTION IS NOT USED SLEEP I/O 31 Sleep Enable Input from an MCU (edge triggered, only for system shutdown) BST_EN I 1 Boost Enable Input from an MCU, High = Boost Enabled CHG_EN I 30 Charger Enable Input from an MCU, High = Boost Enabled PSCL I/O 28 I2C Clock Pin (only used for TI debug and test) GROUND PIN IN APPLICATION PSDA I/O 27 I2C Data Pin (only used for TI debug and test) GROUND PIN IN APPLICATION PGNDBST - 12 Boost Power Ground AGND - 24 Analog Ground DGND - 2 Digital Ground Thermal PAD - 33 There is an internal electrical connection between the exposed thermal pad and the AGND ground pin of the device. The thermal pad must be connected to the same potential as the AGND pin on the printed circuit board. Do not use the thermal pad as the primary ground input for the device. AGND pin must be connected to ground at all times. N/C - 14, 17 MISC. AND PACKAGE 6 All N/C should be connected to the main system ground. INTRODUCTION Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65735 TPS65735 SLVSAI6 – JUNE 2011 www.ti.com Table 1-2. Pin Absolute Maximum Ratings PIN VALUE / UNIT Input voltage range on all pins (except for VIN, BST_OUT, BST_SW, BST_FB, VLDO, LCLP, LCLN, LCRP, LCRN, AGND, DGND, and PGNDBST) with respect to AGND -0.3 V to 7.0 V VIN with respect to AGND -0.3 V to 28.0 V BST_OUT, BST_SW, LCLP, LCLN, LCRP, and LCRN with respect to PGNDBST -0.3 V to 18.0 V BST_FB with respect to PGNDBST, VLDO with respect to DGND -0.3 V to 3.6 V 1.4 Package Pin Assignments Figure 1-2. TPS65735 Package Pin Assignments INTRODUCTION Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65735 7 TPS65735 SLVSAI6 – JUNE 2011 www.ti.com 2 POWER MANAGEMENT CORE 2.1 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) SUBSYSTEM AND PARAMETER MIN NOM MAX UNIT CHARGER / POWER PATH VVIN Voltage range at charger input pin IVIN Input current at VIN pin 3.7 28 V 200 mA CVIN Capacitor on VIN pin LVIN Inductance at VIN pin VSYS Voltage range at SYS pin ISYS(OUT) Output current at SYS pin CSYS Capacitor on SYS pin 0.1 VBAT Voltage range at BAT pin 2.5 6.4 V CBAT Capacitor on BAT pin 4.7 10 µF REXT(nCHG_STAT) Resistor connected to nCHG_STAT pin to limit current into pin 320 0.1 10 µF 0 2 µH 2.5 6.4 V 100 mA 10 µF Ω BOOST CONVERTER / H-BRIDGE SWITCHES VIN(BST_SW) Input voltage range for boost converter VBST_OUT Output voltage range for boost converter 2.5 6.5 8 16 CBST_OUT LBST_SW (1) V V Boost output capacitor 3.3 10 µF Inductor connected between SYS and BST_SW pins Device optimized for operation with 10 µH inductor 4.7 10 µH 1 10 µF 0.4 V LDO CVLDO External decoupling cap on pin VLDO POWER MANAGEMENT CORE CONTROL (LOGIC LEVELS FOR GPIOs) VIL(PMIC) GPIO low level (BST_EN, CHG_EN, SW_SEL, VLDO_SET and to switch H-Bridge inputs to a low, 0, level) VIH(PMIC) GPIO high level (BST_EN, CHG_EN, SW_SEL, VLDO_SET and to switch H-Bridge inputs to a high, 1, level) (1) 2.2 1.2 V See Section 2.9 for information on boost converter inductor selection. Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) PARAMETER MINIMUM MAXIMUM UNITS Operating free-air temperature, TA 0 60 °C Max Junction Temperature, TJ, Electrical Characteristics Guaranteed 0 85 °C Max Junction temperature, TJ, Functionality Guaranteed (1) 0 105 °C (1) 8 Device has a thermal shutdown feature implemented that shuts down at 105 °C POWER MANAGEMENT CORE Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65735 TPS65735 SLVSAI6 – JUNE 2011 www.ti.com 2.3 Thermal Information TPS65735 THERMAL METRIC RSN UNITS 32 PINS θJA Junction-to-ambient thermal resistance (1) 38.9 θJCtop Junction-to-case (top) thermal resistance (2) 26.5 (3) θJB Junction-to-board thermal resistance ψJT Junction-to-top characterization parameter (4) ψJB Junction-to-board characterization parameter (5) 9.8 (6) 3.5 θJCbot (1) (2) (3) (4) (5) (6) 9.8 Junction-to-case (bottom) thermal resistance °C/W 0.3 The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. 2.4 Quiescent Current over operating free-air temperature range (unless otherwise noted) TYP MAX UNIT IQ(SLEEP) Power management core quiescent current in sleep mode PARAMETER @ 25° C VBAT = 3.6 V VVIN = 0 V No load on LDO CHG_EN, BST_EN grounded BST_FB = 300 mV Power management core in sleep mode / device 'off' 8.6 10.5 µA IQ(ACTIVE) Power management core quiescent current in active mode @ 25° C VBAT = 3.6 V VVIN = 0 V Boost enabled but not switching, H-bridge in grounded state No load on LDO Power management core in active mode 39 53.5 µA MIN TYP MAX UNIT 3.3 3.45 V 2.5 TEST CONDITIONS MIN Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS BATTERY CHARGER POWER PATH VUVLO(VIN) Undervoltage lockout at power path input, VIN pin VVIN: 0 V → 4 V 3.2 VHYS- Hysteresis on UVLO at power path input, VIN pin VVIN: 4 V → 0 V 200 300 mV UVLO(VIN) VIN-DT Input power detection threshold Input power detected if: (VVIN > VBAT + VIN-DT); VBAT = 3.6 V VVIN: 3.5 V → 4 V 40 140 mV VHYS-INDT Hysteresis on VIN-DT VBAT = 3.6 V VVIN: 4 V → 3.5 V 20 POWER MANAGEMENT CORE Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65735 mV 9 TPS65735 SLVSAI6 – JUNE 2011 www.ti.com Electrical Characteristics (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 6.4 6.6 6.8 UNIT VOVP Input over-voltage protection threshold VVIN: 5 V → 7 V VHYS-OVP Hysteresis on OVP VVIN: 11 V → 5 V VDO(VIN- VIN pin to SYS pin dropout voltage VVIN – VSYS ISYS = 150 mA (including IBAT) VVIN = 4.35 V VBAT = 3.6 V 350 mV BAT pin to SYS pin dropout voltage VBAT – VSYS ISYS = 100 mA VVIN = 0 V VBAT > 3 V 150 mV IVIN(MAX) Maximum power path input current at pin VIN VVIN = 5 V VSUP(ENT) Enter battery supplement mode VSYS ≤ (VBAT - 40 mV) V VSUP(EXIT) Exit battery supplement mode VSYS ≥ (VBAT - 20 mV) V VSUP(SC) Output short-circuit limit in supplement mode 250 mV VO(SC) Output short-circuit detection threshold, power-on 0.9 V SYS) VDO(BATSYS) 105 V mV 200 mA BATTERY CHARGER ICC Active supply current into VIN pin IBAT(SC) Source current for BAT pin short-circuit detection VBAT(SC) BAT pin short-circuit detection threshold 1.6 1.8 2.0 V VBAT(REG) Battery charger output voltage –1% 4.20 1% V VLOWV Pre-charge to fast-charge transition threshold 2.9 3.0 3.1 V ICHG Charger fast charge current range ICHG = KISET / RISET 100 mA KISET Battery fast charge current set factor VVIN = 5 V ICHG = KISET / RISET IVIN(MAX) > ICHG ICHG = 100 mA No load on SYS pin, thermal loop not active. –20% 450 20% AΩ IPRECHG Pre-charge current 0.07 × ICHG 0.10 × ICHG 0.15 × ICHG mA ITERM Charge current value for termination detection threshold ICHG = 100 mA 7 10 15 mA VRCH Recharge detection threshold VBAT below nominal charger voltage, VBAT(REG) 55 100 170 mV IBAT(DET) Sink current for battery detection tCHG Charge safety timer (18000 seconds = 5 hours) tPRECHG Pre-charge timer (1800 seconds = 30 minutes) VDPPM DPPM threshold ILEAK(nCHG) Leakage current for nCHG_STAT pin RDSON(nCH G) 10 VVIN = 5 V No load on SYS pin VBAT > VBAT(REG) 2 1 VVIN = 5 V VBAT(REG) > VBAT > VLOWV 5 mA 1 s 1800 s VBAT + 100 mV V 20 POWER MANAGEMENT CORE mA 18000 VnCHG_STAT = 4.2 V CHG_EN = LOW (Charger disabled) On resistance for nCHG_STAT MOSFET switch mA 100 nA 60 Ω Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65735 TPS65735 SLVSAI6 – JUNE 2011 www.ti.com Electrical Characteristics (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER IMAX(nCHG) TEST CONDITIONS MIN TYP Maximum input current to nCHG_STAT pin MAX UNIT 50 mA BATTERY CHARGER NTC MONITOR 75 µA 2100 mV 300 mV 300 mV 30 mV Charger lower thermal regulation limit 75 °C TJ(REG_UPP Charger upper thermal regulation limit ER) 95 °C Charger thermal shutdown temperature 105 °C TJ(OFF-HYS) Charger thermal shutdown hysteresis 20 °C ITSBIAS TS pin bias current VCOLD 0°C charge threshold for 10kΩ NTC (β = 3490) VHYS(COLD) Low temperature threshold hysteresis VHOT 50°C charge threshold for 10kΩ NTC (β = 3490) VHYS(HOT) High temperature threshold hysteresis Battery charging and battery / NTC temperature increasing Battery charging and battery / NTC temperature decreasing BATTERY CHARGER THERMAL REGULATION TJ(REG_LO WER) TJ(OFF) LDO IMAX(LDO) Maximum LDO output current, VVLDO = 2.2 V VSYS = 4.2 V VVIN = 0 V VLDO_SET = 0 V 30 Maximum LDO output current, VVLDO = 3.0 V VSYS = 4.2 V VVIN = 0 V VLDO_SET = VSYS 30 mA mA ISC(LDO) Short circuit current limit 100 mA VVLDO LDO output voltage VLDO_SET = LOW (VLDO_SET pin connected to DGND) 3.7 V ≤ VVIN ≤ 6.5 V ILOAD(LDO) = -10 mA 2.13 2.2 2.27 V VVLDO LDO output voltage VLDO_SET = HIGH (VVLDO_SET = VSYS) 3.7 V ≤ VVIN ≤ 6.5 V ILOAD(LDO) = -10 mA 2.91 3.0 3.09 V VDO(LDO) LDO Dropout voltage VVIN - VLDO when in dropout ILOAD(LDO) = -10 mA 200 mV Line regulation 3.7 V ≤ VVIN ≤ 6.5 V ILOAD(LDO) = -10 mA -1 1 % Load regulation VVIN = 3.5 V 0.1 mA ≤ ILOAD(LDO) ≤ -10 mA -2 2 % Power supply rejection ratio @20 KHz, ILOAD(LDO) = 10 mA VDO(LDO) = 0.5 V CVLDO = 10 µF PSRR 30 45 dB BOOST CONVERTER IQ(BST) Boost operating quiescent current Boost Enabled, BST_EN = High IOUT(BST) = 0 mA (boost is not switching) VBAT = 3.6 V RDSON(BST) Boost MOSFET switch on-resistance VIN(BST) = 2.5 V ISW(MAIN) = 200 mA 2 4.5 µA 0.8 1.2 Ω POWER MANAGEMENT CORE Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65735 11 TPS65735 SLVSAI6 – JUNE 2011 www.ti.com Electrical Characteristics (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER ILKG(BST_S W) Leakage into BST_SW pin (includes leakage into analog h-bridge switches) ISWLIM(BST) Boost MOSFET switch current limit VDIODE(BST Voltage across integrated boost diode during normal operation ) VREF(BST) TEST CONDITIONS MIN TYP BST_EN signal = LOW (Boost disabled) VBST_SW = 4.2 V No load on BST_OUT pin 100 150 BST_EN signal = HIGH VBST_SW = 16.0 V IBST_OUT = - 2 mA UNIT 90 nA 200 mA 1.0 V 1.17 1.2 1.23 V VREFHYS(BS Boost reference voltage hysteresis on BST_FB pin T) 2 2.5 3.2 % TON(BST) Maximum on time detection threshold 5 6.5 8 µs TOFF(BST) Minimum off time detection threshold 1.4 1.75 2.1 TSHUT(BST) Boost thermal shutdown threshold 105 °C TSHUT- Boost thermal shutdown threshold hysteresis 20 °C HYS(BST) Boost reference voltage on BST_FB pin MAX µs FULL H-BRIDGE ANALOG SWITCHES IQ(HSW) Operating quiescent current for h-bridge switches RDSON(HSW H-bridge switches on resistance 20 5 µA 40 Ω ) TDELAY(HS W-H) TDELAY(HS W-L) H-bridge switch propagation delay, input switched from low to high state. VHBxy = 0 V → VVLDO 100 ns H-bridge switch propagation delay, input switched from high to low state. VHBxy = VVLDO → 0 V 100 ns POWER MANAGEMENT CORE CONTROLLER VIL(PMIC) Low logic level for logic signals on IO logic level decreasing: power management core VSYS → 0 V (BST_EN, CHG_EN, SLEEP, HBR1, IIN = 1 mA HBR2, HBL1, HBL2) VIH(PMIC) High logic level for signals on power IO logic level increasing: management core 0 V → VSYS (BST_EN, CHG_EN, SLEEP, HBR1, IIN = 1 mA HBR2, HBL1, HBL2) VGOOD(LDO Power fault detection threshold 0.4 1.2 V V VVLDO decreasing 1.96 V ) VGOOD_HYS Power fault detection hysteresis VVLDO increasing 50 mV (LDO) VBATCOMP COMP pin voltage (scaled down battery voltage) VBAT = 4.2 V VVLDO = 2.2 V 1.85 VBAT = 2.5 V VVLDO = 2.2 V 1.10 VBAT = 4.2 V VVLDO = 3.0 V VBAT = 3.3 V VVLDO = 3.0 V 12 POWER MANAGEMENT CORE 1.90 1.50 V V V V Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65735 TPS65735 SLVSAI6 – JUNE 2011 www.ti.com 2.6 System Operation The system must complete the power up routine before it enters normal operating mode. The specific system operation depends on the setting defined by the state of the SW_SEL pin. The details of the system operation for each configuration of the SW_SEL pin are contained in this section. 2.6.1 System Power Up Figure 2-1. System Power Up State Diagram POWER MANAGEMENT CORE Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65735 13 TPS65735 SLVSAI6 – JUNE 2011 2.6.2 www.ti.com System Operation Using Push Button Switch Figure 2-2. Push Button State Diagram 14 POWER MANAGEMENT CORE Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65735 TPS65735 SLVSAI6 – JUNE 2011 www.ti.com 2.6.3 System Operation Using Slider Switch Figure 2-3. System Operation Using Slider Switch POWER MANAGEMENT CORE Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65735 15 TPS65735 SLVSAI6 – JUNE 2011 2.7 www.ti.com Linear Charger Operation This device has an integrated Li-Ion battery charger and system power path management feature targeted at space-limited portable applications. The architecture powers the system while simultaneously and independently charging the battery. This feature reduces the number of charge and discharge cycles on the battery, allows for proper charge termination, and enables the system to run with a defective or absent battery pack. It also allows instant system turn-on even with a totally discharged battery. The input power source for charging the battery and running the system can be an AC adapter or USB port connected to the VIN pin as long as the input meets the device operating conditions outlined in this datasheet. The power-path management feature automatically reduces the charging current if the system load increases. Note that the charger input, VIN, has voltage protection up to 28 V. 2.7.1 Battery and TS Detection To detect and determine between a good or damaged battery, the device checks for a short circuit on the BAT pin by sourcing IBAT(SC) to the battery and monitoring the voltage on the BAT pin. While sourcing this current if the BAT pin voltage exceeds VBAT(SC), a battery has been detected. If the voltage stays below the VBAT(SC) level, the battery is presumed to be damaged and not safe to charge. The device will also check for the presence of a 10 kΩ NTC thermistor attached to the TS pin of the device. The check for the NTC thermistor on the TS pin is done much like the battery detection feature described previously. The voltage on the TS pin is compared against a defined level and if it is found to be above the threshold, the NTC thermistor is assumed to be disconnected or not used in the system. To reduce the system quiescent current, the NTC thermistor temperature sensing function is only enabled when the device is charging and when the thermistor has been detected. Figure 2-4. Thermistor Detection and Circuit 2.7.2 Battery Charging The battery is charged in three phases: conditioning pre-charge, constant-current fast charge (current regulation), and a constant-voltage tapering (voltage regulation). In all charge phases, an internal control loop monitors the IC junction temperature and reduces the charge current if an internal temperature threshold is exceeded. Figure 2-5 shows what happens in each of the three charge phases: 16 POWER MANAGEMENT CORE Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65735 TPS65735 SLVSAI6 – JUNE 2011 www.ti.com Figure 2-5. Battery Charge Phases In the pre-charge phase, the battery is charged with the pre-charge current that is scaled to be 10% of the fast-charge current set by the resistor connected to the ISET pin. Once the battery voltage crosses the VLOWV threshold, the battery is charged with the fast-charge current (ICHG). As the battery voltage reaches VBAT(REG), the battery is held at a constant voltage of VBAT(REG) and the charge current tapers off as the battery approaches full charge. When the battery current reaches ITERM, the charger indicates charging is done by making the nCHG_STAT pin high impedance. Note that termination detection is disabled whenever the charge rate is reduced from the set point because of the actions of the thermal loop, the DPM loop, or the VIN(LOWV) loop. 2.7.2.1 Pre-charge The value for the pre-charge current is set to be 10% of the charge current that is set by the external resistor, RISET. Pre-charge current is scaled to lower currents when the charger is in thermal regulation. 2.7.2.2 Charge Termination In the fast charge state, once VBAT ≥ VBAT(REG), the charger enters constant voltage mode. In constant voltage mode, the charge current will taper until termination when the charge current falls below the I(TERM) threshold (typically 10% of the programmed fast charge current). Termination current is not scaled when the charger is in thermal regulation. When the charging is terminated, the nCHG_STAT pin will be high impedance (effectively turning off any LED that is connected to this pin). 2.7.2.3 Recharge Once a charge cycle is complete and termination is reached, the battery voltage is monitored. If VBAT < VBAT(REG) - VRCH, the device determines if the battery has been removed. If the battery is still present, then the recharge cycle begins and will end when VBAT ≥ VBAT(REG). 2.7.2.4 Charge Timers The charger in this device has internal safety timers for the pre-charge and fast charge phases to prevent potential damage to either the battery or the system. The default values for these timers are found as follows: Pre-charge timer = 0.5 hours (30 minutes) and Fast charge timer = 5 hours (300 minutes). POWER MANAGEMENT CORE Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65735 17 TPS65735 SLVSAI6 – JUNE 2011 www.ti.com During the fast charge phase, the following events may increase the timer durations: 1. The system load current activates the DPM loop which reduces the available charging current 2. The input current is reduced because the input voltage has fallen to VIN(LOW) 3. The device has entered thermal regulation because the IC junction temperature has exceeded TJ(REG) During each of these events, the internal timers are slowed down proportionately to the reduction in charging current. If the pre-charge timer expires before the battery voltage reaches VLOWV, the charger indicates a fault condition. 2.7.3 Charger Status (nCHG_STAT Pin) The nCHG_STAT pin is used to indicate the charger status by an externally connected resistor and LED circuit. The pin is an open drain input and the internal switch is controlled by the logic inside of the charger. This pin may also be connected to a GPIO of the system MCU to indicate charging status. The table below details the status of the nCHG_STAT pin for various operating states of the charger. Table 2-1. nCHG_STAT Functionality Charging Status 2.8 nCHG_STAT FET / LED Pre-charge / Fast Charge / Charge Termination ON Recharge OFF OVP OFF SLEEP OFF LDO Operation The power management core has a low dropout linear regulator (LDO) with variable output voltage capability. This LDO is used for supplying the microcontroller and may be used to supply either an external IR or RF module, depending on system requirements. The LDO can supply a continuous current of up to 30 mA. The output voltage (VVLDO) of the LDO is set by the state of the VLDO_SET pin. See Table 2-2 for details on setting the LDO output voltage. Table 2-2. VLDO_SET Functionality 2.8.1 VLDO_SET State VLDO Output Voltage (VVLDO) Low (VLDO_SET < VIL(PMIC)) 2.2 V High (VLDO_SET > VIH(PMIC)) 3.0 V LDO Internal Current Limit The internal current limit feature helps to protect the LDO regulator during fault conditions. During current limit, the output sources a fixed amount of current that is defined in the electrical specification table. The voltage on the output in this stage can not be regulated and will be VOUT = ILIMIT × RLOAD. The pass transistor integrated into the LDO will dissipate power, (VIN - VOUT) × ILIMIT, until the device enters thermal shutdown. In thermal shutdown the device will enter the "SLEEP / POWER OFF" state which means that the LDO will then be disabled and shut off. 18 POWER MANAGEMENT CORE Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65735 TPS65735 SLVSAI6 – JUNE 2011 www.ti.com 2.9 Boost Converter Operation The boost converter in this device is designed for the load of active shutter 3D glasses. This load is typically a light load where the average current is 2 mA or lower and the peak current out of a battery is limited in operation. This asynchronous boost converter operates with a minimum off time / maximum on time for the integrated low side switch, these values are specified in the electrical characteristics table of this datasheet. The peak output voltage from the boost converter is adjustable and set by using an external resistor divider connected between BST_OUT, the BST_FB pin, and ground. The peak output voltage is set by choosing resistors for the feedback network such that the voltage on the BST_FB pin is VREF(BST) = 1.2 V. See Section 3.3 for more information on calculating resistance values for this feedback network. 100 100 90 90 80 80 70 70 Efficiency (%) Efficiency (%) The efficiency curves for various input voltages over the typical 3D glasses load range (2 mA and lower) are shown below. All curves are for a target VOUT of 16 V. For output voltages less than 16 V, a higher efficiency at each operating input voltage should be expected. Note that efficiency is dependent upon the external boost feedback network resistances, the inductor used, and the type of load connected. 60 50 40 40 30 20 20 VIN = 3.0 V 0 0.01 10 VOUT = 16.0 V 0.1 Output Current (mA) 1 VIN = 3.7 V 0 0.01 2 G000 Figure 2-6. Boost Efficiency vs. IOUT, VIN = 3.0 V, VOUT = 16 V 100 90 80 80 70 70 50 40 20 0.1 Output Current (mA) 1 10 2 VIN = 5.5 V 0 0.01 G000 Figure 2-8. Boost Efficiency vs. IOUT, VIN = 4.2 V, VOUT = 16 V G000 40 30 VOUT = 16.0 V 2 50 20 VIN = 4.2 V 0 0.01 1 60 30 10 0.1 Output Current (mA) 100 90 60 VOUT = 16.0 V Figure 2-7. Boost Efficiency vs. IOUT, VIN = 3.7 V, VOUT = 16 V Efficiency (%) Efficiency (%) 50 30 10 2.9.1 60 VOUT = 16.0 V 0.1 Output Current (mA) 1 2 G000 Figure 2-9. Boost Efficiency vs. IOUT, VIN = 5.5 V, VOUT = 16 V Boost Thermal Shutdown An internal thermal shutdown mode is implemented in the boost converter that shuts down the device if the typical junction temperature of 105°C is exceeded. If the device is in thermal shutdown mode, the main switch of the boost is open and the device enters the "SLEEP / POWER OFF" state. POWER MANAGEMENT CORE Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65735 19 TPS65735 SLVSAI6 – JUNE 2011 2.9.2 www.ti.com Boost Load Disconnect When the boost is disabled (BST_EN = LOW), the H-bridge is automatically placed into the OFF state. In the OFF state the high side H-bridge switches are open and the low side switches of the H-bridge are closed. The OFF state grounds and discharges the load, potentially prolonging the life of the LC shutters by eliminating any DC content (see Section 2.10.1 for more information regarding the H-bridge states). The disconnection of the load is done with the H-Bridge and can be seen in the next figure (Figure 2-10). Figure 2-10. Boost Load Disconnect An advantage to this topology for disconnecting the load is that the boost output capacitor is charged to approximately the SYS voltage level, specifically VSYS - VDIODE(BST), when the boost is disabled. This design ensures that there is not a large in-rush current into the boost output capacitor when the boost is enabled. The boost operation efficiency is also increased because there is no load disconnect switch in the boost output path, such a switch would decrease efficiency because of the resistance that it would introduce. 2.10 Full H-Bridge Analog Switches The TPS65735 has two integrated full H-bridge analog switches that can be connected to GPIOs of a host microcontroller. There is an internal level shifter that takes care of the input signals to the H-Bridge switches. 2.10.1 H-Bridge Switch Control The H-Bridge switches are controlled by an external microcontroller for system operation - specifically to control charge polarity on the LCD shutters. Depending on the state of the signals from the microcontroller, the H-Bridge will be put into 4 different states. These states are: • OPEN: All Switches Opened • CHARGE+: Boost Output Voltage Present on Pins LCLP or LCRP • CHARGE-: Boost Output Voltage Present on Pins LCLN or LCRN • GROUNDED: High side switches are opened and low side switches are closed 20 POWER MANAGEMENT CORE Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65735 TPS65735 SLVSAI6 – JUNE 2011 www.ti.com If CHARGE+ state is followed by the CHARGE- state, the voltage across the capacitor connected to the H-Bridge output terminals will be reversed. The system is automatically put into the GROUNDED state when the boost is disabled by the BST_EN pin - for more details see Section 2.6. Table 2-3. H-Bridge States from Inputs HBx2 [HBL2 & HBR2] HBx1 [HBL1 & HBR1] 0 0 OPEN 0 1 CHARGE + 1 0 CHARGE - 1 1 GROUNDED H-Bridge State Figure 2-11. H-Bridge States Figure 2-12. H-Bridge States from Oscilloscope POWER MANAGEMENT CORE Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65735 21 TPS65735 SLVSAI6 – JUNE 2011 www.ti.com 2.11 Power Management Core Control Various functions of the power management core can be controlled by GPIOs of an external MCU or by setting the default state by connecting these function pins to a logic high or low level on the PCB. 2.11.1 SLEEP / Power Control Pin Function The internal SLEEP signal between the power management device and the MSP430 can be used to control the power down behavior of the device. This has multiple practical applications such as a watchdog implementation for the communication between the sender (TV) and the 3D glasses (receiver) or different required system on and off times; typically when the push-button press timing for an off event is a few seconds in length, programmable by software in the system MCU. If there is a requirement that the push-button press for system on and off events are different, the SLEEP signal must be set to a logic high value (VSLEEP > VIH(PMIC)) upon system startup. This implementation allows the device to power down the system on the falling edge of the SLEEP signal (when: VSLEEP < VIL(PMIC)). Figure 2-13. SLEEP Signal to Force System Power Off 2.11.2 COMP Pin Functionality The COMP pin is used to output a scaled down voltage level related to the battery voltage for input to a comparator of a microcontroller. Applications for this COMP feature could be to generate an interrupt on the microcontroller when battery voltage drops under a threshold and the device can then be shut down or indicate to the end user with an LED that the battery requires charging. Figure 2-14. COMP Pin Internal Connection 22 POWER MANAGEMENT CORE Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65735 TPS65735 SLVSAI6 – JUNE 2011 www.ti.com Table 2-4. Scaling Resistors for COMP Pin Function (VVLDO = 2.2 V) Scaling Resistors for COMP Pin Function Value RBSCL1 3.0 MΩ RBSCL2 2.36 MΩ Table 2-5. Scaling Resistors for COMP Pin Function (VVLDO = 3.0 V) Scaling Resistors for COMP Pin Function Value RBSCL1 3.0 MΩ RBSCL2 2.48 MΩ Using the designed values in Table 2-4 or Table 2-5, the voltage on the COMP pin will be: VCOMP = 0.5 × VVLDO + 300 mV. This assures that the COMP pin voltage will be close to half of the LDO output voltage plus the LDO dropout voltage of the device. The COMP pin can also be used as the input to an ADC channel of an external microcontroller if greater accuracy or more functionality is desired than a simple comparison. 2.11.3 SW_SEL Pin Functionality The SW_SEL pin is used to select what type of switch is connected to the SWITCH pin of the device. Selection between a push-button and a slider switch can be made based on the state of this pin. Table 2-6. SW_SEL Settings SW_SEL State Type of Switch Selected Low (VSW_SEL < VIL(PMIC)) Slider Switch High (VSW_SEL > VIH(PMIC)) Push-button When the push button switch type is selected, the device will debounce the SWITCH input with a 32 ms timer for both the ON and OFF events and either power on or off the device. Using the push-button switch function, the on and off timings are equal; tON = tOFF. If the system requirements are such that the on and off timings should be different, tON ≠ tOFF, then refer to the following section for the correct system setup: Section 3.4. When the slider switch operation is selected, the SWITCH pin must be externally pulled up to the SYS voltage with a resistor and the output connected to the slider switch. When the SWITCH pin is pulled to ground, the device will turn on and enter the power up sequence. 2.11.4 SWITCH Pin The SWITCH pin behavior is defined by the SW_SEL pin (Section 2.11.3) which defines the type of switch that is connected to the system; either a slider switch or push-button. 2.11.5 Slider Switch Behavior If a slider switch is connected in the system then the system power state and VLDO output (which can power an external MCU) is defined by the state of the slider switch. If the slider is in the "off" position than the SWITCH pin should be connected to the SYS pin. If the slider is in the "on" position than the SWITCH pin should be connected to ground. Figure 2-15 details the system operation using the slider switch configuration. POWER MANAGEMENT CORE Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65735 23 TPS65735 SLVSAI6 – JUNE 2011 www.ti.com Figure 2-15. SWITCH, Slider Power On-Off Behavior 2.11.6 Push-Button Switch Behavior The system is powered on or off by a push-button press after a press that is greater than 32 ms. The following figures (Figure 2-16 and Figure 2-17) show the system behavior and the expected VLDO output during the normal push-button operation where the on and off press timings are the same value, tON = tOFF. Figure 2-16. SWITCH, Push-button Power On Behavior 24 POWER MANAGEMENT CORE Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65735 TPS65735 SLVSAI6 – JUNE 2011 www.ti.com Figure 2-17. SWITCH, Push-button Power Off Behavior POWER MANAGEMENT CORE Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65735 25 TPS65735 SLVSAI6 – JUNE 2011 www.ti.com 3 APPLICATION INFORMATION 3.1 Applications Schematic Figure 3-1. TPS65735 Applications Schematic 3.2 Reducing System Quiescent Current (IQ) This PMU device has been optimized for low power applications. If an even lower quiescent current is desired, the following circuit and configuration can be utilized to reduce system off / sleep quiescent current further. Please note that this will cause a slight efficiency drop to the overall system due to the addition of the resistance of the FET that has been added. With this circuit, achieving an IQ of less than 1 µA is possible. Please refer to the datasheet of the MCU used in the system to determine the system IQ that is possible. 26 APPLICATION INFORMATION Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65735 TPS65735 SLVSAI6 – JUNE 2011 www.ti.com Figure 3-2. Reducing System IQ with Addition of a FET Along with this system configuration, the MCU code must be written such that the MCU sits in the lowest power state that can support an interrupt on a GPIO from a switch (slider or push button). After a valid button press or switch action, the device can begin the power on sequence and open the FET in the previous figure (Figure 3-2). This will allow power flow into the PMU and the system can then operate normally. 3.3 3.3.1 Boost Converter Application Information Setting Boost Output Voltage To set the boost converter output voltage of this device, two external resistors that form a feedback network are required. The values recommended below (in Table 3-1) are given for a desired quiescent current of 5 µA when the boost is enabled and switching. See Figure 3-3 for the detail of the applications schematic that shows the boost feedback network and the resistor names used in the table below. Figure 3-3. Boost Feedback Network Schematic APPLICATION INFORMATION Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65735 27 TPS65735 SLVSAI6 – JUNE 2011 www.ti.com Table 3-1. Recommended RFB1 and RFB2 Values (for IQ(FB) = 5 µA) (1) Targeted VBST_OUT RFB1 (1) RFB2 (1) 8V 1.3 MΩ 240 kΩ 10 V 1.8 MΩ 240 kΩ 12 V 2.2 MΩ 240 kΩ 14 V 2.4 MΩ 240 kΩ 16 V 3.0 MΩ 240 kΩ Resistance values given in closest standard value (5% tolerance, E24 grouping). These resistance values can also be calculated using the following information. To start, it is helpful to target a quiescent current through the boost feedback network while the device is operating (IQ(FB)). When the boost output voltage and this targeted quiescent current is known, the total feedback network resistance can be found. The value for RFB2 can be found by using the boost feedback pin voltage (VFB = 1.2 V, see "Electrical Characteristics" in Section 2) and IQ(FB) in the following equation: RFB1 + RFB2 = VBST_OUT / IQ(FB) RFB2 = (1.2 V) / IQ(FB) To find RFB1, simply subtract the RFB2 from RFB(TOT): RFB1 = RFB(TOT) - RFB2 3.3.2 Boost Inductor Selection The selection of the boost inductor and output capacitor is very important to the performance of the boost converter. The boost has been designed for optimized operation when a 10 µH inductor is used. Smaller inductors, down to 4.7 µH, may be used but there will be a slight loss in overall operating efficiency. A few inductors that have been tested and found to give good performance can be found in the list below: Recommended 10 µH inductors • TDK VLS201612ET-100M (10 µH, IMAX = 0.53 A, RDC = 0.85 Ω) • Taiyo Yuden CBC2016B100M (10 µH, IMAX = 0.41 A, RDC = 0.82 Ω) 3.3.3 Boost Capacitor Selection The recommended minimum value for the capacitor on the boost output, BST_OUT pin, is 4.7 µF. Values that are larger can be used with the measurable impact being a slight reduction in the boost converter output voltage ripple while values smaller than this will result in an increased boost output voltage ripple. Note that the voltage rating of the capacitor should be sized for the maximum expected voltage at the BST_OUT pin. 3.4 Bypassing Default Push-Button SWITCH Functionality If the SWITCH pin functionality is not required to power on and off the device because of different system requirements (when the SWITCH timing requirements of system will be controlled by an external microcontroller), then the feature can be bypassed. The following diagram shows the connections required for this configuration, note that INT. I/O refers to an interruptible I/O on the microcontroller. 28 APPLICATION INFORMATION Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65735 TPS65735 SLVSAI6 – JUNE 2011 www.ti.com Figure 3-4. Bypassing Default TPS65735 Push Button SWITCH Timing In a system where a different push-button SWITCH off timing is required, the SLEEP pin is used to control the power off of the device. After system power up, the MCU must force the SLEEP pin to a high state (VSLEEP > VIH(PMIC)). Once the SWITCH push-button is pressed to shut the system down, a timer in the MCU should be active and counting the desired tOFF time of the device. Once this tOFF time is detected, the MCU can assert the SLEEP signal to a logic low level (VSLEEP < VIL(PMIC)). It is on the falling edge of the SLEEP signal where the system will be powered off (see Figure 3-5) Figure 3-5. SWITCH Press and SLEEP Signal to Control System Power Off APPLICATION INFORMATION Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65735 29 PACKAGE OPTION ADDENDUM www.ti.com 23-Jun-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) TPS65735RSNR ACTIVE QFN RSN 32 3000 Green (RoHS & no Sb/Br) TPS65735RSNT PREVIEW QFN RSN 32 250 TBD Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) CU NIPDAU Level-2-260C-1 YEAR Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 22-Jun-2011 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS65735RSNR Package Package Pins Type Drawing QFN RSN 32 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 3000 330.0 12.4 Pack Materials-Page 1 4.3 B0 (mm) K0 (mm) P1 (mm) 4.3 1.5 8.0 W Pin1 (mm) Quadrant 12.0 Q2 PACKAGE MATERIALS INFORMATION www.ti.com 22-Jun-2011 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS65735RSNR QFN RSN 32 3000 340.5 338.1 20.6 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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