TPS51511 www.ti.com SLVS735A – FEBRUARY 2007 – REVISED APRIL 2007 Synchronous Switcher Controller With 2-A LDO for GPU Power FEATURES • • – Optional PGOOD – Output Discharge – Thermal Shutdown Switcher Controller: – Adjustable-Output Buck Converter, 0.75 V to 3.3 V – Wide Input Voltage Range: 3.0-V to 28-V – D-CAP™ Mode with 100-ns Load Step Response – Current Mode Option Supports Ceramic Output Capacitors – Current Sensing From RDS(ON) or Resistor – Internal Switch Supports Dynamic Output Voltage Change – Advanced PGOOD Mask Feature – Equipped With PGOOD, OVP and UVP – Output Discharge – 5 V UVLO Protection LDO Regulator: – 2-A LDO for GPU I/O Power – Input Range: Up to 5 V – Output Range: 0.75 V to 3.3 V – Requires Only 20-µF Ceramic Output Capacitor for LDO Output APPLICATIONS • • GPU Power Notebook Computers DESCRIPTION The TPS51511 is a 350-kHz D-CAP-mode synchronous switcher with a 2-A, source-only low drop-out (LDO) regulator. It is specifically designed for low cost/low noise/low external-component count power systems for GPU applications. The integrated 'OD' switch in the buck controller supports dynamic output voltage change. The current mode option of the synchronous buck converter can support pure output ceramic-capacitor applications. The open-drain LDO power-good signal can be accessed through the OD pin when it is needed in the application. The TPS51511 is available in the thermally-enhanced 20-pin QFN package, and is specified from –40°C to 85°C. +1.8 V_LDOIN 2 NC 1 20 VBST PCI Express I/O +1.2 V/ 2 A VLDOIN VI = 3 V to 28 V LL 18 3 VLDO DRVL 17 4 VLDOFB 5 GND PGND 16 TPS51511 CS 15 6 ODOFF V5IN 14 7 OD 8 COMP PGOOD 13 ENLDO 9 VOSW VSWFB ODOFF = Lo, 1.2 V ODOFF = Hi, 1.1 V GPU_core +1.1 V_Lower Power +1.2 V_Performance DRVH 19 10 11 +5 V ENSW 12 PGOOD ENSW ENLDO Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. D-CAP, PowerPAD are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007, Texas Instruments Incorporated TPS51511 www.ti.com SLVS735A – FEBRUARY 2007 – REVISED APRIL 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION TA PACKAGED DEVICES –40°C to 85°C PLASTIC RHL ORDERING PART NUMBER MINIMUM ORDER QUANTITY PINS OUTPUT SUPPLY Small Tape-and-Reel 250 20 Tape-and-Reel 3000 TPS51511RHLT TPS51511RHLR ECO PLAN Green (RoHS and no Sb/Br) ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) Input voltage range (2) Output voltage range θJA θJC (2) Thermal information VALUE UNIT VBST –0.3 to 36 V VBST (3) –0.3 to 6 V V5IN, VLDOIN –0.3 to 6 V CS, VLDOFB, VOSW –0.3 to 6 V ENSW, ENLDO, VSWFB, ODOFF –0.3 to 6 V PGND –0.3 to 0.3 V DRVH –1.0 to 36 V LL –1.0 to 30 V DRVL –0.3 to 6 V VLDO, OD, COMP, PGOOD –0.3 to 6 V Junction-to-Ambient thermal resistance 53.34 °C/W Junction-to-PowerPAD thermal resistance 8.84 °C/W TA Operating ambient temperature range –40 to 85 °C TJ Operating junction temperature range –40 to 125 °C Tstg Storage temperature –55 to 150 °C (1) (2) (3) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to the network ground terminal unless otherwise noted. Voltage value is with respect to the LL terminal. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) Supply voltage Voltage range TA 2 MIN MAX UNIT V5IN 4.75 5.25 V VBST, DRVH –0.1 34 LL –0.6 28 VLDO, VLDOFB, VOSW –0.1 3.6 PGND –0.1 0.1 ENSW, ENLDO, ODOFF, PGOOD, CS, COMP, DRVL, OD, VSWFB, VLDOIN –0.1 5.25 –40 85 Operating free-air temperature Submit Documentation Feedback V °C TPS51511 www.ti.com SLVS735A – FEBRUARY 2007 – REVISED APRIL 2007 ELECTRICAL CHARACTERISTICS over operating free-air temperature range, VV5IN = 5 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT IV5IN1 Supply current 1,V5IN TA =25°C; No load, VENSW= VENLDO = 5 V, COMP connected to capacitor 0.8 2 mA IV5IN2 Supply current 2,V5IN TA =25°C; No load, VENSW= 5,VENLDO = 0V, COMP connected to capacitor 300 600 µA IV5IN3 Supply current 3,V5IN TA =25°C; No load, VENSW = 5 V, VENLDO = 0, VCOMP = 5 V 240 500 µA IV5INSDN Shutdown current, V5IN TA =25°C; No load, VENSW = VENLDO = 0 V 0.1 1.0 µA IVLDOIN1 Supply current1,VLDOIN TA =25°C; No load, VENSW = VENLDO = 5 V 1 15 µA IVLDOIN2 Supply current 2,VLDOIN TA =25°C; No load, VENSW = 0 V, ENLDO = 5 V, 0.1 15 µA Standby current, VLDOIN TA =25°C; No load, VENSW = VENLDO = 0 V 0.1 1 µA LDO feedback voltage –40°C < TA < 85°C VLDOIN = 1.8 V, VVLDO set to 1.2 V 757 768.3 mV ∆VVLDO LDO load regulation 0 A < ILDO < 2 A, VLDOIN = 2.5 V (1), VVLDO set to 1.2 V, 0°C < TA < 85°C ILDOOC LDO current limit VLDOIN = 2.5 V (1), VLDO = 1.2 V, COUT = 2×10 µF, Raise the output current until it is limited IVLDOFBBIAS LDO feedback bias current IVLDOFBLK LDO feedback leak current IVLDOINSDN LDO VLDOFB RDS(ON) IVLDODischg Series resistance VLDO discharge current 745.6 30 mV 2 2.5 3.5 A ENLDO = 5 V, VLDOIN = 1.8 V, VLDOFB = 0.8 V –1 –0.2 1 µA ENLDO = 0 V, VLDOIN = 1.8 V, VLDOFB = 0.8 V –1 1 µA VVLDO = 2.5 V, IVLDO = 1 A; Reduce VLDOIN until VVLDO drops to 2.425 V, TA = 25°C 0.18 (2) VVLDO = 1.8 V, IVLDO = 1 A; Reduce VLDOIN until VVLDO drops to 1.746 V, TA = 25°C 0.16 (2) VVLDO = 1.2 V, IVLDO = 1 A; Reduce VLDOIN until VVLDO drops to 1.164 V, TA = 25°C 0.15 (2) ENLDO = 0 V, VLDO = 0.5 V Ω 10 17 40 0.698 0.716 0.735 mA OPEN DRAIN SWITCH Turn on threshold voltage VODOFFth1 Open drain enable threshold voltage VODOFFth2 Hysteresis 38 Second threshold voltage 1.25 Hysteresis V 8 mV µs TODOFFth1delay Turn on threshold voltage ≥ Turn off threshold voltage 32 ROD Open drain resistance TA = 25°C; VOD = 0.5 V, VODOFF = 0 V 13 IODLEAK OD switch current leakage TA = 25°C; VODOFF = 5 V –1 1 IODOFFBIAS Open drain enable bias current TA = 25°C; VODOFF = 5 V –1 1 (1) (2) V mV 50 Ω µA Because of the voltage drop on the contact of the test fixture, VLDOIN is set at 2.5 V. Ensured by design. Not production tested. Submit Documentation Feedback 3 TPS51511 www.ti.com SLVS735A – FEBRUARY 2007 – REVISED APRIL 2007 ELECTRICAL CHARACTERISTICS (continued) over operating free-air temperature range, VV5IN = 5 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 740.2 750 759.8 738.7 750 761.3 738.0 750 762.0 UNIT VOSW OUTPUT TA = 25°C VVSWFB VSWFB regulation voltage TA = 0 to 85°C (3) TA = -40 to 85°C RVOSW Input impedance, VOSW IVSWFB Input current, VSWFB IVOSWDischg Discharge current, VOSW (3) mV 750 kΩ VSWFB = 0.78 V, COMP = open –0.04 µA VSWFB = 0.78 V, COMP = 5 V –0.06 ENSW = 0 V, VOSW = 0.5 V µA 8 15 35 mA 240 300 360 µS TRANSCONDUCTANCE AMPLIFIER gm Gain TA = 25°C ICOMPSNK COMP maximum sink current ENLDO=0 V, ENSW=5 V, VSWFB=0 V, VOSW=1.94 V, COMP=1.28 V 13 µA ICOMPSRC COMP maximum source current ENLDO=0 V, ENSW=5 V, VSWFB=0 V, VOSW=1.66 V, COMP=1.28 V –13 µA VCOMPHI COMP high clamp voltage ENLDO=0 V, ENSW=5 V, VSWFB=0 V, CS=0 V, VOSW=1.66 V 1.31 1.34 1.37 V VCOMPLO COMP low clamp voltage ENLDO=0 V, ENSW=5 V, VSWFB=0V, CS=0 V, VOSW=1.94 V 1.18 1.21 1.24 V DUTY CONTROL TON Operation on time VIN = 12 V, VOSW = 1.8 V 400 ns TON0 Startup on time VIN = 12 V, VOSW = 0 V 125 ns TONMIN Minimum on time TA = 25°C 100 ns TOFFMIN Minimum off time TA = 25°C 350 ns OUTPUT DRIVERS RDRVH DRVH resistance RDRVL DRVL resistance TD Dead time Source, IDRVH = -100 mA Sink, IDRVH = 100 mA Source, IDRVL = -100 mA 3 6 0.9 3 3 6 Sink, IDRVL = 100 mA 0.9 3 DRVH-off to DRVL-on (3) 10 DRVH-on (3) 30 DRVL-off to Ω Ω ns INTERNAL BST DIODE VFBST IVBSTLK Forward voltage VV5IN-VBST, IF = 10 mA, TA = 25°C VBST leakage current VBST = 34 V, LL = 28 V, VOSW = 1.87 V, TA = 25°C 0.7 0.8 0.9 V 0.1 1 µA 0 10 mV ZERO CURRNT COMPARATOR VZC (3) 4 Zero current comparator offset –10 Ensured by design. Not production tested. Submit Documentation Feedback TPS51511 www.ti.com SLVS735A – FEBRUARY 2007 – REVISED APRIL 2007 ELECTRICAL CHARACTERISTICS (continued) over operating free-air temperature range, VV5IN = 5 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX VPGND-CS voltage, PGOOD = Hi, VCS < 0.5 V 50 60 70 VPGND-CS voltage, PGOOD = Lo, VCS < 0.5 V 20 30 40 VCS > 4.5 V, PGOOD = Hi, TA = 25°C 9 10 11 VRDS(ON)CS > 4.5 V, PGOOD = Lo, TA = 25°C 4 5 6 UNIT PROTECTION VOCL Current limit threshold ITRIP CS sink current TCITRIP TRIP current temperature coefficient sense scheme, On the basis of 25°C VOCLoff OCP comp. offset (VV5IN-CS– VPGND-LL) voltage, VV5IN-CS = 60 mV, VCS > 4.5 V VRtrip Current limit threshold setting range V5IN-CS voltage (4) mV 4500 –10 0 30 µA ppm/°C 10 mV 150 mV POWERGOOD COMPARATOR PG out from low end 87% 90% 93% PG out from high end 107% 110% 113% VTVoPG VOSW PG Threshold IPGMAX PG Sink Current VLDO = 0 V, VPGOOD = 0.5 V 2.5 7.5 TPGDEL PGOOD Delay Delay for PG in 80 130 PG hysteresis VVOSWTH VOSW threshold voltage for turning on PGOOD up limit and OVP feature VOSW threshold hysteresis voltage for turning on PGOOD up limit and OVP feature 5% mA 200 1.36 µs V VOSW = 1.5 V 10 mV UVLO/LOGIC THRESHOLD Wake up VUVV5IN V5IN UVLO threshold VIH High-level input voltage ENLDO, ENSW VIL Low-level input voltage ENLDO, ENSW VIHYS Hysteresis voltage ENLDO, ENSW IINLEAK Logic input leakage current ENLDO, ENSW IINVSWFB Input Leakage/Bias Current VSWFB -1 1 Hysteresis 3.7 4.0 4.3 0.15 0.225 0.3 2.2 V V 0.3 V –1 1 µA –1 1 µA 0.2 V PROTECTION: UVP AND OVP VOVP VOSW OVP trip threshold OVP detect TOVPDEL VOSW OVP prop delay See VUVP Output UVP trip threshold UVP detect TUVPDEL Output UVP prop delay TUVPEN Output UVP enable delay (4) 110% 115% 1.5 120% µs 70% 32 clks 1007 clks THERMAL SHUTDOWN TSDN (4) Thermal SDN threshold Shutdown temperature (4) Hysteresis (4) 160 10 °C Ensured by design. Not production tested. Submit Documentation Feedback 5 TPS51511 www.ti.com SLVS735A – FEBRUARY 2007 – REVISED APRIL 2007 DEVICE INFORMATION TOP VIEW RHL PACKAGE VLDOIN VBST 1 20 19 DRVH NC 2 VLDO 3 COMP VLDOFB 4 18 LL 17 DRVL GND 5 16 PGND TPS51511 ODOFF 6 15 CS 14 V5IN OD 7 13 PGOOD COMP 8 VOSW 9 12 ENSW 10 11 VSWFB ENLDO TERMINAL FUNCTIONS TERMINAL NAME 6 NO. VLDOIN 1 NC VLDO I/O DESCRIPTION I Input terminal of the LDO. 2 – Pin not used. No internal connection. 3 O Output terminal of the LDO. When LDO is turned off, the output capacitor is discharged by an internal FET. VLDOFB 4 I Feedback pin of the LDO. A voltage divider sets the LDO output voltage. GND 5 – Signal ground. Connect to negative terminal of the LDO output capacitor. ODOFF 6 I A comparator input. When this pin is tied to VLDOFB, OD acts as a PGOOD signal for the LDO. When connected to external logic, OD acts like a switch. See Table 1 for detailed information. OD 7 I/O The output of the multifuntional open-drain switch. COMP 8 I/O Output of the transconductance amplifier for phase compensation in current mode. Connect to V5IN to disable Gm amplifier and enable D-CAP mode. VOSW 9 I/O Switcher output voltage monitor. Input for on-time one-shot timer and advanced PGOOD masking comparator. VSWFB 10 I Feedback pin of the switcher. A voltage divider connected to this pin sets the switcher output voltage. A resistor connected between this pin and OD pin can be inserted in parallel with the low-side resistor of the voltage divider, according to the ODOFF input, to establish the dynamic voltage step. This terminal is also the input for the OVP, UVP and PGOOD comparators. ENLDO 11 I LDO-enable signal input. ENSW 12 I Switcher-enable signal input. PGOOD 13 O Power-good signal open-drain output. Pulled low when VSWFB voltage falls outside the target window comparator. The upper side of the window comparator will be masked if the VOSW volttage is lower than 1.36 V (typ.). Refer to the Advance PGOOD Mask section for details. V5IN 14 I 5V Power supply input. This 5 V supplies internal control circuitry, LDO pass FET gate drive, VDRVH and VDRVL gate drivers. CS 15 I/O Current-sense comparator input (–) for resistor current-sense mode. If connected to 5VIN through a voltage-setting resistor, constant current sinks through this pin to set the OCL point for the RDS(ON) current-sense mode. PGND 16 I/O Ground for bottom MOSFET gate driver. Also current-sense comparator input (+). DRVL 17 O Rectifying (bottom) MOSFET gate-drive output. LL 18 I/O Switching (top) MOSFET gate driver return. Current sense comparator input (–) for RDS(ON) current-sense mode. DRVH 19 O Switching (top) MOSFET gate drive output VBST 20 I/O Switching (top) MOSFET driver bootstrap voltage input. Internally connected to V5IN through an PN diode. Submit Documentation Feedback TPS51511 www.ti.com SLVS735A – FEBRUARY 2007 – REVISED APRIL 2007 TYPICAL CHARACTERISTICS V5IN SHUTDOWN CURRENT vs TEMPERATURE 1 1.80 0.90 IV5INSDN - Shutdown Current - mA IV5IN1 - Supply Current 1 - mA V5IN SUPPLY CURRENT vs TEMPERATURE 2 1.60 1.40 1.20 1 0.80 0.60 0.40 0.80 0.70 0.60 0.50 0.40 0.30 0.20 0.10 0.20 0 -50 0 50 100 TJ - Junction Temperature - °C 0 -50 150 0 50 100 150 TJ - Junction Temperature - °C Figure 1. Figure 2. VLDOIN SUPPLY CURRENT vs TEMPERATURE CS CURRENT vs TEMPERATURE 5 16 4.50 14 PGOOD = Hi 12 3.50 I(trip) - CS Current - mA ICC - Supply Current - mA 4 3 2.50 2 1.50 10 8 PGOOD = Lo 6 4 1 2 0.50 0 -50 0 50 100 TJ - Junction Temperature - °C 0 -50 150 0 Figure 3. VOSW DISCHARGE CURRENT vs TEMPERATURE 150 VLDO DISCHARGE CURRENT vs TEMPERATURE 30 IVLDODISCHG - Discharge Current - mA IVOSWDISCHG - Discharge Current - mA 100 Figure 4. 30 25 20 15 10 5 0 -50 50 TJ - Junction Temperature - °C 0 50 100 TJ - Junction Temperature - °C 150 25 20 15 10 -50 0 50 100 150 TJ - Junction Temperature - °C Figure 5. Figure 6. Submit Documentation Feedback 7 TPS51511 www.ti.com SLVS735A – FEBRUARY 2007 – REVISED APRIL 2007 TYPICAL CHARACTERISTICS (continued) OVP, UVP THRESHOLD vs TEMPERATURE SWITCHING FREQUENCY vs INPUT VOLTAGE 450 140 IOSW = 5 A, VI = 4V - 28 V, VO = 1.2 V fSW - Switching Frequency - kHz VOVP, VUVP - Threshold - % 400 VOVP 120 100 80 VUVP 350 300 250 200 150 100 50 60 -50 0 50 100 TJ - Junction Temperature - °C 0 4 150 8 12 16 20 VI - Input Voltage - V Figure 7. SWITCHING FREQUENCY vs OUTPUT CURRENT VOSW LOAD REGULATION 1.220 VI = 12 V, VO = 1.2 V IVOSW = 1 mA - 10 A, VI = 12 V, VO = 1.2 V 1.215 350 1.210 VO - Output Voltage - V fSW - Switching Frequency - kHz 400 300 250 200 150 1.205 1.2 1.195 100 1.190 50 1.185 1.180 0 2 0 4 6 IO - Output Current - A 8 10 0 2 4 6 IO - Output Current - A Figure 9. 8 10 Figure 10. VOSW LINE REGULATION LDO LOAD REGULATION AT 1.5V INPUT 1.240 1.21 VLDOIN = 1.5 V VI = 4 V - 28 V, VO = 1.2 V 1.230 1.2 VO - Output Voltage - V 1.220 VO - Output Voltage - V 28 Figure 8. 450 1.210 1.2 1.190 1.180 TA = -40°C 1.19 1.18 TA = 25°C 1.17 1.16 TA = 85°C 1.15 1.170 1.160 1.14 4 8 12 16 20 24 28 0 VI - Input Voltage - V Figure 11. 8 24 0.5 1 IL - Load Currents - A Figure 12. Submit Documentation Feedback 1.5 2 TPS51511 www.ti.com SLVS735A – FEBRUARY 2007 – REVISED APRIL 2007 TYPICAL CHARACTERISTICS (continued) LDO LOAD REGULATION AT 1.8V INPUT VOSW EFFICIENCY 1.21 100 IO = 1 mA - 10 A, VO = 1.2 V TA = -40°C 1.2 VI = 12 V VI = 8 V TA = 25°C 1.19 Efficiency - % VO - Output Voltage - V 90 1.18 TA = 85°C 1.17 80 VI = 20 V 70 1.16 60 1.15 VLDOIN = 1.8 V 1.14 0 0.5 1 IL - Load Currents - A 1.5 2 50 0.001 0.01 0.1 IO - Current - A 1 Figure 13. Figure 14. RIPPLE WAVEFORMS, HEAVY LOAD CONDITION VOSW LOAD TRANSIENT RESPONSE t - Time - 4 ms/div 10 t - Time - 20 ms/div Figure 15. Figure 16. VLDO LOAD TRANSIENT RESPONSE VOSW START-UP WAVEFORMS t - Time - 10 ms/div t - Time - 100 ms/div Figure 17. Figure 18. Submit Documentation Feedback 9 TPS51511 www.ti.com SLVS735A – FEBRUARY 2007 – REVISED APRIL 2007 TYPICAL CHARACTERISTICS (continued) VOSW SHUT-DOWN WAVEFORMS VLDO START-UP WAVEFORMS t - Time - 20 ms/div t - Time - 20 ms/div Figure 19. Figure 20. VLDO SHUT-DOWN WAVEFORMS VOSW BODE PLOT (CURRENT MODE) 180 80 60 135 40 90 20 45 0 0 Gain -20 -45 -40 -90 -60 -135 -80 100 1K 10K f - Frequency - Hz 100K -180 1M t - Time - 1 ms/div Figure 21. Figure 22. DYNAMIC VOLTAGE STEP-UP WAVEFORMS DYNAMIC VOLTAGE STEP-DOWN WAVEFORMS t - Time - 40 ms/div t - Time - 40 ms/div Figure 23. 10 Phase - deg Gain - dB Phase Figure 24. Submit Documentation Feedback TPS51511 www.ti.com SLVS735A – FEBRUARY 2007 – REVISED APRIL 2007 FUNCTIONAL BLOCK DIAGRAM ENLDO V5IN LDO_ON VLDO + V5INOK 3.7V/3.5V ENSW SW_ON GND + RefOK VOSW Ref 0.7V OD + Ref GND 1.25V 1.25V + GND GND S0 0 0 1 1 ODOFF S1 OUT 1.36V 0 A 1 B 0 C 1 D + + 0.716V VLDOIN + 0.75V+5/10% OUT High(1) 0.678V + PGOOD A B Delay 45us + D 1 VLDO S0 S1 0.75V-5/10% 0 VLDOFB 0.75V Loop path control + LDO_ON Delay PGOOD C SW_ON 0.75V-30% VSWFB VOSWOK PGND UVP + OVP + 0.75V + + Ref PWM 0.75V+15% VOSWOV + VOSW V5IN LL VOSWUV V5IN COMP V5IN VOSWOK 60/30mV + VBST OCP DRVH 1 shot + LL XCON 10/5uA V5IN DRVL GND + VOSWOK ZC PGND CS LL Ref + VOSW 4V + Submit Documentation Feedback 11 TPS51511 www.ti.com SLVS735A – FEBRUARY 2007 – REVISED APRIL 2007 DESCRIPTION TPS51511 is an integrated power-management solution that combines a synchronous buck controller and a high-current, source-only, low-dropout linear regulator (LDO) in a small 20-pin QFN package. Each output provides voltages required by typical graphic-system applications. The switching-mode power supply portion employs external N-channel MOSFETs to provide high current for a GPU core. The output voltage is adjustable from 0.75 to 3.3 V with an external divider. The input voltage range of the switcher is 3 V to 28 V. The switcher uses adaptive on-time PWM under heavy load conditions, and automatically reduces the frequency under light loads to achieve excellent efficiency down to several mA. The output of the switcher is sensed by the VOSW pin to generate the on-time pulse, with the voltage of VIN sensed by LL pin. The current sensing uses either the RDS(ON) of the external rectifying MOSFET for a low-cost, lossless solution, or a sense resistor placed in series to the rectifying MOSFET for applications needing a more accurate current limit. The LDO can source up to 2 A DC current with only 20 µF (two 10 µF in parallel) ceramic output capacitors. VOSW Switcher, Dual PWM Operation Modes The main control loop of the switcher is designed as an adaptive on-time pulse width modulation (PWM) controller. It supports two control schemes; a current mode and a proprietary D-CAP mode. D-CAP mode does not require an external compensation circuit, and is suitable for low external component count configurations using output capacitor(s) with an appropriate ESR value. Current-mode control has more flexibility, using an external compensation network, and can be used to achieve stable operation with very low-ESR capacitors such as ceramic capacitors. These control modes are selected by the COMP terminal connection. If the COMP pin is connected to V5IN, the TPS51511 is in D-CAP Mode. If the COMP pin is connected to the RC compensation network, the device operates in current mode. At the beginning of each cycle, the synchronous top MOSFET is turned on (ON state). This MOSFET is turned off (OFF state) after the internal one-shot timer expires. The on-time issued by this one-shot is proportional to the ratio of VOUT to VIN. In this way, the switching frequency can be kept reasonably constant over the input-voltage range, hence it is called adaptive on-time control (see PWM frequency and Adaptive On-time Control). The MOSFET is turned on again when the feedback information indicates insufficient output voltage and the inductor current is below the overcurrent limit. By repeating operation in this manner, the controller regulates the output voltage. The synchronous bottom, or the rectifying MOSFET, is turned on during each OFF state to minimize conduction loss. The rectifying MOSFET is turned off when the inductor current indicates zero voltage level. This enables seamless transition to the reduced frequency operation under light load conditions so that the high efficiency is maintained over the broad range of load currents. In the current-mode control scheme, the transconductance amplifier generates a target current level corresponding to the voltage difference between the feedback point and the internal 750-mV reference. During the OFF state, the PWM comparator monitors the inductor-current signal as well as the target current level, and when the inductor-current signal goes lower than the target current level, the comparator asserts the SET signal, switching the system to the ON state. The voltage-feedback gain is adjustable outside the controller IC to support various types of output MOSFETs and capacitors. In the D-CAP Mode, the transconductance amplifier is disabled and the PWM comparator directly compares the feedback-point voltage to the internal 750-mV reference during the OFF state. When the feedback point becomes lower than the reference voltage, the comparator asserts the SET signal, triggering the ON state. 12 Submit Documentation Feedback TPS51511 www.ti.com SLVS735A – FEBRUARY 2007 – REVISED APRIL 2007 VOSW Switcher, Light Load Condition TPS51511 automatically reduces the switching frequency under light load conditions to maintain high efficiency. This frequency reduction is achieved smoothly and without increasing the VOUT ripple or affecting the load regulation. As the output current decreases from a heavy load condition, the inductor current is also reduced and eventually comes to the point that its ripple-valley value decreases down to zero current, which is the boundary between continuous conduction and discontinuous conduction modes. The rectifying MOSFET will be turned off when this zero inductor current is detected. As the load current decreases further, the converter runs in discontinuous-conduction mode, and takes longer to discharge the output capacitor to the level that will issue the next ON cycle. The ON time is kept the same as that in the heavy load condition. Conversely, when the output current increases from a light load to a heavy load, the switching frequency increases to the constant 350 kHz as the inductor current reaches continuous conduction. The transition point between light and heavy-load operation IOUT(LL) (i.e., the threshold between continuous and discontinuous conduction mode) can be calculated as follows; ǒV IN * V OUTǓ V OUT 1 I OUT(LL) + 2 L ƒ V IN (1) Where f is the PWM switching frequency, 350 kHz. The switching frequency versus the output current in the light load condition is a function of L, f, VIN and VOUT, but it decreases almost proportionally to the output current from the IOUT(LL) given above. For example, it will be 35 kHz at IOUT(LL)/10 and 3.5 kHz at IOUT(LL)/100. Low-Side Driver The low-side driver is designed to drive high current low RDS(ON) N-channel MOSFETs. The drive capability is represented by its internal resistance, 3 Ω for V5IN to DRVL, and 0.9 Ω for DRVL to PGND. A dead time to prevent shoot-through is internally generated between the top MOSFET off to bottom MOSFET on, and bottom MOSFET off to top MOSFET on. The 5-V bias voltage is delivered from V5IN supply. The instantaneous drive current is supplied by an input capacitor connected between V5IN and GND. Add a ceramic capacitor with a value between 1.0 µF and 4.7 µF placed close to the V5IN pin to stabilize the 5-V output from any parasitic impedance from the supply. The average drive current is equal to the gate charge at VGS=5 V condition, times the switching frequency. This gate-drive current as well as the high-side gate-drive current times 5 V accounts for the power that must be dissipated from the TPS51511 package. High-Side Driver The high-side driver is designed to drive high-current, low RDS(ON) N-channel MOSFET(s). It is configured as a floating driver, with the 5-V bias voltage delivered from the V5IN supply. The average drive current is also calculated by the gate charge at VGS=5 V condition, times switching frequency. The instantaneous drive current is supplied by the flying capacitor between VBST and LL pins. The drive capability is represented by its internal resistance, 3 Ω for VBST to DRVH, and 0.9 Ω for DRVH to LL. Current Sensing Scheme To support both high-accuracy and low-cost current sensing applications, TPS51511 supports two different current sensing schemes; external-resistor sensing, and rectifying-MOSFET RDS(ON) sensing. In the resistor-sensing scheme, an appropriate current-sensing resistor is connected between the source terminal of the rectifying MOSFET and PGND, and the CS pin is connected to the rectifying MOSFET source terminal node. The inductor current is monitored by the voltage between PGND pin and CS pin. In the RDS(ON)-sensing scheme, the CS pin is connected to the V5IN pin through the trip-voltage setting resistor RTRIP. In this case, the CS terminal sinks the 10-µA ITRIP current, and the trip level is set to the voltage across RTRIP. The inductor current is monitored by the voltage between the PGND pin and the LL pin, so the LL pin is connected to the drain terminal of the rectifying MOSFET. ITRIP has a 4500-ppm/°C temperature slope to compensate the temperature dependency of the RDS(ON). In either scheme, PGND is used as the positive current-sensing node, so PGND must be connected to the proper current-sensing device, i.e., the sense resistor or the source terminal of the rectifying MOSFET. Submit Documentation Feedback 13 TPS51511 www.ti.com SLVS735A – FEBRUARY 2007 – REVISED APRIL 2007 PWM Frequency and Adaptive On-Time Control TPS51511 employs an adaptive on-time control scheme, and does not have a dedicated oscillator on board. However, the device runs with a fixed 350kHz pseudo-constant frequency by feed-forwarding the input and output voltage into the on-time one-shot timer. The on-time is inversely proportional to the input voltage and proportional to the output voltage so that the duty-cycle ratio is kept the same as VOUT/VIN in the same cycle time. Although the TPS51511 does not have a pin connected to VIN, the input voltage is monitored at the LL pin during the ON state. This reduces the pin count in order to make the part compact without sacrificing its performance. In order to secure minimum ON time during startup, the feed-forward feature from the output voltage is enabled after the output voltage becomes 750 mV or higher. Soft-Start and Powergood (PGOOD) The soft-start function of the switcher is achieved by ramping up the reference voltage and a two-stage current clamp. At the starting point, the reference voltage is set to 650 mV (87% of its target value), and the overcurrent threshold is set to half of the nominal value. When the UVP comparator detects an VOSW voltage greater than 80% of the target, the reference begins to ramp up and reaches 750 mV after 85 µs. 45 µs after the voltage becomes good, the power-good comparator releases the overcurrent threshold to the nominal value. TPS51511 turns off the power-good open-drain MOSFET when VOSW reaches the good state. The soft-start function of the LDO is achieved by clamping the current during startup. The threshold of the current limit is set to 2.5 A (typical). TPS51511 has an independent window comparator for each output, but the PGOOD signal indicates only the status of VOSW. If a separate powergood signal is needed for the LDO, see OD and ODOFF for configuration details. The soft-start durations, TVOSW, TVLDO are functions of output capacitances. 2 C VOSW V VOSW T VOSW + ) 80 ms I VOSWOCP (2) Where, IVOSWOCP is the current limit value for the VOSW switcher calculated by Equation 5. C VVLDO T VLDO + VLDO I VLDOOCL (3) Where, IVLDOOCL = 2.5 A (typical). In both equations, no load current during startup is assumed. Note that both the switcher and the LDO do not start up to target voltage with full load conditions. Enable and Discharge Both the switcher and LDO can be enabled by bringing the voltage on the ENSW and ENLDO pins above 2.2 V, and disabled by pulling the voltage of ENSW and ENLDO down to 0.3 V. Both the switcher and LDO have output-discharge feature. The output is discharged through an internal MOSFET when the channel is disabled. Discharge continues until the output voltage is discharged below 0.3 V. In UVP or OVP conditions of the switching power supply, the device is latched off and the discharge is enabled until the output voltage drops below 0.3 V. 14 Submit Documentation Feedback TPS51511 www.ti.com SLVS735A – FEBRUARY 2007 – REVISED APRIL 2007 Current Protection for VOSW The switcher has cycle-by-cycle current-limit control. The inductor current is monitored during the OFF state, and the controller keeps the OFF state while the inductor current is larger than the overcurrent trip level. The trip level and current-sense scheme are determined by the CS pin connection (see Current Sensing Scheme). In the resistor sensing scheme, the trip level, VTRIP, is a fixed value of 60 mV. In the RDS(ON) sensing scheme, the CS terminal sinks 10 µA and the trip level is set to the voltage across the RTRIP resistor. V TRIP(mV) + RTRIP(kW) 10(mA) (4) Because the comparison is done during the OFF state, VTRIP sets the valley level of the inductor current. Thus, the load current at the overcurrent threshold, Iocp, can be calculated as follows; ( V - VOUT ) ´ VOUT VTRIP I VTRIP 1 IOCP = + RIPPLE = + ´ IN RDS( ON) 2 RDS( ON) 2 ´ L ´ f VIN (5) In an overcurrent condition, the current to the load exceeds the current to the output capacitor, thus the output voltage tends to fall. If the output voltage becomes less than power-good level, the VTRIP level is cut in half, and the output voltage tends to be even lower. Eventually, it will end up crossing the undervoltage-protection threshold and be shut down. Over/Under Voltage Protection for VOSW The TPS51511 monitors the feedback voltage to detect overvoltage and undervoltage conditions. When the feedback voltage becomes higher than 115% of the target voltage, the OVP comparator output goes high, and the circuit latches the top MOSFET driver OFF and the bottom MOSFET driver ON. The TPS51511 also monitors the VOSW voltage directly, and if it becomes greater than 4 V, TPS51511 turns off the top MOSFET driver. When the feedback voltage becomes lower than 70% of the target voltage, the UVP-comparator output goes high, and an internal UVP delay counter starts. After 32 switching cycles, the TPS51511 latches OFF both top and bottom MOSFETs. This function is enabled after 1007 cycles from switcher startup to ensure proper startup. V5IN UVLO Protection TPS51511 has V5IN under voltage lock out protection (UVLO). When the V5IN voltage is lower than the UVLO threshold voltage, the switcher and LDO are shut off. This is a non-latching protection. LDO Operation The TPS51511 integrated LDO is a source-only 2- A LDO. It has a typical current limit of 2.5 A . It can be separately enabled via the ENLDO pin, and the output voltage is set via the external voltage divider. Only a 20 µF ceramic capacitor (2×10µF) is needed for this LDO. The transient response is very fast due to the wide bandwidth design of the LDO feedback loop. The LDO has an internally fixed constant overcurrent limit of 2.5 A. This is a trailing current limit with no shutdown function. Thermal Shutdown The TPS51511 monitors its internal temperature. If the temperature exceeds the threshold value (typically 160°C), the switcher and LDO are shut off. This is a non-latching protection, and operation is resumed when the device is cooled down by approximately 10°C. Dynamic Voltage Step, OD and ODOFF OD and ODOFF are multifunction pins. By connecting the OD pin through a resistor to VSWFB, ODOFF is connected to an external control logic signal which can control OD to switch in and out this resistor in parallel with the bottom resistor of the voltage divider. This can dynamically change the switcher output voltage during operation. If the application requires a power-good signal for the LDO rather than switcher dynamic voltage control, OD and ODOFF can be configured to support the LDO power-good feature by connecting ODOFF to VLDOFB. In this mode, connect OD through a pullup resistor to the bias voltage (i.e. 5 V, 3.3 V) to act as the LDO power-good output. The functions of ODOFF and OD pin combinations related to the ENLDO and ENSW pin voltage levels are shown in Table 1. Submit Documentation Feedback 15 TPS51511 www.ti.com SLVS735A – FEBRUARY 2007 – REVISED APRIL 2007 Table 1. OD and ODOFF Functions ENLDO ENSW Hi (1) (2) (3) X Lo Hi Lo Lo ODOFF (1) OD (2) Applications (3) > 1.25 V Off D 0.716 V < ODOFF < 1.25 V and lasts longer than 45 µs Off D&G 0.716 V < ODOFF < 1.25 V and lasts less than 45 µs Keep State G 0.678 V < ODOFF < 0.716 V Keep State G < 0.678 V On D&G > 1.25 V Off D < 1.25 V On D&G X On G All voltages are typical values. "Keep state" means no state change with previous state, “On” means open drain MOSFET is turned on and OD is connected to ground through this MOSFET. “Off” means open drain MOSFET off. “D” stands for dynamic voltage change “G” stands for LDO PGOOD . Advanced PGOOD Mask The advanced PGOOD mask feature allows the switcher to dynamically change the output voltage while maintaining the PGOOD and OVP functions during the transition. During the dynamic voltage change, if the output voltage is lower than 1.36 V (typ) the high-end PGOOD comparator and OVP comparator is masked. If the output voltage is set equal to or higher than 1.36 V (typ), the blanking circuit is disabled, and the high-end PGOOD threshold is set to 110%, and the OVP threshold is set to 115% of the output-voltage setting . When dynamic voltage change is implemented, a 1-nF ceramic capacitor must be added in parallel with the top resistor of the voltage divider as shown in Figure 27. APPLICATION INFORMATION LOOP COMPENSATION AND EXTERNAL PARTS SELECTION Current Mode Operation A buck converter using TPS51511 current mode operation can be partitioned into three portions, a voltage divider, an error amplifier and a switching modulator. By linearizing the switching modulator, we can derive the transfer function of the whole system. Since the current-mode scheme directly controls the inductor current, the modulator can be linearized as shown in Figure 25. Voltage Divider VOSW R1 VIN Gm = 300 mS Filter R2 DRVH Ref 0.75 V PWM Control Logic and Driver Lx DRVL ESR COMP Rc RL CS Ro = 75 M CO RS Cc2 PGND Cc Error Amplifier Switching Modulator Figure 25. Simplified Current-Mode Functional Blocks In this representation, the inductor is located inside the local feedback loop, and its inductance does not appear in the small-signal model. As a result, a modulated current source including the power inductor can be modeled 16 Submit Documentation Feedback TPS51511 www.ti.com SLVS735A – FEBRUARY 2007 – REVISED APRIL 2007 APPLICATION INFORMATION (continued) as a current source with its transconductance of 1/Rs, and the output capacitor represents the modulator portion. This simplified model is applicable in the frequency space up to approximately half the switching frequency. Although the inductance has no influence in the small-signal model, it influences the large-signal model by limiting the slew rate of the current source. This means that the buck converter’s load-transient response, one of the large signal behaviors, can be improved by using a smaller inductance without affecting loop stability. The total open-loop transfer function of the whole system is given by H(s) = H1(s) ´ H2(s) ´ H3(s) (6) Assuming RL>>ESR, Ro>>Rc and Cc>>Cc2, the transfer function of each block is R2 H 1(s) + ǒR2 ) R1Ǔ (7) H2 (s) = -Gm ´ Ro(1 + s ´ Cc ´ Rc ) (1 + s ´ Cc ´ Ro)(1 + s ´ Cc 2 ´ Rc ) H 3(s) + 1 ) s 1)s Co Co ESR RL (8) RL Rs (9) There are three poles and two zeros in H(s). Each pole and zero is given by ωp1 = 1/(Cc × Ro) ωp2 = 1/(Co × RL) ωz1 = 1/(Cc × Rc) ωz2 = 1/(Co × ESR) ωp1 = 1/(Cc2 × Rc) Usually, each frequency of the poles and zeros is lower than the 0dB frequency, f0. However, the f0 should be kept under 1/3 of the switching frequency to avoid the effect of switching-circuit delay. The f0 is given by Equation 10. R1 Gm Rc + 1 0.75 Gm Rc ƒo + 1 2p R 1 ) R 2 2p Vout Co Rs Co Rs (10) Based on the small-signal analysis above, the external components can be selected by the following steps: 1. Choose the inductor. The inductance value should be determined to give a ripple current of approximately 1/4 to 1/3 of the maximum output current. L+ 1 IIND(ripple) ǒVIN(max) * VOUTǓ ƒ VIN(max) VOUT + 3 IOUT(max) ǒVIN(max) * VOUTǓ ƒ VIN(max) VOUT (11) The inductor also needs low DCR to achieve good efficiency, as well as enough room above peak inductor current before saturation. The peak inductor current can be estimated as follows. Vtrip ( VIN(max) - VOUT ) ´ VOUT 1 IIND(peak ) = + ´ RDS( ON) L ´ f VIN(max) (12) 2. Choose the rectifying (bottom) MOSFET. When the RDS(ON) sensing scheme is selected, the rectifying MOSFET’s on-resistance is used as this Rs so that lower RDS(ON) does not always promise better performance. In order to clearly detect inductor current, minimum Rs recommended is to give 15 mV or larger ripple voltage with the inductor ripple current. This will provide smooth transitions from CCM to DCM or vice versa. The upper side of the RDS(ON) is of course restricted by the efficiency requirement, and usually this resistance affects efficiency more at high load conditions. When using external-resistor current sensing, there is no restriction for low RDS(ON). However, the current sensing resistance Rs itself affects the efficiency. 3. Choose the output capacitor(s). When using organic semiconductor capacitors (OS-CON) or specialty polymer capacitors (SP-CAP), the ESR Submit Documentation Feedback 17 TPS51511 www.ti.com SLVS735A – FEBRUARY 2007 – REVISED APRIL 2007 APPLICATION INFORMATION (continued) to achieve required ripple value at stable state or transient load conditions will determine the number and size of capacitor(s) needed, and the resulting capacitance will then be enough to satisfy stable operation. The peak-to-peak ripple value can be estimated by ESR times the inductor ripple current for stable state, or ESR times the load-current step for a fast transient-load response. Ceramic capacitors typically have ESR values small enough to meet the ripple requirement. On the other hand, transient undershoot and overshoot driven by output capacitance will become the key factor to determine the capacitance. 4. Determine f0 and calculate Rc using Equation 13. Co Rc v 2p ƒ0 Vout Rs 0.75 Gm (13) Note that higher Rc shows faster transient response at the cost of instability. If the transient response is not enough even with a high Rc value, try increasing the output capacitance. Recommended f0 is fosc/4. Then Rc can be derived by the next simplified equation. Rc + 2.4 Vout Co[mF] Rs[mW] (14) 5. Calculate Cc2. The purpose of this capacitance is to cancel the zero caused by the output capacitor ESR. If ceramic capacitors are used, there is no need for Cc2. 1 1 w z2 + + w p3 + (Co ESR) (Cc2 Rc) (15) Cc2 + Co ESR Rc (16) 6. Calculate Cc. The purpose of Cc is to cut the DC component to obtain a high DC-feedback gain. However, because this causes phase delay, another zero to cancel this effect at f0 frequency is needed. This zero, ωz1, is determined by Cc and Rc. Recommended ωz1 is 10 times lower than the f0 frequency. ƒ 1 ƒ z1 + + 0 10 2p Cc Rc (17) 10 18 Cc + ^ [nF] 2p Rc ƒ 0 Rc[kW] (18) 7. Determine the value of R1 and R2. Recommended R2 value is from 10 kΩ to 100 kΩ. Determine R1 using Equation 19. R 1 + Vout * 0.75 R2 0.75 (19) D-CAP™ Mode Operation A buck converter system using D-CAP mode can be simplified as shown in Figure 26. Voltage Divider VOSW R1 VIN R2 PWM 0.75 V DRVH Control Logic and Driver Lx DRVL IL IC IO ESR RL VC Switching Modulator CO Figure 26. Simplified D-CAP Mode Buck Converter Functional Blocks 18 Submit Documentation Feedback TPS51511 www.ti.com SLVS735A – FEBRUARY 2007 – REVISED APRIL 2007 APPLICATION INFORMATION (continued) The VOSW voltage is compared with the internal reference voltage from the divider resistors. The PWM comparator determines the timing to turn on the top MOSFET. The gain and speed of the comparator is high enough to keep the voltage at the beginning of each on cycle (or the end of off cycle) substantially constant. The DC output voltage may have line regulation due to ripple amplitude that slightly increases as the input voltage increases. To ensure loop stability, the 0dB frequency, f0, defined below, should be lower than 1/3 of the switching frequency. ƒ 1 ƒ0 + v sw 3 2p ESR Co (20) Because f0 is determined solely by the output capacitor’s characteristics, the loop stability of D-CAP Mode is determined by the capacitor’s chemistry. For example, specialty polymer capacitors (SP-CAP) have Co in the order of several-hundred µF and ESR values in the range of 10 mΩ. These will make f0 approximately 100 kHz or less, and the loop will be stable. However, ceramic capacitors have f0 at more than 700 kHz, which is not suitable for this mode. D-CAP mode provides many advantages such as ease-of-use, minimum external component count and extremely short response time. However, because it does not employ an error amplifier in the loop, a sufficient amount of feedback signal must be provided by the external circuit to reduce jitter level. A good layout which follows the layout considerations in this data sheet also can reduce the jitter level. Components selection is much simpler in D-CAP mode. 1. Choose inductor. This section is the same as the current mode. Refer to the instructions in the Current Mode Section. 2. Choose output capacitor(s). Organic semiconductor capacitor(s) or specialty polymer capacitor(s) are recommended. Thermal Design The primary power dissipation of TPS51511 is generated from the LDO. The potential difference between VLDOIN and VLDO times LDO current gives the power dissipation, WDSRC, W DSRC + ǒVVLDOIN * VVLDOǓ I VLDO (21) Another power consideration is the current used for internal control circuitry from the V5IN supply. V5IN supports both the internal circuitry and the external MOSFET drive current. These powers need to be effectively dissipated from the package. Maximum power dissipation allowed to the package is calculated by, T J(max) * T A(max) V PKG + q JA (22) Where: TJ(max) is 125°C TA(max) is the maximum ambient temperature in the system θJA is the thermal resistance from the silicon junction to the ambient This thermal resistance strongly depends on the board layout. TPS51511 is assembled in a thermally enhanced PowerPAD package that has an exposed die pad underneath the body. For maximum thermal performance, this die pad must be attached to a ground trace via a thermal land on the PCB. This ground trace acts as a heat sink. The typical thermal resistance, 53.3°C/W, is achieved based on a 3,05 mm × 2,05 mm thermal land with 6 vias without air flow. It can be improved by using a larger thermal land and/or increasing the number of vias. Further information about PowerPAD™ and its recommended board layout is described in a Texas Instruments document, SLMA002. This document is available at www.TI.com. Submit Documentation Feedback 19 TPS51511 www.ti.com SLVS735A – FEBRUARY 2007 – REVISED APRIL 2007 APPLICATION INFORMATION (continued) Layout Considerations Below are some points to be considered before the layout of TPS51511 design begins. • The PCB trace defined as LL node, which connects to the source of the switching MOSFET, the drain of the rectifying MOSFET, and the high voltage side of the inductor, should be as short and wide as possible. • Consider adding a small snubber circuit consisting of a 3-Ωresistor and 1-nF capacitor between LL and PGND if a high frequency surge is observed on the LL voltage waveform. • V5IN input capacitor, 1 µF - 4.7 µF, should be placed near the V5IN pin, within 0.1" (2,5 mm), if possible. • All sensitive analog traces such as VOSW, VSWFB,VLDOFB and CS should be placed away from high-voltage switching nodes such as LL, DRVL or DRVH nodes to avoid coupling. • An input bypass capacitor should be placed to VLDOIN as close as possible with short and wide connection. • The output capacitor for VLDO should be placed close to the pin with short and wide connections in order to avoid additional ESR and/or ESL of the trace. • In order to effectively remove heat from the package, prepare thermal land and solder to the package’s thermal pad. Using a wide trace for the component-side copper, connected to this thermal land, will help heat dissipation. Numerous vias of 0,33 mm diameter connected from the thermal land to the internal/solder-side ground plane(s) should be used to help dissipation. Do NOT connect PGND to this thermal land underneath the package. APPLICATION CIRCUITS +1.8 V_LDOIN VIN = 3 V to 28 V 10 mF 0.1 mF C1 10 mF 30 kW NC 3 VLDO 4 VLDOFB DRVL 17 5 GND PGND 16 6 ODOFF 7 OD TPS51511 GPU_core +1.1 V_lower power +1.2 V_performance/12 A DRVH 19 L LL 18 Q2 1 nF C2 COMP 9 VOSW V5IN 14 14 kW 6,34 kW 1 mF 30 kW 100 kW PGOOD 13 ENLDO 8 C3 CS 15 105 kW VSWFB ODOFF = Lo, 1.2 V ODOFF = Hi, 1.1 V 20 2 COMP 18 kW 10 mF 1 VBST PCI Express I/O +1.2 V/ 2 A VLDOIN Q1 10 11 4.7 mF +5 V ENSW 12 PGOOD ENSW ENLDO Symbol L C1 C2 C3 Q1 Q2 Specification 1 mH 3X10 mF 330 mF 330 mF 30 V, 13 mW 30 V, 5 mW Manufacturer Vishay TDK Sanyo Sanyo IR IR Part Number IHLP5050 C3225X5R1E106M 2R5TPE330MC 2R5TPE330MC IRF7821 IRF7832 Figure 27. D-CAP Mode, RDS(ON) Sensing, 1-Bit DAC for the Output Voltage Dynamic Change 20 Submit Documentation Feedback TPS51511 www.ti.com SLVS735A – FEBRUARY 2007 – REVISED APRIL 2007 APPLICATION INFORMATION (continued) +1.8 V_LDOIN VIN = 3 V to 28 V 10 mF 0.1 mF C1 10 mF 30 kW NC 3 VLDO 4 VLDOFB DRVL 17 5 GND PGND 16 6 ODOFF TPS51511 GPU_core +1.1 V_lower power +1.2 V_performance/12 A DRVH 19 L LL 18 Q2 1 nF C2 7 OD 8 COMP 9 VOSW C3 14 kW 6,34 kW 1 mF CS 15 105 kW V5IN 14 30 kW 100 kW PGOOD 13 ENLDO 33 kW 2 VSWFB ODOFF = Lo, 1.2 V ODOFF = Hi, 1.1 V 20 COMP 18 kW 10 mF 1 VBST PCI Express I/O +1.2 V/ 2 A VLDOIN Q1 10 11 4.7 mF +5 V ENSW 12 PGOOD ENSW 4700 pF ENLDO Symbol L C1 C2 C3 Q1 Q2 Specification 1 mH 3X10 mF 47 mF 47 mF 30 V, 13 mW 30 V, 5 mW Manufacturer Vishay TDK TDK TDK IR IR Part Number IHLP5050 C3225X5R1E106M C3225X5R0J476K C3225X5R0J476K IRF7821 IRF7832 Figure 28. Current Mode, RDS(ON) Sensing, 1-Bit DAC for the Output Voltage Dynamic Change Submit Documentation Feedback 21 TPS51511 www.ti.com SLVS735A – FEBRUARY 2007 – REVISED APRIL 2007 APPLICATION INFORMATION (continued) +1.8 V_LDOIN VIN = 3 V to 28 V 10 mF 0.1 mF C1 VLDO 4 VLDOFB DRVL 17 5 GND PGND 16 6 ODOFF PGOOD_LDO 100 kW 33 kW VBST NC 3 7 OD 8 COMP 9 VOSW NU DRVH 19 TPS51511 1.2 V/12 A L LL 18 Q2 1 nF C2 C3 18 kW 6,34 kW 1 mF CS 15 V5IN 14 30 kW 100 kW PGOOD 13 ENLDO 10 mF 30 kW 2 COMP 18 kW 10 mF 20 VSWFB +1.2 V/ 1 A 1 VLDOIN Q1 10 11 4.7 mF +5 V ENSW 12 PGOOD ENSW 4700 pF ENLDO Symbol L C1 C2 C3 Q1 Q2 Specification 1 mH 3X10 mF 47 mF 47 mF 30 V, 13 mW 30 V, 5 mW Manufacturer Vishay TDK TDK TDK IR IR Part Number IHLP5050 C3225X5R1E106M C3225X5R0J476K C3225X5R0J476K IRF7821 IRF7832 Figure 29. Current Mode Single Switcher, OD and ODOFF Configure to Second PGOOD for LDO 22 Submit Documentation Feedback PACKAGE MATERIALS INFORMATION www.ti.com 17-May-2007 TAPE AND REEL INFORMATION Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com Device 17-May-2007 Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS51511RHLR RHL 20 MLA 330 12 3.8 4.8 1.6 8 12 PKGORN T1TR-MS P TPS51511RHLT RHL 20 MLA 180 12 3.8 4.8 1.6 8 12 PKGORN T1TR-MS P TAPE AND REEL BOX INFORMATION Device Package Pins Site Length (mm) Width (mm) TPS51511RHLR RHL 20 MLA 346.0 346.0 29.0 TPS51511RHLT RHL 20 MLA 190.0 212.7 31.75 Pack Materials-Page 2 Height (mm) PACKAGE MATERIALS INFORMATION www.ti.com 17-May-2007 Pack Materials-Page 3 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety-critical applications. TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security RFID www.ti-rfid.com Telephony www.ti.com/telephony Low Power Wireless www.ti.com/lpw Video & Imaging www.ti.com/video Wireless www.ti.com/wireless Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2007, Texas Instruments Incorporated