NX2422 TWO PHASE SYNCHRONOUS PWM CONTROLLER WITH INTEGRATED FET DRIVER, DIFFERENTIAL CURRENT SENSE & 5V BIAS REGULATOR PRELIMINARY DATA SHEET Pb Free Product FEATURES DESCRIPTION The NX2422 is a two-phase PWM controller with inte- n Differential inductor DCR sensing eliminates the problem with layout parasitic grated FET driver designed for low voltage high current n 5V bias regulator available application. The two phase synchronous buck converter n Low Impedance On-board Drivers offers ripple cancelation for both input and output. The n Hiccup current limit and IOUT indication NX2422 uses differential remote sensing using either curn Power Good for power sequencing rent sense resistor or inductor DCR sensing to achieve n EN2_B pin allows the slave channel on and off while accurate current matching between the two channels. the master channel is working Differential sensing eliminates the error caused by PCB n Programmable frequency board trace resistance that otherwise presents when usn Prebias start up ing a single ended voltage sensing. In addition the NX2422 offers high drive current capabil- n OVP without negative spike at output ity especially for keeping the synchronous MOSFET off n Selectable between internal and external reference during SW node transition, can provide regulated 5V to n Internal Schottky diode from PVCC to BST IC biasing and drivers via 5V bias regulator, allows the n Pb-free and RoHS compliant slave channel on and off via EN2_B pin while the main channel is working. Other features: PGOOD output, pro- n Graphic card High Current Vcore Supply grammable switching frequency and hiccup current lim- n High Current on board DC to DC converter iting circuitry. applications APPLICATIONS TYPICAL APPLICATION 12V BUS C11 R10 C10 2N3904 VCCDRV BST1 2N3904 5V C12 R13 R14 HDRV1 Q1 L1 VOUT SW1 C13 PVCC C31 LDRV1 R11 Q2 C30 C14 R29 C15 5VCC AGND C29 R15 CSCOMP C28 R16 RT R17 IOUT/IMAX R28 CS+1 NX2422 REFIN CS-1 C17 C19 HDRV2 Q3 C27 C26 R18 L2 SW2 VCOMP R19 C18 BST2 LDRV2 C25 C20 R27 Q4 C21 C22 FB R20 EN2_B VOUT R26 CS+2 CS-2 R24 PGND(PAD) Ref for external circuitry INREFOUT/POK C24 Figure1 - Typical application of NX2422 ORDERING INFORMATION Device NX2422CMTR Rev.2.1 12/01/08 Temperature 0 to 70oC Package MLPQ 4x4 - 24L Frequency 50kHz to 1MHz Pb-Free Yes 1 NX2422 ABSOLUTE MAXIMUM RATINGS Vcc to PGND & BST to SW voltage .................... -0.3V to 6.5V BST to PGND Voltage ...................................... -0.3V to 35V SW to PGND .................................................... -2V to 35V All other pins .................................................... -0.3V to 6.5V Storage Temperature Range ............................... -65oC To 150oC Operating Junction Temperature Range ............... -40oC To 125oC Lead temperature(Soldering 5s) ........................... 260oC CAUTION: Stresses above those listed in "ABSOLUTE MAXIMUM RATINGS", may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. PACKAGE INFORMATION LDRV2 θJA ≈ 30.5o C/W SW2 VCCDRV PVCC LDRV1 SW1 24 LEAD PLASTIC MLPQ 24 23 22 21 20 19 1 18 HDRV2 BST1 2 17 BST2 5VCC 3 16 INREFOUT/POK AGND 4 15 EN2_B 5 14 CSCOMP CS+1 6 13 FB 9 10 11 12 CS-2 IOUT/IMAX REFIN VCOMP 8 RT 7 CS+2 PGND(PAD) CS-1 HDRV1 ELECTRICAL SPECIFICATIONS Unless otherwise specified, these specifications apply over 5Vcc = 5V, PVcc= 5V, VBST-VSW =5V, EN2_B=GND, and TA = 0 to 70oC. Typical values refer to TA = 25oC. Low duty cycle pulse testing is used which keeps junction and case temperatures equal to the ambient temperature. PARAMETER Supply Voltage(Vcc) 5VCC ,PVCC Voltage Range SYM TEST CONDITION VCC 5VCC Supply Current (static) ICC (Static) REFIN=GND, EN2_B=5V PVCC Supply Current (Dynamic) REFIN=5V, EN2_B=GND, ICC Freq=200Khz per phase (Dynamic) CLOAD=2200PF VBST Voltage Range VBST to VSW VBST Supply Current ((Dynamic)) REFIN=5V, EN2_B=GND, VBST Freq=200Khz per phase (Dynamic) CLOAD=2200PF Rev.2.1 12/01/08 MIN TYP MAX UNITS 4.5 5 5.5 V - 6.7 mA 4.4 mA 4.5 5 4.5 5.5 V mA 2 NX2422 PARAMETER SYM TEST CONDITION MIN TYP MAX UNITS Under Voltage, Vcc & EN2_B VCC-Threshold VCC-Hysteresis EN2_B Threshold EN2_B Hysteresis Reference Voltage Ref Voltage Ref Voltage line regulation Oscillator (Rt) Frequency for each phase Ramp-Amplitude Voltage Ramp Peak Ramp Valley Max Duty Cycle Min Duty Cycle Transconductance Amplifiers(CSCOMP) Open Loop Gain Transconductance Voltage Mode Error Amplifier Open Loop Gain Input Offset Voltage Output Current Source Output Current Sink Output HI Voltage Output LOW Voltage SS (Internal ) Soft Start time POK/INFEROUT Threshold Hysteresis POK Voltage High Side Driver (CL=4700pF) Output Impedance , Sourcing Current Output Impedance , Sinking Current Rise Time Fall Time Deadband Time Low Side Driver (CL=10000pF) Output Impedance, Sourcing Current Output Impedance, Sinking Current Rev.2.1 12/01/08 VCC_UVLO VCC_Hyst VCC Rising VEN2_B Rising VREF Fs VRAMP 4.5V<5Vcc<5.5V Rt=100kohm 200Khz/Phase 4.1 0.4 0.82 80 V V V mV 0.6 V 0.2 % 400 1.02 KHz V 2.2 1.18 97 V V % % 0 50 65 1600 dB umoh 50 Vio_v 0 5 5 Vcc-1.5 0.5 Tss dB mV mA mA V V 400Khz/Phase 2.5 mS VFB Rising 73 5 1.215 %VP % V IOUT=5mA(sourcing) 1.191 1.24 Rsource(Hdrv) I=200mA 1 ohm Rsink(Hdrv) I=200mA 0.7 ohm 19 18.5 40 ns ns ns THdrv(Rise) 10% to 90% THdrv(Fall) 90% to 10% Tdead(L to Ldrv going Low to Hdrv going H) High, 10%-10% Rsource(Ldrv) I=200mA 1 ohm Rsink(Ldrv) I=200mA 0.5 ohm 3 NX2422 PARAMETER Supply Voltage(Vcc) Rise Time Fall Time Deadband Time Propagation Delay Current Sense Amplifier(CS+, CS-) Input Offset Voltage Voltage Gain OVP Threshold OVP Threshold FB UVLO Threshold FB UVLO Threshold REFIN VOLTAGE REFIN Voltage Range Disable Voltage Threshold Threshold Enable Internal Reference 5V AUX REG Regout Output Voltage High Regout Output Voltage Low Internal Schottky Diode Forward voltage drop Rev.2.1 12/01/08 SYM TEST CONDITION TLdrv(Rise) 10% to 90% TLdrv(Fall) 90% to 10% Tdead(H to SW going Low to Ldrv going L) High, 10% to 10% Tdealy(H) IN going High to Ldrv going Low MIN TYP 34 18 10 MAX 14 -2 29.7 30 UNITS ns ns ns ns 2 30.3 mV V/V percent of Vp 130 % percent of Vp 70 % 0.4 0.3 0.35 75 2.5 0.4 V V %VCC VIN=12V, PVCC=3V VIN=12V, PVCC=5.8V, VCCDRV connected to 12V by 1k resistor 11 2 V V forward current=10mA 600 mV 4 NX2422 PIN DESCRIPTIONS SYMBOL HDRV1 High side gate driver for Channel 1. BST1 Bootstrap supply for Channel 1. 5VCC IC’s supply voltage. This pin biases the internal logic circuits. A minimum 1uF ceramic capacitor is recommended to connect from this pin to ground plane. AGND Controller analog ground pin. EN2_B This pin is used to startup or shutdown the channel2 only while 5VCC and REFIN is ready. For two phase opeartion, EN2_B is preferred to be tied to GND. For one phase opeartion, EN2_B is preferred to be tied to 5VCC. During the operation, it is not recommended to change EN2_B voltage. CS+1 Positive input of the channel 1 differential current sense amplifiers. It is connected directly to the RC junction of the respective phase’s output inductor. CS-1 Negative input of the channel 1 differential current sense amplifiers. It is connected directly to the negative side of the respective phase’s output inductor. CS-2 Negative input of the channel 2 differential current sense amplifiers. It is connected directly to the negative side of the respective phase’s output inductor. CS+2 Positive input of the channel 2 differential current sense amplifiers. It is connected directly to the RC junction of the respective phase’s output inductor. IOUT/IMAX This pin indicates average output current level and sets OCP threshold using a resistor from this pin to ground. A no more than 1nF ceramic capacitor is recommended to connect this pin to ground plane to filter the noise on this pin. RT This pin programs the internal oscillator frequency using a resistor from this pin to ground. VCOMP FB CSCOMP Rev.2.1 12/01/08 PIN DESCRIPTION This is the output pin of the error amplifier. This pin is the error amplifier inverting input. It is connected to the output voltage via a voltage divider. The output of the transconductance op amp for current balance circuit. An external RC is connected from this pin to GND to stabilize the current loop. REFIN External reference input. If pull-up to >4.5V, internal reference is used. If driven by an external voltage ranged from 0.4V to 2.5V, external reference is used with slew rate following SS rate. If REFIN is below 0.4V, device is disabled. INREFOUT/ POK This pin has dual functions. When FB pin is below 75% of internal 0.6V reference, this pin is held low. When FB reaches above this threshold, this pin is tied to an internal 1.25V reference, allowing it to be used as a reference for any external op amp circuitry as well as an indicator of power OK. This pin can not be connected directly to an output capacitor. An RC network is needed which also provides a slow ramp up of the reference for the external op amp. 5 NX2422 SYMBOL BST2 HDRV2 SW2 PIN DESCRIPTION Bootstrap supply for Channel 2. High side gate driver for Channel 2. Switch node for Channel2. LDRV2 Low side gate driver for Channel 2. PVCC This pin provide the supply voltage for the lower MOSFET drivers. This pin provide the supply voltage for the lower MOSFET drivers. A high frequency ceramic 1uF must be placed close to this pin and tied to PGND to provide peak current needed for low side MOSFETs. LDRV1 Low side gate driver for Channel 1. SW1 PGND Switch node for Channel 1. This is the ground connection for the power stage of the controller. The output of the 5V regulator controller that drives a low current low cost exter- VCCDRV nal BIPOLAR transistor or an external MOSFET to regulate the voltage at Vcc pin derived from BUS voltage. A resistor with value from 1k to 10k is used to connect VCCDRV and VBUS. Pulling down VCCDRV is used to disable chip in NX2422 application . Rev.2.1 12/01/08 6 NX2422 BLOCK DIAGRAM +12V VCCDRV 1.25V OFF ON 5VCC Bias generator +5V PVCC 0.6V 1.6V UVLO UVLO OVP 1.25V BST1 +5V +12V EN2_B +5V ENBUS_2 Hiccup ON 0.82/0.74 OFF DAC DrvH1 start SW1 0.35 /0.3V REFIN FET driver FILTER 0.6V VOUT VOUT +1.2V/50A DrvL1 PGND ENBUS_2 3.6 /3.3V Vp Digital start BST2 SS_finish DrvH2 Dis_EA SW2 FB R S VCOMP ramp1 DrvL2 Set1 K=30 Two phase OSC KR V1.25 R CS01 set2 Rt Q CS-1 KR CS02 ramp2 R PWM control logic and driver Vp*130% FILTER CS+1 OVP KR V1.25 R CS+2 CS-2 FB R CScomp(SS/EN) KR Slave channel control Vp*75% Hiccup SS_finished Hiccup Logic V1.25 Σ ÷2 Σ gm=0.04mA/V IOUT/IMAX INREFOUT/POK 1.25V 6 Cycles filter 1.25V SS_FINISHED AGND Vp*70% FB Figure 2 - Block diagram of NX2422 Rev.2.1 12/01/08 7 NX2422 APPLICATION INFORMATION Symbol Used In Application Information: VIN - Input voltage VOUT - Output voltage IOUT - Output current Choose inductor from Vishay IHLP_5050FD-01 with L=0.68uH DCR=1.4mΩ. Current Ripple is recalculated as ∆IRIPPLE = DVRIPPLE - Output voltage ripple FS L OUT =0.54uH - Operation frequency for each channel = DIRIPPLE - Inductor current ripple VIN -VOUT VOUT 1 × × LOUT VIN FS ...(2) 12V-1.2V 1.2V 1 × × = 3.97A 0.68uH 12V 400kHz Output Capacitor Selection Design Example The following is typical application for NX2422. Output capacitor value is basically decided by the VIN = 12V output voltage ripple, capacitor RMS current rating and VOUT=1.2V IOUT_max=60A load transient. Based on Voltage Ripple For electrolytic, POSCAP bulk capacitor, the ESR DVRIPPLE <=12mV (equivalent series resistance) and inductor current typi- DVDROOP<=120mV @30A step cally determines the output voltage ripple. IOUT=50A FS=400kHz ESRdesire = Phase number N=2 ∆VRIPPLE 12mV = = 3.022mΩ ∆IRIPPLE 3.97A ...(3) If low ESR is required, for most applications, mul- Output Inductor Selection tiple capacitors in parallel are better than a big capaci- The selection of inductor value is based on induc- tor. For example, for 12mV output ripple, SANYO OS- tor ripple current, power rating, working frequency and CON capacitors 2R5SEPC1000MX(1000uF 7mΩ) are efficiency. Larger inductor value normally means smaller chosen. ripple current. However if the inductance is chosen too large, it brings slow response and lower efficiency. Usu- N = ally the ripple current ranges from 20% to 40% of the output current. This is a design freedom which can be decided by design engineer according to various application requirements. The inductor value can be calculated by using the following equations: L OUT = VIN -VOUT VOUT 1 × × ∆IRIPPLE VIN FS ∆IRIPPLE =k × IOUTPUT N where k is between 0.2 to 0.4. Select k=0.2, then ...(1) E S R E × ∆ IR I P P L E ∆ VR IPPLE ...(4) Number of Capacitor is calculated as 7m Ω × 3.97A 12mV N =2.3 For ceramic capacitor, the current ripple is determined by the number of capacitor instead of ESR N= COUT = ∆IRIPPLE 8 × FS × ∆VRIPPLE ...(5) Typically, the calculated capacitance is so small that the output voltage droop during the transient can not meet the spec although ripple is small. 12V-1.2V 1.2V 1 L OUT = × × 50A 12V 400kHz 0.2 × 2 Rev.2.1 12/01/08 8 NX2422 Based On Transient Requirement Typically, the output voltage droop during transient is specified as: ∆VDROOP <∆VTRAN @ step load DISTEP During the transient, the voltage droop during the transient is composed of two sections. One Section is dependent on the ESR of capacitor, the other section is a function of the inductor, output capacitance as well as input, output voltage. For example, overshoot caused by DISTEP transient load which is from high load to low load, can be estimated as the following equation,if assuming the bandwidth of system is high enough. ∆Vovershoot = ESR × ∆Istep + VOUT × τ2 2 × L × COUT ...(6) where τ is the a function of capacitor, etc. 0 if LEFF ≤ Lcrit τ = LEFF ×∆Istep − ESR × COUT V OUT ...(7) If the OS-CON capacitors (1000uF, 7mΩ ) is used, the critical inductance is given as Lcrit = The effective inductor value is 0.34uH which is big- number of capacitors is in parallel. The above equation shows that if the selected output inductor is smaller than the critical inductance, the voltage droop or overshoot is only dependent on the ESR of output capacitor. For low frequency capacitor such as electrolytic capacitor, the product of ESR and capacitance is high and L ≤ L crit is true. In that case, the transient spec is dependent on the ESR of capacitor. In most cases, the output capacitors are multiple capacitors in parallel. The number of capacitors can be calculated by the following + VOUT × τ2 2 × L × C E × ∆Vtran LEFF × ∆Istep VOUT − ESR E × CE 0.34µH × 30A − 7mΩ × 1000µF = 1.5us 1.2V ...(8) where ESRE and CE represents ESR and capaci- ∆Vtran ESR E × C E × VOUT = ∆Istep 7mΩ × 1000µF × 1.2V = 0.28µH 30A = tance of each capacitor if multiple capacitors are used Rev.2.1 12/01/08 is 120mV for 30A load step. capacitance. if LEFF ≥ Lcrit LOUT 0.68uH = = 0.34uH N 2 ESR × COUT × VOUT ESR E × C E × VOUT = = ∆Istep ∆Istep where For example, assume voltage droop during transient τ= ESR E × ∆Istep ...(10) age transient not only dependent on the ESR, but also L EFF = N= if LEFF ≥ Lcrit ger than critical inductance. In that case, the output volt- where L crit 0 if LEFF ≤ Lcrit τ = LEFF × ∆Istep − ESR E × CE V OUT ...(9) N= ESR E ×∆Istep ∆Vtran + VOUT ×τ2 2 × LEFF × CE ×∆Vtran 7mΩ× 30A + 120mV 1.2V × (1.5us)2 2 × 0.34µH×1000µF ×120mV = 1.78 = The number of capacitors has to satisfied both ripple and transient requirement. Overall, we can choose N=2. It should be considered that the proposed equation is based on ideal case, in reality, the droop or overshoot is typically more than the calculation. The equation gives a good start. For more margin, more capacitors have to be chosen after the test. Typically, for high frequency capacitor such as high quality POSCAP especially ceramic capacitor, 20% to 100% (for ceramic) more capacitors have to be chosen since the ESR of capacitors is so low that the PCB parasitic can affect the results tremendously. More capacitors have to be selected to compensate these parasitic parameters. 9 NX2422 Control Loop Compensator Design NX2422 can control and drive two channel synchro- Gain= nous bucks with 180o phase shift between each other. One of two channels is called master, the other is called Fz = slave. They are connected together by sharing the same output capacitors. Voltage loop is designed to regulate ... (11) 1 2 × π × R3 × C1 Fp ≈ output voltage. In order to achieve the current balance in R3 R2 ... (12) 1 2 × π × R 3 × C2 ... (13) these two synchronous buck converters, current loop compensation network is employed to to make sure the currents in slave is following the master. Voltage Loop Compensator Design C2 Vout R2 Fb Due to the double pole generated by LC filter of the power stage, the power system has 180o phase shift , C1 R3 Ve R1 and therefore, is unstable by itself. In order to achieve Vref accurate output voltage and fast transient response,compensator is employed to provide highest possible bandwidth and enough phase margin. Ideally, Figure 3 - Type II compensator the Bode plot of the closed loop system has crossover frequency between 1/10 and 1/5 of the switching frequency, phase margin greater than 50o and the gain crosstors usually decide the compensator type. If electrolytic capacitors are chosen as output capacitors, type II power stage Gain(db) ing 0dB with -20dB/decade. Power stage output capaci- 40dB/decade compensator can be used to compensate the system, because the zero caused by output capacitor ESR is loop gain lower than crossover frequency. Otherwise type III com- 20dB/decade pensator should be chosen. A. Type II compensator design If the electrolytic capacitors are chosen as power stage output capacitors, usually the Type II compensa- compensator Gain tor can be used to compensate the system. Type II compensator can be realized by simple RC circuit without feedback as shown in figure 3. R3 and C1 FZ FLC FESR FO FP introduce a zero to cancel the double pole effect. C2 introduces a pole to suppress the switching noise. The following equations show the compensator pole zero lo- Figure 4 - Bode plot of Type II compensator cation and constant gain. For this type of compensator, FO has to satisfy FLC<FESR<< FO and FO <=1/10~1/5Fs. Here a type II compensator is designed for the case which has six electrolytic capacitors(1800uF, 13mΩ) and Rev.2.1 12/01/08 10 NX2422 two 1.5uH inductors. 1.Calculate the location of LC double pole F LC Sanyo OSCON and POSCAP, the frequency of ESR zero and ESR zero FESR. FLC = caused by output capacitors is higher than the cross- 1 2 ×π× LEFF × COUT 1 = 2 ×π× 0.75uH×10800uF = 1.768kHz FESR = 1 2 × π × ESR × COUT 1 2 × π × 13m Ω × 1800uF = 6.801kHz = 2.Set R2 equal to10kΩ and calculate R1. R1= R 2 × VREF 10k Ω × 0.6V = = 10k Ω VOUT -VREF 1.2V-0.6V 3. Set crossover frequency FO=15kHz. 4.Calculate R3 value by the following equation. R3= B. Type III compensator design For low ESR output capacitors, typically such as V O S C 2 × π × FO × L E F F × × R2 V in ESR 1V 2 × π × 15kHz × 0.75uH = × × 10kΩ 12V 2.16m Ω =27.3kΩ Choose R 3 =27.4kΩ. over frequency. In this case, it is necessary to compensate the system with type III compensator. In design example, six electrolytic capacitors are used as output capacitors. The system is compensated with type III compensator. The following figures and equations show how to realize the this type III compensator with electrolytic capacitors. FZ1 = 1 2 × π × R 4 × C2 ...(14) FZ2 = 1 2 × π × (R 2 + R3 ) × C3 ...(15) FP1 = 1 2 × π × R3 × C3 ...(16) FP2 = 1 ...(17) C × C2 2 × π × R4 × 1 C1 + C2 where FZ1,FZ2,FP1 and FP2 are poles and zeros in the compensator. Zin Zf C1 Vout 5. Calculate C1 by setting compensator zero FZ at 75% of the LC double pole. R3 R2 C1= 1 2 × π × R3 × Fz 1 = 2 × π × 27.4kΩ× 0.75 × 1.768kHz =4.4nF C3 C2 R4 Fb Ve R1 Vref Choose C1=4.7nF. 6. Calculate C 2 by setting compensator pole Fp at half the swithing frequency. C2= Figure 5 - Type III compensator 1 π × R 3 × Fs 1 π × 2 7 .4k Ω × 4 0 0 k H z =30pF = Choose C2=33pF. Rev.2.1 12/01/08 11 NX2422 Gain(db) R1= power stage FLC Choose R1=10kΩ. 40dB/decade 3. Calculate C3 by setting FZ2 = FLC and Fp1 =FESR. C3 = FESR loop gain R 2 × VREF 10k Ω × 0.6V = = 10k Ω VOUT -VREF 1.2V-0.6V 1 1 1 ×( ) 2 × π × R2 Fz2 Fp1 1 1 1 ×( ) 2 × π × 10k Ω 6.1kHz 22.7kHz =1.9nF = 20dB/decade Choose C3=1.8nF. compensator 5. Calculate R 3 by equation (13). R3 = FZ1 FZ2 FP1 FO FP2 Figure 6 - Bode plot of Type III compensator The transfer function of type III compensator 1 2 × π × 22.7kHz × 1.8nF = 3.89k Ω = Choose R3=3.92kΩ. 6. Calculate R4 by choosing FO=40kHz. is given by: (1+ sR4 × C2 ) × [1+ s(R2 + R3 ) × C3 ] Ve 1 = × VOUT sR2 × (C2 + C1) (1+ sR × C2 × C1 ) × 1+ sR × C ( 4 3 3) C2 + C1 Use the same power stage requirement as demo board. The crossover frequency has to be selected as FLC<FESR<FO, and usually FO<=1/10~1/5FS. 1.Calculate the location of LC double pole F LC and ESR zero FESR. FLC = R4 = VOSC 2 × π × FO × LEFF R2 × R3 × × Vin ESR R 2 + R3 1V 2 × π × 40kHz × 0.34uH 10kΩ × 3.92kΩ × × 12V 3.5mΩ 10kΩ + 3.92kΩ =5.73kΩ = Choose R4=5.62kΩ. 7. Calculate C2 with zero Fz1 at 75% of the LC double pole by equation (11). C2 = 1 2 × π × FZ1 × R 4 1 2 × π × 0.75 × 6.1kHz × 5.62k Ω = 6.2nF = 1 2 × π × LEFF × COUT = 1 2 × π × FP1 × C3 1 2 × π × 0.34uH × 2000uF = 6.1kHz Choose C2=6.8nF. 8. Calculate C 1 by equation (14) with pole F p2 at half the switching frequency. FESR = 1 2 × π × ESR × COUT 1 2 × π × 3.5mΩ × 2000uF = 22.7kHz = 2.Set R2 equal to10kΩ. Rev.2.1 12/01/08 C1 = 1 2 × π × R 4 × FP2 1 2 × π × 5.62kΩ × 200kHz = 141pF = Choose C1=150pF. 12 NX2422 Current Loop Compensator Design Power stage Compensation D(s) Master channel 1 Vosc Current Sensing Amplifier Gain d Vin s*L+Req iL s*L+DCR Rs*Cs*s+1 Inductor Current sense Figure 7 - Current loop control diagram VIN master channel DCR L Rs Vbias Cs Rs VIN Slave channel 1 DCR L PWM control logic and driver Ramp for slave channel VOUT Rs Cs Vbias Rs CSCOMP Rcc C1 Slave channel control C2 Slave channel control Slave channel Figure 8 - Function diagram of current loop Rev.2.1 12/01/08 13 NX2422 Inductor Current Sensing racy during the transient if droop function is required. The illustration is shown in the following figure. VIN iL L Control & Driver VOUT Rs Current Sensing Amplifier DCR Rs Cs VS_IL VS_IL----Voltage accross the sensing capacitor Cs Overshoot caused by inductor nonlinearity iL--- inductor current Figure 9 - Inductor current sensing using RC network. The inductor current can be sensed through a RC Output voltage with droop function network as shown above. The advantage of the RC network is the lossless comparing with a resistor in series Droop misbehavoir caused by overshoot of VS_IL with output inductor. The selection of the resistor sensing network is chosen by the following equation: R S × CS = L DCR ...(18) If the above equation is satisfied, the voltage across Figure 10 - Droop accuracy affected by the nonlinearity of inductor. In this case, the sensing resistor has to be chosen the sensing capacitor Cs will be equal to the inductor current times DCR of inductor for all frequency domain. VS _ IL = DCR × iL If the sensing capacitor is chosen CS = 1µF CS must be X7R or COG ceramic capacitor. The sensing resistor is calculated as RS = L DCR × CS For example, for 0.68uH inductor with 1.4mΩ DCR, we have RS = 0.68µH = 486Ω 1.4mΩ × 1µF In most of cases, the selection of sensing resistor based on the above equation will be sufficient. However, for some inductor such as toroid coiled inductor with micrometal, even the product of sensing resistor and capacitor is perfectly match with L/DCR, the voltage across the capacitor still has overshoot due to the nonlinearity of inductor. This will affect the droop accu- Rev.2.1 12/01/08 RS ≥ L DCR × CS to compensate the overshoot. This selection only affects the small signal mode of current loop. For DC accuracy, there is no effect since the DC voltage across the sensing capacitor will equal to the DCR times inductor current at DC load no matter what Rs is. RS value is preferred to be less than 400Ω in NX2422's application, therefore we need to reiterate the calculation, choose CS 2.2uF instead. RS value is finally chosen as 301Ω . Powe dissipation of Rs resistor is calculated as followed: PD (RS ) = (VIN − VOUT )2 V 2 × D + OUT × (1 − D) RS RS (12 V − 1.2V)2 (1.2 V)2 × 0. 1 + × (1 − 0.1) 301Ω 301Ω = 0.04 W = The power rating of Rs should be over 0.04W. 14 NX2422 Current Loop Compensation FP1 = Req 2× π ×L = 7.4mΩ = 1.7kHz 2 × π × 0.68µH The current compensation transfer function is Slave channel power stage -20 dB given as D(s) = Current loop compensation gm × s × ( C1 + C2 ) 1 + s × Rcc × C1 R × C1 × C2 1 + s × cc C1 + C2 It has one zero and one pole. The ideal is to Loop gain for slave channel choose resistor Rcc to achieve desired loop gain such -20dB 0 DB as 50kHz. Rcc can be calculated as -40dB Fp1 Fzc Fo Rcc = Fpc 2 × π × Fo × L × Vosc gm × VIN × K C × DCR ...(19) where Figure 11 - Bode plot of current loop The diagram and bode plot for current loop of KC ≈ 60 ⋅ kΩ = 22.9 2kΩ+ RS through inductor sensing is amplified by current sensing 60kΩ and 2kΩ is the internal resistance for the current sensing amplifier. For fast response, we can set the current loop differential amplifier. The amplified slave current signal cross-over frequency one and half times of voltage loop is compared with the amplified inductor current from cross-over frequency. Since the voltage loop cross-over master channel (channel 1 for NX2422) through a frequency is typically selected as 1/10 of switching fre- transconductance amplifier, the difference between chan- quency, we choose FO=50kHz. NX2422 is shown in above figure. The current signal nel current will change the output of transconductance 2 × π × 50kHz × 0.68µH × 1V = 442Ω 1.6mA / V × 12 V × 22.9 ×1.4mΩ amplifier, which will compare with a internal ramp signal Rcc = and changes the duty cycle of slave channel buck con- Select verter. If the inductor are perfectly matched and the PWM Rcc = 430Ω . controller has no offset, the DC current in slave channel will equal to the DC current of master channel (channel 1) due to the gain of current loop. From the bode plot, the power stage has one pole The selection of capacitor C1 is such that the zero of compensation will cancel the pole of power stage, therefore, C1 = located at FP1 = Req L 0.68µH = = 214nF Req × Rcc 7.4mΩ × 430Ω Typically, the capacitor C1 is so big that the cur- 2×π×L where Req is the equivalent resistor and it is given by rent loop may start slowly during the start up. There- VOUT V + Rdson _ syn × 1 − OUT VIN VIN selected capacitor can not reduce too much to cause R eq ≈ DCR + R dson _ con × R dson _ con is the Rdson of control FET and R dson _ syn is the Rdson of synchronous FET. For this example, Req = 7.4mΩ fore, smaller capacitor can be selected. However, the phase droop. Select C1=220nF. The capacitor C2 is an option and it is used to filter out the switching noise. C2 can be calculated as The pole is located as Rev.2.1 12/01/08 15 NX2422 C2 = 0.2*Iout=0.2*50A=10A. 1 1 = = 1.85nF π × Rcc × FS π × 430Ω × 400kHz A combination of ceramic and electrolytic(SANYO Select C2=2.2nF. WG or WF series) or OSCON type capacitors can Frequency Selection ing enough capacitance such that input voltage will not achieve both ripple current capability together with hav- The frequency can be set by external Rt resistor. sag too much. In this application, one OSCON The relationship between frequency per phase and RT SVPC180M(180uF, 16V, 2.8A) and three 10uF X5R ce- pin around 400kHz is shown as follows. ramic capacitors are selected. RT ≈ A 1uH input inductor is recommended to slow down 40000000 FS the input current transient. Suppose power stage effi- ...(20) ciency is 0.8, then input current can estimated by IINPUT = Frequency(kHz) vsRt(kohm) 1200 In this application, Coilcraft DO3316P_102HC with RMS rating 10A is chosen. 1000 Frequency(kHz) IO U T × VOUT 60 A × 1 . 2 V = = 7 .5 A η × VIN 0 . 8 × 12 V 800 0.5 600 Singlephase 0.4 400 I RMS (IN ) 0.3 Iout 200 0 Two phase 0.2 0 50 100 150 200 250 300 Rt(kohm) 0.1 Three phase Figure 12 - Frequency vs Rt chart 0 Input Filter Selection 0 0.1 0.2 0.4 0.5 D The selection criteria of input capacitor are voltage rating and the RMS current rating. For conservative con- 0.3 Figure 13 - Normalized input RMS current vs. duty cycle sideration, the capacitor voltage rating should be 1.5 times higher than the maximum input voltage. The RMS current rating of the input capacitor for multi-phase converter can be estimated from the above Figure 14. First, determine the duty cycle of the converter (VO/ VIN). The ratio of input RMS current over output current can be obtained. Then the total input RMS current can be calculated. From this figure, it is obvious that a multiphase converter can have a much smaller input RMS current, which results in a lower amount of input capacitors that are required. Over Current/Short Circuit Protection The converter will go into hiccup mode if the output current reaches a programmed limit I OCP determined by the resistor value Rocp at pin IOUT/IMAX. ROCP = 2kΩ + RS 1.25V 2 1 × × × 0.04mA / V 60kΩ DCR IOCP ...(21) Where Iocp is the desired over current protection level, R S is the current sensing matching resistor when For example, Vin=12V, Vout=1.2V. The duty cycle using DCR sensing method. is D=Vout/Vin=1.2/12=10%. From the figure, for two phase, Rev.2.1 12/01/08 the normlized RMS current is 16 NX2422 Over Voltage Protection TSW is the sum of TR and TF which can be found in Over voltage protection is achieved by sensing the mosfet datasheet, IOUT is output current, and FS is switch- output voltage through resistor divider. The sensed volt- ing frequency. Swithing loss PSW is frequency depen- age on FB pin is compared with 130%*VREF to generate dent. the OVP signal. Soft Start and Enable Signal Operation Power MOSFETs Selection The NX2422 requires two N-Channel power MOSFETs for each channels. The selection of MOSFETs is based on maximum drain source voltage, gate source voltage, maximum current rating, MOSFET on resistance and power dissipation. The main consideration is the power loss contribution of MOSFETs to the overall converter efficiency. In this design example, eight NTD60N02 are used. They have the following parameters: VDS=25V, ID =62A,RDSON =12mΩ,QGATE =9nC. There are three factors causing the MOSFET power loss:conduction loss, switching loss and gate driver loss. Gate driver loss is the loss generated by discharging the gate capacitor and is dissipated in driver circuits. It is proportional to frequency and is defined as: Pgate = (QHGATE × VHGS + QLGATE × VLGS ) × FS ...(22) where QHGATE is the high side MOSFETs gate charge,QLGATE is the low side MOSFETs gate charge,VHGS The NX2422's master channel will start operation after 5VCC and REFIN have reached their threshold voltages. Pulling down VCCDRV will cause 5VCC drop below to its threshold, then shuts down NX2422. The slave channel will start operation only when EN2_B is less than 0.8V, 5VCC and REFIN have reached their respective thresholds. For two phase opeartion, EN2_B is preferred to be tied to GND. For one phase opeartion, EN2_B is preferred to be tied to 5VCC. During the operation, it is not recommended to change EN2_B voltage. Once the converter starts, there is a soft start sequence of 1024 steps between 0 and VREF. The ramp rate is determined by the switching frequency. dVO VO = dt 1024 × TS ...(25) Layout Considerations The layout is very important when designing high is the high side gate source voltage, and VLGS is frequency switching converters. Layout will affect noise the low side gate source voltage. This power dissipation pickup and can cause a good design to perform with should not exceed maximum power dissipation of the less than expected results. driver device. There are two sets of components considered in Conduction loss is simply defined as: the layout which are power components and small sig- PHCON =IOUT 2 × D × RDS(ON) × K nal components. Power components usually consist of PLCON =IOUT 2 × (1 − D) × RDS(ON) × K PTOTAL =PHCON + PLCON input capacitors, high-side MOSFET, low-side MOSFET, ...(23) inductor and output capacitors. A noisy environment is generated by the power components due to the switch- Where the RDS(ON) will increases as MOSFET jun- ing power. Small signal components are connected to ction temperature increases, K is RDS(ON) temperature sensitive pins or nodes. A multilayer layout which in- dependency and should be selected for the worst case. cludes power plane, ground plane and signal plane is Conduction loss should not exceed package rating or recommended . Layout guidelines: overall system thermal budget. Switching loss is mainly caused by crossover con- 1. First put all the power components in the top duction at the switching transition. The total switching layer connected by wide, copper filled areas. The input loss can be approximated. 1 PSW = × VIN × IOUT × TSW × FS 2 capacitor, inductor, output capacitor and the MOSFETs Rev.2.1 12/01/08 should be close to each other as possible. This helps to ...(24) reduce the EMI radiated by the power loop due to the 17 NX2422 high switching currents through them. 2. Low ESR capacitor which can handle input RMS ripple current and a high frequency decoupling ceramic cap which usually is 1uF need to be practically touching the drain pin of the upper MOSFET, a plane connection is a must. 3. The output capacitors should be placed as close as to the load as possible and plane connection is required. 4. Drain of the low-side MOSFET and source of the high-side MOSFET need to be connected thru a plane ans as close as possible. A snubber nedds to be placed as close to this junction as possible. 5. Source of the lower MOSFET needs to be connected to the GND plane with multiple vias. One is not enough. This is very important. The same applies to the output capacitors and input capacitors. 6. Hdrv and Ldrv pins should be as close to MOSFET gate as possible. The gate traces should be wide and short. A place for gate drv resistors is needed to fine tune noise if needed. 7. Vcc capacitor, BST capacitor or any other bypassing capacitor needs to be placed first around the IC and as close as possible. The capacitor on comp to GND or comp back to FB needs to be place as close to the pin as well as resistor divider. 8. The output sense line which is sensing output back to the resistor divider should not go through high frequency signals. 9. All GNDs need to go directly thru via to GND plane. 10. The feedback part of the system should be kept away from the inductor and other noise sources, and be placed close to the IC. 11. In multilayer PCB, separate power ground and analog ground. These two grounds must be connected together on the PC board layout at a single point. The goal is to localize the high current path to a separate loop that does not interfere with the more sensitive analog control function. 12. Inductor current sense line should be connected directly to the inductor solder pad. Rev.2.1 12/01/08 18 NX2422 MLPQ 24 PIN 4 x 4 PACKAGE OUTLINE DIMENSIONS NOTE: ALL DIMENSIONS ARE DISPLAYED IN MILLIMETERS. Rev.2.1 12/01/08 19 NX2422 MLPQ 24 PIN 4 x 4 TAPE AND REEL INFORMATION NOTE: 1. R7 = 7 INCH LOCK REEL, R13 = 13 INCH LOCK REEL. 2. ALL DIMENSIONS ARE DISPLAYED IN MILLIMETERS. Rev.2.1 12/01/08 20