TSM1121 3.3V 5V 12V HOUSEKEEPING IC ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Over voltage protection for 3.3V 5V and 12V without external components Under voltage protection for 3.3V 5V and 12V without external components Over voltage protection for -12V or -5V with external components Externally adjustable under voltage blanking during power up Power good input/output Externally adjustable pg delay Fault output Remote output Externally adjustable remote delay Precision voltage reference 2kV ESD protection N DIP14 (Plastic Package) D SO14 (Plastic Micropackage) PIN CONNECTIONS (top view) DESCRIPTION The TSM1121 integrated circuit incorporates all sensing circuitry to regulate and protect from over voltage and under voltage a multiple output power supply (3.3V, 5V and 12V). TSM1121 incorporates all the necessary functions for Housekeeping features which allow safe operation in all conditions, and very high system integration. TSM1121 integrates a precise voltage reference. VS33 1 14 VCC VS5 2 13 FAULT VS12 3 12 PG EP 4 11 TPG PI 5 10 TREM TUV 6 9 REM GND 7 8 VREF APPLICATION ■ PC SMPS triple power line housekeeping ic (3.3V 5V 12V) ORDER CODE Part Number Temperatur e Range TSM1121CN TSM1121CD 0 to 85°C 0 to 85°C Package Marking N D • • TSM1121C M1121 Note: N = Dual in Line Package (DIP) D = Small Outline Package (SO) - also available in Tape & Reel (DT) May 2003 Revision A 1/11 TSM1121 1 Pin Description PIN DESCRIPTION Name Pin # Vcc Gnd 14 7 Vs12 Type Function 3 Power Supply Power Supply Analog Input Positive Power Supply Line Ground Line. 0V Reference For All Voltages Over and Under voltage Sense Input Dedicated to the 12V Line1 Vs5 2 Analog Input Over and Under voltage Sense Input Dedicated to the 5V Line1) Vs33 1 Analog Input Tuv Fault PI 6 13 5 PG 12 Timing Capacitor Open Collector Analog Input Open Collector Tpg 11 REM 9 Trem Vref 10 8 EP 4 Over and Under voltage Sense Input Dedicated to the 3.3V Line1) Adjustable Under voltage Blanking Delay at Power Up (Setting Capacitor) Fault Output. Fault is high when Over or Under Voltage has been Detected Power Good Input. Detection of the Power Conditions Power Good Output. PG output is High when the Power Conditions are OK Adjustable Power Good Delay (Setting Capacitor) Input Remote Control of the Complete System by the Motherboard (µController). Remote is active high. Switch OFF/ON of the Power Supply. Reset of the Complete System after a FAULT Activation. Adjustable Remote Delay (Setting Capacitor). 2.5V Reference for all Voltages Extra Protection Circuit. Can be used for -12V or -5V Over Voltage Protection. Timing Capacitor Logic Input Timing Capacitor Voltage Reference Analog Input 1) Over and Under Voltage Inputs can go higher than Vcc within the allowed Max Rating range ABSOLUTE MAXIMUM RATINGS Symbol Vcc Iout Io VFault Pd Tstg ESD Tuv EP PI PG Tpg REM Trem DC Supply Voltage 1 DC Supply Voltage Output Current Power Good Output current for the Voltage reference Fault Ouput Power Dissipation Storage Temperature Electrostatic Discharge Adjustable Under voltage Blanking At Power UP Extra Protection Power Good Input Power Good Output Adjustable Power Good Delay Remote Control Adjustable Remote Delay Value Unit 25 V 30 20 5 0.7 -55 to 150 2 5 5 5 5 5 5 5 mA mA V W °C kV V V V V V V V Value Unit 4.5 to 24 0 to 85 V °C 1) All voltage values, except differential voltage are with respect to network ground terminal. OPERATING CONDITIONS Symbol Vcc Toper 2/11 Parameter DC Supply Conditions Operating Free Air Temperature Range Electrical Characteristics 2 TSM1121 ELECTRICAL CHARACTERISTICS Tamb = 25°C and Vcc = 17V (unless otherwise specified) Symbol Parameter Test Condition Min Typ Max Unit 3 5 mA 4 4.2 V 6.1 6.4 V 14.2 15 V 2.3 4 10 1.28 100 2.5 4.3 10.8 V V V V µs 300 500 ms Total Current Consumption Icc Vov33 Vov5 Vov12 Vuv33 Vuv5 Vuv12 Vep Tfault Total Supply Current Over Voltage and Under Voltage Protection Over Voltage Sense 3.3V Input can go higher than 3.8 Vcc Over Voltage Sense 5V Input can go higher than 5.8 Vcc Over Voltage Sense12V Input can go higher than 13.4 Vcc Under Voltage Sense 3.3V 2.1 Under Voltage Sense 5V 3.7 Under Voltage Sense 12V 9.2 Extra Over voltage Protection Threshold Fault Delay Before Latching Internally Fixed Delay Under Voltage Blanking During Power Up Tuv Thuv Under Voltage Blanking During Power Up (Vcc rising) Cuv = 2.2µF Adjustable Blanking 100 Blanking Threshold 1.28 V 1.28 V 70 mV Power Good (PG) Vpgth Power Good Voltage Threshold Power Good Voltage Threshold HysterVpghyst esis Low Output Open Collector Saturation Vpgol Voltage High Output Open Collector Leakage Ipgoh Current Tpgr Power Good Output Rise Time Tpgf Power Good Output Fall Time Tpg Power Good Adjustable Delay PIth Power Input Detection Threshold Collector Current = 15mA PG Output = 5V Load Capacitor = 100pF Load Capacitor = 100pF Load Capacitor Cpg=2.2µF 100 1 1 300 1.28 0.4 V 1 µA 500 µs µs ms V Fault Vfaultol Ifaultoh Fault Output Saturation Voltage Level Fault Output Leakage Current Level IFault = 1mA Vfault = 5V 1 1 V µA Remote Control (REM) Vremth Vremih Iremil Trem1 Trem2 Remote ON/OFF Input Voltage Threshold High Input Remote Voltage Low Input Remote Saturation Current Remote Adjustable Delay ON to OFF Load Capacitor Crem=0.1µF Remote Adjustable Delay OFF to ON Load Capacitor Crem=0.1µF 0.7 0.8 3.3 3.4 1 V 0.5 V mA 40 50 60 ms 40 50 60 ms 2.46 2.5 2.54 V 4 10 mV Voltage Reference Vref Regline Regline Internal Voltage Reference Line regulation Io = 0mA Io = 0mA Line regulation 4.5V<Vcc<24V Io = 10mA Regload Load regulation 1 4.5V<Vcc<24V 0<Io<10mA 15 mV 25 mV 1) Do not short circuit the Vref Pin 3/11 TSM1121 Electrical Characteristics Fig. 1: Application Schematic ~ PRIMARY MAIN RECT. CONV. 12V 12V 5V 5V 3.3V 3.3V PWM + OPTO + Vref AUX. Vcc CONV. 5Vstby 5Vstby PWM + OPTO + Vref TSM1121 Over & Undervoltage Protection FAULT PG REM Reference Logic Sequencer Fig. 2: Internal Schematic TO POWER SUPPLY 12V Vs12 5V Vs5 3.3V Vs33 TSM1121 OVP LOGIC UVP SECONDARY HOUSEKEEPING OUTPUT Ep 5V MAIN 3.3V FAULT REM Tpg Vref UV BLANK Vref CONV. Gnd 4/11 PG Trem 12V FROM PI Tuv to MOTHERBOARD Vcc Electrical Characteristics TSM1121 Fig. 3: Detailed Internal Schematic Vcc 14 OVP VS12 3 1k Tfault Vov12 Vref S Q FAULT 13 R 3.47V UVP 1.28V Tuv 6 Vuv12 VS5 2 Cuv Vov5 Trem 10 Trem 3.47V Vref Vuv5 0.8V VS33 1 Crem Rem 9 Pg 12 1.28V Vov33 Vref 3.47V Vuv33 EP 4 Tpg 11 VovEP Cpg 1.25V Vref 8 1.28V VREF TSM1121 Gnd PI 5 7 5/11 TSM1121 Principle of Operation and Application Hints TSM1121: Housekeeping IC. Latch OFF TSM1121 is a one chip solution for all PC SMPS: it integrates on one chip the Housekeeping Circuitry (Over Voltage and Under Voltage protections, with adequate sequencing). The Over Voltage and Under Voltage Circuits outputs are again ORed before activating a latch. When activated, this latch commands the full switch OFF of the three main power lines (3.3V, 5V, 12V) by an external link between the housekeeping and the primary PWM circuits via the main optocoupler or any other device . Note that the Under Voltage Circuit, after Power Up UV blanking, bears no other delay to the latch setting input whereas the Over Voltage circuit bears an additional Tfault delay time. This allows an efficient protection against Output Short Circuit conditions. Triple Power Line Protection The TSM1121 Housekeeping Circuit is dedicated to 3.3V, 5V and 12V power lines protection. It integrates a Precision Voltage Reference, a Triple Over Voltage Protection Circuit and a Triple Under Voltage Protection Circuit as well as all the necessary logic and transient timing management circuits for optimal and secure communication with the motherboard, during start up, switch off and stabilized conditions. Over Voltage Protection The Over Voltage Protection Circuit is made of three comparators with internal voltage thresholds (Vov33, Vov5, Vov12) which do not require any external components for proper operation. The outputs of these three comparators are ORed. Under Voltage Protection The Under Voltage Protection Circuit is made of three comparators with internal voltage thresholds (Vuv33, Vuv5, Vuv12) which do not require any external components for proper operation. The outputs of these three comparators are ORed, and blanked by an internal delay circuitry (Power Up Blanking - Tuv) which can be adjusted with an external capacitor (Cuv). This allows that during power up, the under voltage protection circuit is inhibited. 6/11 Power Good The Over Voltage and Under Voltage Circuits are Ored to switch the Power Good output active (PG) to warn the motherboard that the voltage of at least one of the three power lines is out of range. The PG activation bears an internal Tpg delay circuitry which can be adjusted with an external capacitor (Cpg). Remote Control Thanks to this information link to the motherboard, a resetting signal to the latch is achievable with the Remote pin (REM). When the Remote pin is active, the external Fault link between Housekeeping circuit and the PWM generator is active (high = PWM OFF) and the PG pin is active (high). Note that to reset effectively the latch, a minimum width Remote pulse should be applied thanks to an internal delay circuitry (Trem) which can be adjusted with an external capacitor (Crem). Application Information 3 TSM1121 APPLICATION INFORMATION 1 - Rem On/Off 2 - Pi & Vs5 On/Off Vcc Vcc Gnd Gnd Vs5 Vs5 EP&PI=Vref Pi Rem Rem TRem TRem Fault Trem Trem Fault Tuv Tuv Tpg Tpg Tpg Pg Tpg Pg 7/11 TSM1121 Application Information 3 - OVP Rem On/Off, Tuv start up OK 4 - OVP Rem On/Off, Tuv start up NOK Vcc Vcc Gnd Gnd Vs5 Ovp level Vs5 Uvp level Uvp level EP&PI=Vref EP&PI=Vref Gnd Gnd Rem Rem TRem TRem Tfault Tfault TRem TRem Fault Fault Tuv Tuv Tpg Tpg Pg Pg Tpg 8/11 Ovp level Tuv Application Information TSM1121 Truth Table for OVP and UVP detection EP PI Vsxx Rem Fault PG Power supply state Vref Vref Vref Vref Vref Vref Vref Vref <1.28V Vref Vref Vref Vref Vref Vref Vref Vref Vref <1.28V Vref Vref Vref Vref Vref OK OK OVP on Vsxx OK OK OK OK OK OK OK OK OK 1 0 0 0 1 0 0 0 0 0 1 0 1 0 1 1 1 0 0 0 1 1 1 0 0 1 0 1 0 1 0 1 0 0 0 1 Remote OK OVP detected Fault latched Remote OK UVP detected on PI OK UVP detected on EP Fault latched Remote OK 9/11 TSM1121 4 PACKAGE MECHANICAL DATA PACKAGE MECHANICAL DATA Plastic DIP-14 MECHANICAL DATA mm. inch DIM. MIN. a1 0.51 B 1.39 TYP MAX. MIN. TYP. MAX. 0.020 1.65 0.055 0.065 b 0.5 0.020 b1 0.25 0.010 D 20 0.787 E 8.5 0.335 e 2.54 0.100 e3 15.24 0.600 F 7.1 0.280 I 5.1 0.201 L Z 3.3 1.27 0.130 2.54 0.050 0.100 P001A 10/11 PACKAGE MECHANICAL DATA 5 TSM1121 PACKAGE MECHANICAL DATA SO-14 MECHANICAL DATA DIM. mm. MIN. TYP A a1 inch MAX. MIN. TYP. 1.75 0.1 0.2 b 0.35 b1 0.19 a2 0.068 0.003 0.007 0.46 0.013 0.018 0.25 0.007 1.65 C MAX. 0.064 0.5 0.010 0.019 c1 45˚ (typ.) D 8.55 8.75 0.336 E 5.8 6.2 0.228 e 1.27 e3 0.344 0.244 0.050 7.62 0.300 F 3.8 4.0 0.149 0.157 G 4.6 5.3 0.181 0.208 L 0.5 1.27 0.019 0.050 M S 0.68 0.026 8 ˚ (max.) PO13G Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics © 2003 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom http://www.st.com 11/11