TLV710 Series TLV711 Series www.ti.com SBVS142A – JULY 2010 – REVISED AUGUST 2010 Dual, 200mA, Low-IQ Low-Dropout Regulator for Portable Devices FEATURES DESCRIPTION • Very Low Dropout: – 150mV at IOUT = 200mA and VOUT = 2.8V – 75mV at IOUT = 100mA and VOUT = 2.8V – 40mV at IOUT = 50mA and VOUT = 2.8V 2% Accuracy Over Temperature Low IQ of 35mA per Regulator Multiple Fixed Output Voltage Combinations Possible from 1.2V to 4.8V High PSRR: 70dB at 1kHz Stable with Effective Capacitance of 0.1mF(1) Over-Current and Thermal Protection Dedicated VREF for Each Output Minimizes Crosstalk Available in 1.5mm × 1.5mm SON-6 Package The TLV710 and TLV711 series of dual, low-dropout (LDO) linear regulators are low quiescent current devices with excellent line and load transient performance. These LDOs are designed for power-sensitive applications. These devices provide a typical accuracy of 2% over temperature. See the Input and Output Capacitor Requirements in the Application Information section The TLV710 and TLV711 series are available in a 1.5mm x 1.5mm SON-6 package, and are ideal for handheld applications. 1 2 • • • • • • • • (1) The TLV711 series provides an active pulldown circuit to quickly discharge the outputs. In addition, the TLV711-D series of devices have pull-down resistors at the EN pins. This design helps in disabling the device when the signal-driving EN pins are in a weak, indeterminate state (for example, the GPIO of a processor that might be three-stated during startup). The pull-down resistor pulls the voltage to the EN pins down to 0V, thus disabling the device. APPLICATIONS • • Wireless Handsets, Smart Phones, PDAs MP3 Players and Other Handheld Products TLV710 TLV711 1.5mm x 1.5mm SON-6 (TOP VIEW) EN1 1 6 OUT1 IN 2 5 OUT2 EN2 3 4 GND Typical Application Circuit VIN IN OUT1 EN1 OUT2 ON CIN OFF ON EN2 GND VOUT1 VOUT2 COUT2 1mF Ceramic COUT1 1mF Ceramic OFF 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010, Texas Instruments Incorporated TLV710 Series TLV711 Series SBVS142A – JULY 2010 – REVISED AUGUST 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) VOUT (2) PRODUCT TLV710xxyyqwwwz TLV711xxyyqwwwz (1) (2) XX is nominal output voltage of channel 1 (for example 18 = 1.8V). YY is nominal output voltage of channel 2 (for example 28 = 2.8V). Q is optional. Use "U" for devices with EN pin pull-up resistor, and "D" for devices with EN pin pull-down resistor. WWW is package designator. Z is package quantity. Use "R" for reel (3000 pieces), and "T" for tape (250 pieces). For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the device product folder on www.ti.com. Output voltages from 1.2V to 4.8V in 50mV increments are available through the use of innovative factory OTP programming; minimum order quantities may apply. Contact factory for details and availability. ABSOLUTE MAXIMUM RATINGS (1) At TJ = –40°C to +125°C (unless otherwise noted). VALUE Voltage (2) MIN MAX UNIT IN –0.3 +6.0 V EN –0.3 VIN + 0.3 V –0.3 +6.0 V OUT Current OUT Output short-circuit duration Temperature Internally limited A Indefinite s Operating junction, TJ –55 +150 Storage, Tstg –55 +150 °C 2 kV 500 V Human body model (HBM) QSS 009-105 (JESD22-A114A) Electrostatic Discharge Rating (1) (2) Charged device model (CDM) QSS 009-147 (JESD22-C101B.01) °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability. All voltages with respect to ground. THERMAL INFORMATION (1) TLV710, TLV711 THERMAL METRIC (2) DSE UNITS 6 PINS yJT (1) (2) 2 Junction-to-top characterization parameter 6 °C/W See the Power Dissipation section for more details. For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated TLV710 Series TLV711 Series www.ti.com SBVS142A – JULY 2010 – REVISED AUGUST 2010 ELECTRICAL CHARACTERISTICS At TJ = +25°C, VIN = VOUT(TYP) + 0.5V or 2.0V (whichever is greater), IOUT = 10mA, VEN1 = VEN2 = 0.9V, and COUT1 = COUT2 = 1mF, unless otherwise noted. TLV710, TLV711 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIN Input voltage range 2.0 5.5 VO Output voltage range 1.2 4.8 V VOUT DC output accuracy –40°C ≤ TJ ≤ +125°C –2 +2 % ΔVO/ΔVIN Line regulation VOUT(NOM) + 0.5V ≤ VIN ≤ 5.5V 1 5 mV ΔVO/ΔIOUT Load regulation 0mA ≤ IOUT ≤ 200mA 5 15 mV VIN = 0.98V × VOUT(NOM), IOUT = 200mA, 2V ≤ VOUT < 2.4V 200 285 mV VIN = 0.98V × VOUT(NOM), IOUT = 200mA, 2.4V ≤ VOUT < 2.8V 175 250 mV VIN = 0.98V × VOUT(NOM), IOUT = 200mA, 2.8V ≤ VOUT < 3.3V 150 215 mV VIN = 0.98V × VOUT(NOM), IOUT = 200mA, 3.3V ≤ VOUT ≤ 4.8V 140 200 mV 350 550 mA VDO ICL IQ Dropout voltage Output current limit Quiescent current VOUT = 0.9V × VOUT(NOM) 35 VEN1 = low, VEN2 = high, IOUT2 = 0mA 35 VEN1 = high, VEN2 = high, IOUT = 0mA 70 IGND Ground pin current IOUT1 = IOUT2 = 200mA ISHUTDOWN Shutdown current VEN1,2 ≤ 0.4V, 2.0V ≤ VIN ≤ 4.5V PSRR VOUT = 1.8V dB f = 1kHz 70 dB f = 10kHz 70 dB f = 100kHz 50 dB 48 mVRMS COUT = 1.0mF, IOUT = 200mA Enable high (enabled) VLO Enable low (shutdown) TSD Thermal shutdown temperature mA dB VHI Operating junction temperature 4 75 Startup time (1) TJ µA f = 100Hz tSTR Undervoltage lockout 2.5 µA 80 BW = 100Hz to 100kHz, VOUT = 1.8V UVLO mA 110 f = 10Hz Output noise voltage Enable pin current, enabled mA 360 VN IEN (1) Power-supply rejection ratio 220 VEN1 = high, VEN2 = low, IOUT1 = 0mA V 100 ms 0.9 VIN 0 0.4 TLV710, TLV711 TLV710-D, TLV711-D VIN rising V V 0.04 mA 6 mA 1.9 –40 V +125 °C Shutdown, temperature increasing +165 °C Reset, temperature decreasing +145 °C Startup time = time from EN assertion to 0.98 x VOUT(NOM). Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 3 TLV710 Series TLV711 Series SBVS142A – JULY 2010 – REVISED AUGUST 2010 www.ti.com FUNCTIONAL BLOCK DIAGRAM TLV711 and TLV711-D only 120W Bandgap TLV710-D and TLV711-D only UVLO Current Limit Thermal Shutdown OUT1 Enable and Power Control Logic EN1 EN2 OUT2 150kW Thermal Shutdown IN Current Limit UVLO TLV710-D and TLV711-D only Bandgap 120W TLV711 and TLV711-D only GND 4 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated TLV710 Series TLV711 Series www.ti.com SBVS142A – JULY 2010 – REVISED AUGUST 2010 PIN CONFIGURATION DSE PACKAGE 1.5mm x 1.5mm SON-6 (TOP VIEW) EN1 1 6 OUT1 IN 2 5 OUT2 EN2 3 4 GND PIN DESCRIPTIONS NAME PIN NO. DESCRIPTION EN1 1 Enable pin for regulator 1. Driving EN1 over 0.9V turns on regulator 1. Driving EN below 0.4V puts regulator 1 into shutdown mode. IN 2 Input pin. A small capacitor is needed from this pin to ground to assure stability. See Input and Output Capacitor Requirements in the Application Information section for more details. EN2 3 Enable pin for regulator 2. Driving EN2 over 0.9V turns on regulator 2. Driving EN2 below 0.4V puts regulator2 into shutdown mode. GND 4 Ground pin. OUT2 5 Regulated output voltage pin. A small 1mF ceramic capacitor is needed from this pin to ground to assure stability. See Input and Output Capacitor Requirements in the Application Information section for more details. OUT1 6 Regulated output voltage pin. A small 1mF ceramic capacitor is needed from this pin to ground to assure stability. See Input and Output Capacitor Requirements in the Application Information section for more details. Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 5 TLV710 Series TLV711 Series SBVS142A – JULY 2010 – REVISED AUGUST 2010 www.ti.com TYPICAL CHARACTERISTICS Over operating temperature range of TJ = –40°C to +125°C, VEN1 = VEN2 = VIN, CIN = 1mF, COUT1 = 1mF, and COUT2 = 1mF, unless otherwise noted. Typical values are at TJ = +25°C. LINE REGULATION: VOUT1 LINE REGULATION: VOUT2 (TLV7101828) (TLV7101828) 1.90 2.90 IOUT1 = 10mA IOUT2 = 10mA 1.86 2.86 1.84 2.84 1.82 2.82 1.80 1.78 1.76 1.72 2.72 2.6 3.1 3.6 4.1 VIN (V) 4.6 5.1 3.1 5.6 3.6 4.1 4.6 5.1 5.6 VIN (V) Figure 1. Figure 2. LINE REGULATION: VOUT1 (TLV7101828) LINE REGULATION: VOUT2 (TLV7101828) 1.90 2.90 IOUT1 = 200mA IOUT2 = 0mA 1.88 1.86 2.86 1.84 2.84 1.82 2.82 1.80 1.78 1.76 1.72 2.80 2.78 2.76 +125°C +85°C +25°C -40°C 1.74 IOUT1 = 0mA IOUT2 = 200mA 2.88 VOUT (V) VOUT (V) +125°C +85°C +25°C -40°C 2.70 2.1 +125°C +85°C +25°C -40°C 2.74 2.72 1.70 2.70 2.1 2.6 3.1 3.6 4.1 VIN (V) 4.6 5.1 3.1 5.6 3.6 4.1 4.6 5.1 5.6 VIN (V) Figure 3. Figure 4. LINE REGULATION: VOUT1 (TLV7103333) LINE REGULATION: VOUT2 (TLV7103333) 3.40 3.40 IOUT1 = 10mA IOUT2 = 10mA 3.38 3.36 3.36 3.34 3.34 3.32 3.32 3.30 3.28 3.26 3.22 3.30 3.28 3.26 +125°C +85°C +25°C -40°C 3.24 IOUT1 = 10mA IOUT2 = 10mA 3.38 VOUT (V) VOUT (V) 2.78 2.74 1.70 +125°C +85°C +25°C -40°C 3.24 3.22 3.20 3.20 3.6 3.8 4.0 4.2 4.4 4.6 4.8 VIN (V) Figure 5. 6 2.80 2.76 +125°C +85°C +25°C -40°C 1.74 IOUT1 = 10mA IOUT2 = 10mA 2.88 VOUT (V) VOUT (V) 1.88 Submit Documentation Feedback 5.0 5.2 5.4 5.6 3.6 3.8 4.0 4.2 4.4 4.6 4.8 VIN (V) 5.0 5.2 5.4 5.6 Figure 6. Copyright © 2010, Texas Instruments Incorporated TLV710 Series TLV711 Series www.ti.com SBVS142A – JULY 2010 – REVISED AUGUST 2010 TYPICAL CHARACTERISTICS (continued) Over operating temperature range of TJ = –40°C to +125°C, VEN1 = VEN2 = VIN, CIN = 1mF, COUT1 = 1mF, and COUT2 = 1mF, unless otherwise noted. Typical values are at TJ = +25°C. LINE REGULATION: VOUT1 (TLV7103333) LINE REGULATION: VOUT2 (TLV7103333) 3.40 3.40 IOUT1 = 200mA IOUT2 = 0mA 3.36 3.36 3.34 3.34 3.32 3.32 3.30 3.28 3.26 3.22 +125°C +85°C +25°C -40°C 3.22 3.20 3.6 3.8 4.0 4.2 4.4 4.6 4.8 VIN (V) 5.0 5.2 5.4 3.6 5.6 3.8 4.0 4.2 4.4 4.6 4.8 VIN (V) 5.0 5.2 Figure 7. Figure 8. LINE REGULATION: VOUT1 (TLV7111525) LINE REGULATION: VOUT2 (TLV7111525) 1.60 5.4 5.6 2.60 IOUT1 = 10mA IOUT2 = 10mA 1.58 1.56 2.56 1.54 2.54 1.52 2.52 1.50 1.48 1.46 1.42 2.50 2.48 2.46 +125°C +85°C +25°C -40°C 1.44 IOUT1 = 10mA IOUT2 = 10mA 2.58 VOUT (V) VOUT (V) 3.28 3.24 3.20 +125°C +85°C +25°C -40°C 2.44 2.42 1.40 2.40 2.0 2.5 3.0 3.5 4.0 VIN (V) 4.5 5.0 3.0 5.5 3.5 4.0 4.5 5.0 5.5 VIN (V) Figure 9. Figure 10. LINE REGULATION: VOUT1 (TLV7111525) LINE REGULATION: VOUT2 (TLV7111525) 1.60 2.60 IOUT1 = 200mA IOUT2 = 0mA 1.58 1.56 2.56 1.54 2.54 1.52 2.52 1.50 1.48 1.46 1.42 2.50 2.48 2.46 +125°C +85°C +25°C -40°C 1.44 IOUT1 = 0mA 2.58 VOUT (V) VOUT (V) 3.30 3.26 +125°C +85°C +25°C -40°C 3.24 IOUT1 = 0mA IOUT2 = 200mA 3.38 VOUT (V) VOUT (V) 3.38 +125°C +85°C +25°C -40°C 2.44 2.42 1.40 2.40 2.0 2.5 3.0 3.5 4.0 VIN (V) Figure 11. Copyright © 2010, Texas Instruments Incorporated 4.5 5.0 5.5 3.0 3.5 4.0 4.5 5.0 5.5 VIN (V) Figure 12. Submit Documentation Feedback 7 TLV710 Series TLV711 Series SBVS142A – JULY 2010 – REVISED AUGUST 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) Over operating temperature range of TJ = –40°C to +125°C, VEN1 = VEN2 = VIN, CIN = 1mF, COUT1 = 1mF, and COUT2 = 1mF, unless otherwise noted. Typical values are at TJ = +25°C. LOAD REGULATION: VOUT1 (TLV7101828) LOAD REGULATION: VOUT2 (TLV7101828) 1.90 2.90 VIN = 3.3V 1.86 2.86 1.84 2.84 1.82 2.82 1.80 1.78 1.76 1.72 2.72 20 40 60 80 100 120 140 160 180 200 IOUT (mA) 0 20 40 60 80 100 120 140 160 180 200 IOUT (mA) Figure 13. Figure 14. LOAD REGULATION: VOUT1 (TLV7103333) LOAD REGULATION: VOUT2 (TLV7103333) 3.40 3.40 VIN = 3.8V 3.38 3.36 3.36 3.34 3.34 3.32 3.32 3.30 3.28 3.26 3.22 3.30 3.28 3.26 +125°C +85°C +25°C -40°C 3.24 VIN = 3.8V 3.38 VOUT (V) VOUT (V) +125°C +85°C +25°C -40°C 2.70 0 +125°C +85°C +25°C -40°C 3.24 3.22 3.20 3.20 0 20 40 60 80 100 120 140 160 180 200 IOUT (mA) 0 20 40 60 80 100 120 140 160 180 200 IOUT (mA) Figure 15. Figure 16. LOAD REGULATION: VOUT1 (TLV7111525) LOAD REGULATION: VOUT2 (TLV7111525) 1.60 2.60 VIN = 3.0V 1.58 1.56 2.56 1.54 2.54 1.52 2.52 1.50 1.48 1.46 +125°C +85°C +25°C -40°C 1.44 1.42 1.40 VIN = 3.0V 2.58 VOUT (V) VOUT (V) 2.78 2.74 1.70 2.50 2.48 2.46 +125°C +85°C +25°C -40°C 2.44 2.42 2.40 0 20 40 60 80 100 120 140 160 180 200 IOUT (mA) Figure 17. 8 2.80 2.76 +125°C +85°C +25°C -40°C 1.74 VIN = 3.3V 2.88 VOUT (V) VOUT (V) 1.88 Submit Documentation Feedback 0 20 40 60 80 100 120 140 160 180 200 IOUT (mA) Figure 18. Copyright © 2010, Texas Instruments Incorporated TLV710 Series TLV711 Series www.ti.com SBVS142A – JULY 2010 – REVISED AUGUST 2010 TYPICAL CHARACTERISTICS (continued) Over operating temperature range of TJ = –40°C to +125°C, VEN1 = VEN2 = VIN, CIN = 1mF, COUT1 = 1mF, and COUT2 = 1mF, unless otherwise noted. Typical values are at TJ = +25°C. DROPOUT VOLTAGE vs INPUT VOLTAGE DROPOUT VOLTAGE vs INPUT VOLTAGE 70 120 VOUT1 = VOUT2 = 4.8V IOUT = 50mA 60 VOUT1 = VOUT2 = 4.8V IOUT = 100mA 100 50 VDO (mV) VDO (mV) 80 40 30 60 40 20 +125°C +85°C +25°C -40°C 10 +125°C +85°C +25°C -40°C 20 0 0 2.0 2.4 2.8 3.2 3.6 VIN (V) 4.0 4.4 2.0 4.8 2.4 2.8 3.2 3.6 VIN (V) 4.0 Figure 19. Figure 20. DROPOUT VOLTAGE vs INPUT VOLTAGE DROPOUT VOLTAGE vs INPUT VOLTAGE 180 4.4 4.8 250 VOUT1 = VOUT2 = 4.8V IOUT = 200mA VOUT1 = VOUT2 = 4.8V IOUT = 150mA 160 200 140 VDO (mV) VDO (mV) 120 100 80 150 100 60 +125°C +85°C +25°C -40°C 40 20 0 0 2.0 2.4 2.8 3.2 3.6 VIN (V) 4.0 4.4 2.0 4.8 2.4 2.8 3.2 3.6 VIN (V) 4.0 4.4 4.8 Figure 21. Figure 22. DROPOUT VOLTAGE vs OUTPUT CURRENT: VOUT2 (TLV7101828) DROPOUT VOLTAGE vs OUTPUT CURRENT: VOUT1/VOUT2 (TLV7103333) 200 180 180 160 160 140 140 120 120 VDO (mV) VDO (mV) +125°C +85°C +25°C -40°C 50 100 80 100 80 60 60 +125°C +85°C +25°C -40°C 40 20 0 +125°C +85°C +25°C -40°C 40 20 0 0 20 40 60 80 100 120 140 160 180 200 IOUT (mA) Figure 23. Copyright © 2010, Texas Instruments Incorporated 0 20 40 60 80 100 120 140 160 180 200 IOUT (mA) Figure 24. Submit Documentation Feedback 9 TLV710 Series TLV711 Series SBVS142A – JULY 2010 – REVISED AUGUST 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) Over operating temperature range of TJ = –40°C to +125°C, VEN1 = VEN2 = VIN, CIN = 1mF, COUT1 = 1mF, and COUT2 = 1mF, unless otherwise noted. Typical values are at TJ = +25°C. DROPOUT VOLTAGE vs OUTPUT CURRENT: VOUT2 (TLV7111525) OUTPUT VOLTAGE vs TEMPERATURE: VOUT1 (TLV7101828) 250 1.90 VIN = 3.3V 1.88 200 1.86 VOUT (V) VDO (mV) 1.84 150 100 1.72 20 40 60 80 100 120 140 160 180 200 IOUT (mA) -40 -25 -10 5 20 35 50 65 80 Junction Temperature (°C) 95 110 125 Figure 25. Figure 26. OUTPUT VOLTAGE vs TEMPERATURE: VOUT2 (TLV7101828) OUTPUT VOLTAGE vs TEMPERATURE: VOUT1 (TLV7103333) 2.90 3.40 VIN = 3.3V 2.88 2.86 3.36 2.84 3.34 2.82 3.32 2.80 2.78 VIN = 3.8V 3.38 VOUT (V) VOUT (V) 10mA 150mA 200mA 1.70 0 2.76 3.30 3.28 3.26 10mA 150mA 200mA 2.74 2.72 10mA 150mA 200mA 3.24 3.22 2.70 3.20 -40 -25 -10 5 20 35 50 65 80 Junction Temperature (°C) 95 110 125 -40 -25 -10 5 20 35 50 65 80 Junction Temperature (°C) 95 110 125 Figure 27. Figure 28. OUTPUT VOLTAGE vs TEMPERATURE: VOUT2 (TLV7103333) OUTPUT VOLTAGE vs TEMPERATURE: VOUT1 (TLV7111525) 3.40 1.60 VIN = 3.8V 3.38 3.36 1.56 3.34 1.54 3.32 1.52 3.30 3.28 3.26 VIN = 3.0V 1.58 VOUT (V) VOUT (V) 1.78 1.74 0 1.50 1.48 1.46 10mA 150mA 200mA 3.24 3.22 3.20 10mA 150mA 200mA 1.44 1.42 1.40 -40 -25 -10 5 20 35 50 65 80 Junction Temperature (°C) Figure 29. 10 1.80 1.76 +125°C +85°C +25°C -40°C 50 1.82 Submit Documentation Feedback 95 110 125 -40 -25 -10 5 20 35 50 65 80 Junction Temperature (°C) 95 110 125 Figure 30. Copyright © 2010, Texas Instruments Incorporated TLV710 Series TLV711 Series www.ti.com SBVS142A – JULY 2010 – REVISED AUGUST 2010 TYPICAL CHARACTERISTICS (continued) Over operating temperature range of TJ = –40°C to +125°C, VEN1 = VEN2 = VIN, CIN = 1mF, COUT1 = 1mF, and COUT2 = 1mF, unless otherwise noted. Typical values are at TJ = +25°C. OUTPUT VOLTAGE vs TEMPERATURE: VOUT2 (TLV7111525) GROUND PIN CURRENT vs INPUT VOLTAGE: IQ1 (TLV7101828) 50 2.60 2.56 40 2.54 35 2.52 30 2.50 2.48 10mA 150mA 200mA 2.44 2.42 20 +125°C +85°C +25°C -40°C 10 5 0 2.40 -40 -25 -10 5 20 35 50 65 80 Junction Temperature (°C) 95 2.1 110 125 2.6 3.1 3.6 4.1 VIN (V) 4.6 5.1 5.6 Figure 31. Figure 32. GROUND PIN CURRENT vs INPUT VOLTAGE: IQ2 (TLV7101828) GROUND PIN CURRENT vs INPUT VOLTAGE: IQ1 (TLV7103333) 50 50 45 45 40 40 35 35 30 30 IGND (mA) IGND (mA) 25 15 2.46 25 20 15 5 25 20 15 +125°C +85°C +25°C -40°C 10 +125°C +85°C +25°C -40°C 10 5 0 0 3.1 3.6 4.1 4.6 5.1 3.6 5.6 4.0 4.4 4.8 5.2 5.6 VIN (V) VIN (V) Figure 33. Figure 34. GROUND PIN CURRENT vs INPUT VOLTAGE: IQ2 (TLV7103333) GROUND PIN CURRENT vs INPUT VOLTAGE: IQ1 (TLV7111525) 50 50 45 45 40 40 35 35 30 30 IGND (mA) IGND (mA) VIN = 3.3V 45 VIN = 3.0V IGND (mA) VOUT (V) 2.58 25 20 15 5 20 15 +125°C +85°C +25°C -40°C 10 25 +125°C +85°C +25°C -40°C 10 5 0 0 3.6 4.0 4.4 4.8 VIN (V) 3.6 4.1 VIN (V) Figure 35. Figure 36. Copyright © 2010, Texas Instruments Incorporated 5.2 5.6 2.1 2.6 3.1 4.6 5.1 Submit Documentation Feedback 5.6 11 TLV710 Series TLV711 Series SBVS142A – JULY 2010 – REVISED AUGUST 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) Over operating temperature range of TJ = –40°C to +125°C, VEN1 = VEN2 = VIN, CIN = 1mF, COUT1 = 1mF, and COUT2 = 1mF, unless otherwise noted. Typical values are at TJ = +25°C. GROUND PIN CURRENT vs INPUT VOLTAGE: IQ2 (TLV7111525) GROUND PIN CURRENT vs LOAD: IQ1 (TLV7101828) 350 50 VIN = 3.3V 45 300 40 250 30 IGND (mA) IGND (mA) 35 25 20 15 5 150 100 +125°C +85°C +25°C -40°C 10 200 +125°C +85°C +25°C -40°C 50 0 0 2.8 3.2 3.6 4.0 4.4 VIN (V) 4.8 5.2 0 5.6 20 40 60 80 100 120 140 160 180 200 IOUT (mA) Figure 37. Figure 38. GROUND PIN CURRENT vs LOAD: IQ2 (TLV7103333) GROUND PIN CURRENT vs LOAD: IQ1 (TLV7111525) 350 350 VIN = 3.0V 300 300 250 250 IGND (mA) IGND (mA) VIN = 3.8V 200 150 100 0 0 20 40 60 80 100 120 140 160 180 200 IOUT (mA) 0 20 40 60 80 100 120 140 160 180 200 IOUT (mA) Figure 39. Figure 40. SHUTDOWN CURRENT vs INPUT VOLTAGE (TLV7101828) SHUTDOWN CURRENT vs INPUT VOLTAGE (TLV7103333) 4.0 4.0 3.5 3.5 3.0 3.0 2.5 2.5 ISHDN (mA) ISHDN (mA) +125°C +85°C +25°C -40°C 50 0 2.0 1.5 +125°C +85°C +25°C -40°C 1.0 5 2.0 1.5 +125°C +85°C +25°C -40°C 1.0 5 0 0 2.0 2.5 3.0 3.5 4.0 VIN (V) Figure 41. 12 150 100 +125°C +85°C +25°C -40°C 50 200 Submit Documentation Feedback 4.5 5.0 5.5 2.0 2.5 3.0 3.5 4.0 VIN (V) 4.5 5.0 5.5 Figure 42. Copyright © 2010, Texas Instruments Incorporated TLV710 Series TLV711 Series www.ti.com SBVS142A – JULY 2010 – REVISED AUGUST 2010 TYPICAL CHARACTERISTICS (continued) Over operating temperature range of TJ = –40°C to +125°C, VEN1 = VEN2 = VIN, CIN = 1mF, COUT1 = 1mF, and COUT2 = 1mF, unless otherwise noted. Typical values are at TJ = +25°C. SHUTDOWN CURRENT vs INPUT VOLTAGE (TLV7111525) CURRENT LIMIT vs INPUT VOLTAGE: ICL1 (TLV7101828) 4.0 500 3.5 480 +125°C +85°C +25°C -40°C 460 3.0 ILIM (mA) ISHDN (mA) 440 2.5 2.0 1.5 5 380 340 320 300 0 2.0 2.5 3.0 3.5 4.0 VIN (V) 4.5 5.0 2.1 5.5 2.6 3.1 4.6 5.1 Figure 44. CURRENT LIMIT vs INPUT VOLTAGE: ICL2 (TLV7101828) CURRENT LIMIT vs INPUT VOLTAGE: ICL1 (TLV7103333) 5.6 500 +125°C +85°C +25°C -40°C 480 460 440 +125°C +85°C +25°C -40°C 480 460 440 ILIM (mA) 420 400 380 420 400 380 360 360 340 340 320 320 300 300 3.1 3.6 4.1 4.6 5.1 3.6 5.6 4.0 4.4 VIN (V) 4.8 5.2 5.6 VIN (V) Figure 45. Figure 46. CURRENT LIMIT vs INPUT VOLTAGE: ICL2 (TLV7103333) CURRENT LIMIT vs INPUT VOLTAGE: ICL1 (TLV7111525) 500 500 +125°C +85°C +25°C -40°C 480 460 440 +125°C +85°C +25°C -40°C 480 460 440 420 ILIM (mA) ILIM (mA) 3.6 4.1 VIN (V) Figure 43. 500 ILIM (mA) 400 360 +125°C +85°C +25°C -40°C 1.0 420 400 380 420 400 380 360 360 340 340 320 320 300 300 3.6 4.0 4.4 4.8 VIN (V) Figure 47. Copyright © 2010, Texas Instruments Incorporated 5.2 5.6 2.8 3.1 3.4 3.7 4.0 4.3 VIN (V) 4.6 4.9 5.2 5.5 Figure 48. Submit Documentation Feedback 13 TLV710 Series TLV711 Series SBVS142A – JULY 2010 – REVISED AUGUST 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) Over operating temperature range of TJ = –40°C to +125°C, VEN1 = VEN2 = VIN, CIN = 1mF, COUT1 = 1mF, and COUT2 = 1mF, unless otherwise noted. Typical values are at TJ = +25°C. CURRENT LIMIT vs INPUT VOLTAGE: ICL2 (TLV7111525) 500 +125°C +85°C +25°C -40°C 480 460 ILIM (mA) 440 420 400 380 360 340 320 300 2.8 3.1 3.4 3.7 4.0 4.3 VIN (V) 4.6 4.9 5.2 5.5 Figure 49. POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY (TLV7101828) POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY (TLV7103333) 100 100 90 IOUT2 = 30mA 80 IOUT1 = 30mA VIN = 3.3V VOUT = 2.8V PSRR (dB) PSRR (dB) 70 60 IOUT2 = 150mA 50 40 60 IOUT2 = 150mA 50 40 30 30 20 20 10 10 0 0 10 100 1k 10k 100k Frequency (Hz) 1M 10M 10 100 1k 10k 100k Frequency (Hz) 1M Figure 51. POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY (TLV7111525) OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY (TLV7101828) 90 IOUT1 = 30mA VIN = 3.0V VOUT = 2.5V IOUT2 = 30mA 80 70 IOUT2 = 150mA 60 50 40 30 20 10 0 10 100 1k 10k 100k Frequency (Hz) Figure 52. Submit Documentation Feedback 1M 10M Output Spectral Noise Density (mV/ÖHz) Figure 50. 100 PSRR (dB) IOUT1 = 30mA VIN = 3.8V VOUT = 3.3V 80 70 14 IOUT2 = 30mA 90 10M 10 VIN = 3.3V VOUT2 = 2.8V IOUT2 = 30mA 1 0.1 0.01 0.001 10 100 1k 10k 100k Frequency (Hz) 1M 10M Figure 53. Copyright © 2010, Texas Instruments Incorporated TLV710 Series TLV711 Series www.ti.com SBVS142A – JULY 2010 – REVISED AUGUST 2010 TYPICAL CHARACTERISTICS (continued) Over operating temperature range of TJ = –40°C to +125°C, VEN1 = VEN2 = VIN, CIN = 1mF, COUT1 = 1mF, and COUT2 = 1mF, unless otherwise noted. Typical values are at TJ = +25°C. OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY (TLV7111525) 10 VIN = 3.8V VOUT2 = 3.3V IOUT2 = 30mA 1 0.1 0.01 0.001 10 100 1k 10k 100k Frequency (Hz) 1M 10M Output Spectral Noise Density (mV/ÖHz) Output Spectral Noise Density (mV/ÖHz) OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY (TLV7103333) 10 VIN = 3.0V VOUT1 = 1.5V IOUT1 = 30mA 1 0.1 0.01 0.001 10 100 1k 10k 100k Frequency (Hz) Figure 54. Figure 55. LINE TRANSIENT RESPONSE VOUT1 = 1.2V, VOUT2 = 1.2V LINE TRANSIENT RESPONSE VOUT1 = 1.2V, VOUT2 = 1.2V Slew Rate = 1V/ms IOUT = 30mA 3.0V VIN 10M Slew Rate = 1V/ms IOUT = 30mA 5.5V 1V/div 2.0V 1M 2.0V 2V/div VIN 5mV/div 5mV/div VOUT1 5mV/div VOUT1 VOUT2 5mV/div VOUT2 Time (200ms/div) Time (200ms/div) Figure 56. Figure 57. LINE TRANSIENT RESPONSE VOUT1 = 1.8V, VOUT2 = 2.8V LINE TRANSIENT RESPONSE VOUT1 = 1.8V, VOUT2 = 2.8V 5.5V Slew Rate = 1V/ms IOUT = 30mA 4.3V 3.3V 1V/div VIN Slew Rate = 1V/ms IOUT = 30mA 3.3V 1V/div VIN 5mV/div VOUT1 5mV/div VOUT1 5mV/div VOUT2 5mV/div VOUT2 Time (200ms/div) Figure 58. Copyright © 2010, Texas Instruments Incorporated Time (200ms/div) Figure 59. Submit Documentation Feedback 15 TLV710 Series TLV711 Series SBVS142A – JULY 2010 – REVISED AUGUST 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) Over operating temperature range of TJ = –40°C to +125°C, VEN1 = VEN2 = VIN, CIN = 1mF, COUT1 = 1mF, and COUT2 = 1mF, unless otherwise noted. Typical values are at TJ = +25°C. LINE TRANSIENT RESPONSE VOUT1 = 4.8V, VOUT2 = 4.8V Slew Rate = 1V/ms IOUT = 30mA 5.5V 5.3V 1V/div VIN 5mV/div VOUT1 5mV/div VOUT2 Time (200ms/div) Figure 60. LOAD TRANSIENT RESPONSE AND CROSSTALK VOUT1 = 1.2V, VOUT2 = 1.2V 200mA 100mA/div LOAD TRANSIENT RESPONSE AND CROSSTALK VOUT1 = 1.2V, VOUT2 = 1.2V Slew Rate = 1V/ms VIN = 2.0V 0mA IOUT1 Slew Rate = 1V/ms VIN = 2.0V 200mA 50mA 100mA/div IOUT1 50mV/div VOUT1 50mV/div VOUT1 10mV/div VOUT2 10mV/div VOUT2 Time (50ms/div) Time (50ms/div) Figure 61. Figure 62. LOAD TRANSIENT RESPONSE AND CROSSTALK VOUT1 = 1.8V, VOUT2 = 2.8V LOAD TRANSIENT RESPONSE AND CROSSTALK VOUT1 = 1.8V, VOUT2 = 2.8V 200mA 200mA Slew Rate = 1V/ms VIN = 3.3V 100mA/div 100mA/div 0mA IOUT2 VOUT1 50mV/div Slew Rate = 1V/ms VIN = 3.3V IOUT2 50mA 20mV/div VOUT2 5mV/div VOUT1 VOUT2 50mV/div Time (50ms/div) Figure 63. 16 Submit Documentation Feedback Time (50ms/div) Figure 64. Copyright © 2010, Texas Instruments Incorporated TLV710 Series TLV711 Series www.ti.com SBVS142A – JULY 2010 – REVISED AUGUST 2010 TYPICAL CHARACTERISTICS (continued) Over operating temperature range of TJ = –40°C to +125°C, VEN1 = VEN2 = VIN, CIN = 1mF, COUT1 = 1mF, and COUT2 = 1mF, unless otherwise noted. Typical values are at TJ = +25°C. LOAD TRANSIENT RESPONSE AND CROSSTALK VOUT1 = 4.8V, VOUT2 = 4.8V LOAD TRANSIENT RESPONSE AND CROSSTALK VOUT1 = 4.8V, VOUT2 = 4.8V Slew Rate = 1V/ms VIN = 5.3V 200mA 200mA 100mA/div IOUT1 0mA 50mV/div 50mA/div VOUT1 VOUT2 5mV/div Slew Rate = 1V/ms VIN = 5.3V 50mA IOUT1 50mV/div VOUT1 5mV/div VOUT2 Time (50ms/div) Time (50ms/div) Figure 65. Figure 66. VIN RAMP UP, RAMP DOWN RESPONSE VOUT1 = 1.2V, VOUT2 = 1.2V VIN RAMP UP, RAMP DOWN RESPONSE VOUT1 = 1.8V, VOUT2 = 2.8V IOUT = 30mA IOUT = 30mA VIN/VEN VIN/VEN 1V/div 1V/div VOUT2 VOUT1 VOUT1/VOUT2 Time (200ms/div) Time (200ms/div) Figure 67. Figure 68. VIN RAMP UP, RAMP DOWN RESPONSE VOUT1 = 4.8V, VOUT2 = 4.8V IOUT = 30mA VIN/VEN 1V/div VOUT1/VOUT2 Time (200ms/div) Figure 69. Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 17 TLV710 Series TLV711 Series SBVS142A – JULY 2010 – REVISED AUGUST 2010 www.ti.com APPLICATION INFORMATION The TLV710 and TLV711 series of devices belong to a new family of next generation, value LDO regulators. These devices consume low quiescent current and deliver excellent line and load transient performance. These features, combined with low noise, very good PSRR with little (VIN to VOUT) headroom, make these devices ideal for RF portable applications. This family of LDO regulators offers current limit and thermal protection, and is specified from –40°C to +125°C. INPUT AND OUTPUT CAPACITOR REQUIREMENTS 1.0mF X5R- and X7R-type ceramic capacitors are recommended because they have minimal variation in value and equivalent series resistance (ESR) over temperature. However, the TLV710 and TLV711 are designed to be stable with an effective capacitance of 0.1mF or larger at the output. Thus, the device would also be stable with capacitors of other dielectrics, as long as the effective capacitance under operating bias voltage and temperature is greater than 0.1mF. This effective capacitance refers to the capacitance that the device sees under operating bias voltage and temperature conditions (that is, the capacitance after taking bias voltage and temperature derating into consideration.) In addition to allowing the use of cost-effective dielectrics, these devices also enable using smaller footprint capacitors that have a higher derating in size-constrained applications. Note that using a 0.1mF rating capacitor at the output of the LDO regulator does not ensure stability because the effective capacitance under operating conditions would be less than 0.1mF. The maximum ESR should be less than 200mΩ. Although an input capacitor is not required for stability, it is good analog design practice to connect a 0.1mF to 1.0mF low ESR capacitor across the IN and GND pins of the regulator. This capacitor counteracts reactive input sources and improves transient response, noise rejection, and ripple rejection. A higher-value capacitor may be necessary if large, fast-rise-time load transients are anticipated, or if the device is not located near the power source. If source impedance is more than 2Ω, a 0.1mF input capacitor may be necessary to ensure stability. BOARD LAYOUT RECOMMENDATIONS TO IMPROVE PSRR AND NOISE PERFORMANCE Input and output capacitors should be placed as close to the device pins as possible. To improve ac performance such as PSRR, output noise, and transient response, it is recommended that the board be designed with separate ground planes for VIN and VOUT, with the ground plane connected only at the GND pin of the device. In addition, the ground connection for the output capacitor should be connected directly to the GND pin of the device. High ESR capacitors may degrade PSRR. INTERNAL CURRENT LIMIT The TLV710 and TLV711 internal current limits help protect the regulator during fault conditions. During current limit, the output sources a fixed amount of current that is largely independent of output voltage. In such a case, the output voltage is not regulated, and is VOUT = ILIMIT × RLOAD. The PMOS pass transistor dissipates (VIN – VOUT) × ILIMIT until thermal shutdown is triggered and the device is turned off. As the device cools down, it is turned on by the internal thermal shutdown circuit. If the fault condition continues, the device cycles between current limit and thermal shutdown. See the Thermal Information section for more details. The PMOS pass element in the TLV710 and TLV711 has a built-in body diode that conducts current when the voltage at OUT exceeds the voltage at IN. This current is not limited, so if extended reverse voltage operation is anticipated, external limiting to 5% of rated output current is recommended. SHUTDOWN The enable pin (EN) is active high. The device is enabled when EN pin goes above 0.9V. This relatively lower value of voltage needed to turn the LDO regulator on can be used to enable the device with the GPIO of recent processors whose GPIO voltage is lower than traditional microcontrollers. The device is turned off when the EN pin is held at less than 0.4V. When shutdown capability is not required, the EN pin can connected to the IN pin. The TLV711 has internal pull-down circuitry that discharges output with a time constant of: 120 · RL t= · COUT 120 + RL Where: RL = load resistance COUT = output capacitor 18 Submit Documentation Feedback (1) Copyright © 2010, Texas Instruments Incorporated TLV710 Series TLV711 Series www.ti.com SBVS142A – JULY 2010 – REVISED AUGUST 2010 DROPOUT VOLTAGE The TLV710 and TLV711 use a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout voltage (VDO), the PMOS pass device is in the linear region of operation and the input-to-output resistance is the RDS(ON) of the PMOS pass element. VDO scales approximately with the output current because the PMOS device behaves as a resistor in dropout. use worst-case loads and signal conditions. For good reliability, thermal protection should trigger at least +35°C above the maximum expected ambient condition of the particular application. This configuration produces a worst-case junction temperature of +125°C at the highest expected ambient temperature and worst-case load. As with any linear regulator, PSRR and transient response are degraded as (VIN – VOUT) approaches dropout. The internal protection circuitry of the TLV710 and TLV711 has been designed to protect against overload conditions. It was not intended to replace proper heatsinking. Continuously running the TLV710/ TLV711 into thermal shutdown degrades device reliability. TRANSIENT RESPONSE POWER DISSIPATION As with any regulator, increasing the size of the output capacitor reduces over/undershoot magnitude but increases duration of the transient response. The ability to remove heat from a die is different for each package type, presenting different considerations in the printed circuit board (PCB) layout. The PCB area around the device that is free of other components moves the heat from the device to the ambient air. The TLV710 and TLV711 each have a dedicated VREF. Consequently, crosstalk from one channel to the other as a result of transients is close to 0V. UNDERVOLTAGE LOCKOUT (UVLO) The TLV710 and TLV711 use an undervoltage lockout circuit to keep the output shut off until the internal circuitry is operating properly. THERMAL INFORMATION Thermal protection disables the output when the junction temperature rises to approximately +165°C, allowing the device to cool. When the junction temperature cools to approximately +145°C, the output circuitry is again enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage as a result of overheating. Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate heatsink. For reliable operation, junction temperature should be limited to +125°C maximum. To estimate the margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal protection is triggered; Performance data for the TLV710 evaluation module (EVM) are shown in Table 1. The EVM is a 2-layer board with 2 ounces of copper per side. The dimension and layout are shown in Figure 70 and Figure 71. Using heavier copper increases the effectiveness of removing heat from the device. The addition of plated through-holes in the heat-dissipating layer also improves the heatsink effectiveness. Power dissipation depends on input voltage and load conditions. Power dissipation (PD) is equal to the product of the output current and the voltage drop across the output pass element, as shown in Equation 2: PD = (VIN – VOUT) × IOUT (2) PACKAGE MOUNTING Solder pad footprint recommendations for the TLV710 and TLV711 are available from the Texas Instruments Web site at www.ti.com. The recommended land pattern for the DSE (SON-6) package is shown in Figure 72. Table 1. TLV710 EVM Dissipation Ratings PACKAGE RqJA TA < +25°C TA = +70°C TA = +85°C DSE 170°C/W 585mW 320mW 235mW Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 19 TLV710 Series TLV711 Series SBVS142A – JULY 2010 – REVISED AUGUST 2010 www.ti.com 33mm 27mm Figure 70. Top Layer 33mm 27mm Figure 71. Bottom Layer 20 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated TLV710 Series TLV711 Series www.ti.com SBVS142A – JULY 2010 – REVISED AUGUST 2010 Figure 72. Land Pattern Drawing for DSE (SON-6) Package Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 21 PACKAGE OPTION ADDENDUM www.ti.com 28-Aug-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) TLV7101828DSER ACTIVE WSON DSE 6 3000 TBD Call TI Call TI Purchase Samples TLV7101828DSET ACTIVE WSON DSE 6 250 TBD Call TI Call TI Purchase Samples TLV7113333DSER PREVIEW WSON DSE 6 3000 TBD Call TI Call TI Samples Not Available TLV7113333DSET PREVIEW WSON DSE 6 250 TBD Call TI Call TI Samples Not Available (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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