SCAS241A − MARCH 1990 − REVISED APRIL 1996
D Members of the Texas Instruments
D
D
D
D
D
D
D
54AC16646 . . . WD PACKAGE
74AC16646 . . . DL PACKAGE
(TOP VIEW)
Widebust Family
Independent Registers for A and B Buses
Multiplexed Real-Time and Stored Data
Flow-Through Architecture Optimizes
PCB Layout
Distributed VCC and GND Pin Configurations
Minimize High-Speed Switching Noise
EPICt (Enhanced-Performance Implanted
CMOS) 1-mm Process
500-mA Typical Latch-Up Immunity at
125°C
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Packages Using
25-mil Center-to-Center Pin Spacings and
380-mil Fine-Pitch Ceramic Flat (WD)
Packages Using 25-mil Center-to-Center
Pin Spacings
1DIR
1CLKAB
1SAB
GND
1A1
1A2
VCC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
VCC
2A7
2A8
GND
2SAB
2CLKAB
2DIR
description
The ’AC16646 are 16-bit bus transceivers that
consist of D-type flip-flops and control circuitry,
with 3-state outputs arranged for multiplexed
transmission of data directly from the data bus or
from the internal storage registers. The devices
can be used as two 8-bit transceivers or one 16-bit
transceiver. Data on the A or B bus is clocked into
the registers on the low-to-high transition of the
appropriate clock (CLKAB or CLKBA) input.
Figure 1 illustrates the four fundamental
bus-management functions that can be
performed with the bus transceivers and
registers.
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
1OE
1CLKBA
1SBA
GND
1B1
1B2
VCC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
VCC
2B7
2B8
GND
2SBA
2CLKBA
2OE
Output-enable (OE) and direction-control (DIR) inputs are provided to control the transceiver functions. In the
transceiver mode, data present at the high-impedance port may be stored in either register or in both. The select
controls (SAB and SBA) can multiplex stored and real-time (transparent mode) data. The circuitry used for
select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between
stored and real-time data. DIR determines which bus receives data when OE is active (low). In the isolation
mode (OE high), A data may be stored in one register and/or B data may be stored in the other register.
When an output function is disabled, the input function is still enabled and may be used to store and transmit
data. Only one of the two buses, A or B, may be driven at a time.
The 74AC16646 is packaged in the TI shrink small-outline package, which provides twice the functionality of
standard small-outline packages in the same printed-circuit-board area.
The 54AC16646 is characterized for operation over the full military temperature range of −55°C to 125°C. The
74AC16646 is characterized for operation from −40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
Copyright 1996, Texas Instruments Incorporated
!"#$%& "!&'& &(!)$'!& "#))%& ' !( *#+,"'!& '%- )!#" "!&(!)$ !
*%"("'!& *%) % %)$ !( %.' &)#$%& '&') /'))'&0)!#"!& *)!"%&1 !% &! &%"%'),0 &",#% %&1 !( ',,
*')'$%%)-
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•
1
OE
L
DIR
L
CLKAB CLKBA
X
X
SAB
X
BUS B
BUS A
BUS A
BUS B
SCAS241A − MARCH 1990 − REVISED APRIL 1996
SBA
L
OE
L
DIR
H
DIR
X
X
X
CLKAB CLKBA
↑
X
↑
X
↑
↑
SAB
SBA
X
X
X
X
X
X
OE
L
L
STORAGE FROM
A, B, OR A AND B
SBA
X
BUS B
DIR
L
H
CLKAB
X
H or L
CLKBA
H or L
X
SAB
X
H
TRANSFER STORED DATA
TO A AND/OR B
Figure 1. Bus-Management Functions
2
SAB
L
BUS A
BUS A
OE
X
X
H
CLKBA
X
REAL-TIME TRANSFER
BUS A TO BUS B
BUS B
REAL-TIME TRANSFER
BUS B TO BUS A
CLKAB
X
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•
SBA
H
X
SCAS241A − MARCH 1990 − REVISED APRIL 1996
FUNCTION TABLE
DATA I/O†
INPUTS
OE
DIR
CLKAB
CLKBA
SAB
SBA
A1−A8
B1−B8
X
X
↑
X
X
X
Input
Unspecified
OPERATION OR FUNCTION
X
X
X
↑
X
X
Unspecified
Input
Store A, B unspecified{
Store B, A unspecified{
H
X
↑
↑
X
X
Input
Input
Store A and B data
H
X
H or L
H or L
X
X
Input
Input
Isolation, hold storage
L
L
X
X
X
L
Output
Input
Real-time B data to A bus
L
L
X
H or L
X
H
Output
Input
Stored B data to A bus
L
H
X
X
L
X
Input
Output
Real-time A data to B Bus
L
H
H or L
X
H
X
Input
Output
Stored A data to bus
† The data-output functions may be enabled or disabled by various signals at OE or DIR. Data-input functions are always enabled, i.e., data at
the bus terminals is stored on every low-to-high transition of the clock inputs.
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3
SCAS241A − MARCH 1990 − REVISED APRIL 1996
logic symbol†
1OE
1DIR
1CLKBA
1SBA
1CLKAB
1SAB
2OE
2DIR
2CLKBA
2SBA
2CLKAB
2SAB
1A1
56
1
55
54
2
3
29
28
30
31
27
26
G3
3 EN1 [BA]
3 EN2 [AB]
C4
G5
C6
G7
G10
10 EN8 [BA]
10 EN9 [AB]
C11
G12
C13
G14
≥1
5
1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2A1
≥1
7
1
7
8
49
9
48
10
47
12
45
13
44
14
43
15
2A3
2A4
2A5
2A6
2A7
2A8
16
≥1
8
12 11D
42
≥1
1 14
1B3
1B4
1B5
1B6
1B7
1B8
2B1
9
41
17
40
19
38
20
37
21
36
23
34
24
33
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•
1B2
12 1
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
4
1B1
2
51
13D 14
2A2
52
5 1
6D
6
4D
5
2B2
2B3
2B4
2B5
2B6
2B7
2B8
SCAS241A − MARCH 1990 − REVISED APRIL 1996
logic diagram (positive logic)
1OE
56
1
1DIR
55
1CLKBA
54
1SBA
2
1CLKAB
3
1SAB
TG
1A1
5
C1
1D
TG
C1
1D
TG
52
B1
TG
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2OE
2DIR
2CLKBA
2SBA
2CLKAB
2SAB
6
8
9
10
12
13
14
51
49
48
47
45
44
43
Seven Channels Identical
to Channel One Above
B2
B3
B4
B5
B6
B7
B8
29
28
30
31
27
26
TG
15
C1
1D
2A1
TG
C1
1D
TG
42
B1
TG
2A2
2A3
2A4
2A5
2A6
2A7
2A8
16
17
19
20
21
23
24
Seven Channels Identical
to Channel One Above
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•
41
40
38
37
36
34
33
B2
B3
B4
B5
B6
B7
B8
5
SCAS241A − MARCH 1990 − REVISED APRIL 1996
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, IO (VO = 0 to VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±400 mA
Maximum power dissipation at TA = 55°C (in still air) (see Note 2): DL package . . . . . . . . . . . . . . . . . . . 1.4 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils.
recommended operating conditions
54AC16646
VCC
VIH
Supply voltage (see Note 3)
VCC = 3 V
VCC = 4.5 V
High-level input voltage
VCC = 5.5 V
VCC = 3 V
VIL
VI
VO
IOH
IOL
∆t/∆v
MIN
NOM
MAX
3
5
5.5
MAX
3
5
5.5
3.15
3.15
3.85
3.85
0
Output voltage
0
VCC = 3 V
VCC = 4.5 V
Low-level output current
NOM
2.1
Input voltage
High-level output current
MIN
2.1
VCC = 4.5 V
VCC = 5.5 V
Low-level input voltage
74AC16646
0.9
1.35
1.35
1.65
1.65
0
0
VCC
VCC
−4
−4
−24
−24
VCC = 5.5 V
VCC = 3 V
−24
−24
12
12
VCC = 4.5 V
VCC = 5.5 V
24
24
24
24
Input transition rise or fall rate
V
V
0.9
VCC
VCC
UNIT
V
V
V
mA
mA
0
10
0
10
ns/V
TA
Operating free-air temperature
−55
NOTE 3: All VCC and GND pins must be connected to the proper voltage power supply.
125
−40
85
°C
&(!)$'!& "!&"%)& *)!#" & % (!)$'2% !)
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')% %1& 1!',- %.' &)#$%& )%%)2% % )1 ! "'&1% !)
"!&&#% %% *)!#" /!# &!"%-
6
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SCAS241A − MARCH 1990 − REVISED APRIL 1996
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = −50 µA
VOH
VOL
IOH = −4 mA
VCC
MIN
TA = 25°C
TYP
MAX
54AC16646
MIN
MAX
74AC16646
MIN
3V
2.9
2.9
2.9
4.5 V
4.4
4.4
4.4
5.5 V
5.4
5.4
5.4
3V
2.58
2.4
2.48
4.5 V
3.94
3.7
3.8
5.5 V
4.94
4.7
4.8
MAX
V
IOH = −50 mA†
IOH = −75 mA†
5.5 V
3V
0.1
0.1
0.1
IOL = 50 µA
4.5 V
0.1
0.1
0.1
5.5 V
0.1
0.1
0.1
3.85
5.5 V
IOL = 12 mA
3.85
3V
0.36
0.5
0.44
4.5 V
0.36
0.5
0.44
5.5 V
0.36
0.5
0.44
IOL = 50 mA†
IOL = 75 mA†
5.5 V
II
IOZ‡
VI = VCC or GND
VI = VCC or GND
5.5 V
±0.1
5.5 V
±0.5
ICC
Ci
VI = VCC or GND,
VI = VCC or GND
5.5 V
8
V
1.65
5.5 V
IO = 0
UNIT
1.65
5V
±1
±1
µA
±10
±5
µA
160
80
µA
4.5
pF
Co
VI = VCC or GND
5V
16
† Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
‡ For I/O ports, the parameter IOZ includes the input leakage current.
pF
timing requirements over recommended operating free-air temperature range,
VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 2)
TA = 25°C
MIN
MAX
74AC16646
MIN
MAX
MIN
MAX
0
65
0
65
UNIT
fclock
tw
Clock frequency
0
Pulse duration, CLKAB or CLKBA high or low
7
7
7
ns
tsu
th
Setup time, A before CLKAB↑ or B before CLKBA↑
6.5
6.5
6.5
ns
1
1
1
ns
Hold time, A after CLKAB↑ or B after CLKBA↑
65
54AC16646
MHz
timing requirements over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 2)
TA = 25°C
MIN
MAX
0
74AC16646
MIN
MAX
MIN
MAX
0
75
0
75
UNIT
fclock
tw
Clock frequency
6.5
6.5
6.5
ns
tsu
th
Setup time, A before CLKAB↑ or B before CLKBA↑
5
5
5
ns
Hold time, A after CLKAB↑ or B after CLKBA↑
1
1
1
ns
Pulse duration, CLKAB or CLKBA high or low
75
54AC16646
MHz
&(!)$'!& "!&"%)& *)!#" & % (!)$'2% !)
%1& *'% !( %2%,!*$%&- ')'"%)" '' '& !%) *%"("'!&
')% %1& 1!',- %.' &)#$%& )%%)2% % )1 ! "'&1% !)
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•
7
SCAS241A − MARCH 1990 − REVISED APRIL 1996
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 2)
PARAMETER
fmax
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
FROM
(INPUT)
TO
(OUTPUT)
MIN
TA = 25°C
TYP
MAX
65
A or B
B or A
OE
A or B
OE
A or B
CLKBA or CLKAB
A or B
SAB or SBA†
(with A or B high)
A or B
SBA or SAB†
(with A or B low)
A or B
DIR
A or B
DIR
A or B
54AC16646
MIN
74AC16646
MAX
MIN
65
MAX
65
UNIT
MHz
3.4
9.3
13.2
3.4
15.7
3.4
14.8
3.6
10
13.4
3.6
15.1
3.6
4.5
3.8
10.5
3.8
17.6
3.8
16.4
4.8
13.9
4.8
22.1
4.8
20.9
4.4
7.6
4.4
11
4.4
10.7
4
7
4
10.4
4
10.1
4.7
12.1
4.7
19.9
4.7
18.7
4.8
12.2
4.8
18.8
4.8
18
4.7
12
4.7
19.9
4.7
18.5
4.5
11.4
4.5
17.2
4.5
16.4
4
10.5
4
17.3
4
16.3
5.2
13.3
5.2
20.3
5.2
19.3
3.6
10.3
3.6
17.9
3.6
16.8
4.7
13.5
4.7
22.1
4.7
20.8
4.6
7.8
4.6
11.6
4.6
11.2
3.9
7
3.9
11
3.9
10.6
ns
ns
ns
ns
ns
ns
ns
ns
† These parameters are measured with the internal output state of the storage register opposite that of the bus input.
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 2)
PARAMETER
fmax
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
FROM
(INPUT)
TO
(OUTPUT)
MIN
TA = 25°C
TYP
MAX
75
A or B
B or A
OE
A or B
OE
A or B
CLKBA or CLKAB
A or B
SAB or SBA†
(with A or B high)
A or B
SBA or SAB†
(with A or B low)
A or B
DIR
A or B
DIR
A or B
54AC16646
MIN
74AC16646
MAX
MIN
75
75
5.5
8.5
2.9
10.1
2.9
9.5
2.9
5.7
8.9
2.9
10.1
2.9
9.7
3.1
6.1
9.4
3.1
11.1
3.1
10.5
4.1
7.3
11
4.1
12.9
4.1
12.2
4
6.1
8.4
4
9.1
4
8.9
3.8
5.7
8
3.8
8.9
3.8
8.6
3.9
7
10.8
3.9
12.8
3.9
12.1
3.9
7.1
10.8
3.9
12.5
3.9
11.9
4
7.4
11.1
4
13.4
4
12.5
3.6
6.7
10.2
3.6
11.8
3.6
11.2
3.3
6.1
9.5
3.3
11.2
3.3
10.6
4.3
8
11.7
4.3
13.9
4.3
13.1
3
5.9
9.6
3
11.6
3
10.9
3.6
7
11.1
3.6
12.9
3.6
12.2
4
6.2
8.8
4
9.6
3
9.4
3.7
5.7
8.2
3.7
9
3.7
8.8
&(!)$'!& "!&"%)& *)!#" & % (!)$'2% !)
%1& *'% !( %2%,!*$%&- ')'"%)" '' '& !%)
*%"("'!& ')% %1& 1!',- %.' &)#$%& )%%)2% % )1 !
"'&1% !) "!&&#% %% *)!#" /!# &!"%-
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•
UNIT
MHz
2.9
† These parameters are measured with the internal output state of the storage register opposite that of the bus input.
8
MAX
ns
ns
ns
ns
ns
ns
ns
ns
SCAS241A − MARCH 1990 − REVISED APRIL 1996
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Outputs enabled
Power dissipation capacitance
CL = 50 pF,
Outputs disabled
TYP
UNIT
62
f = 1 MHz
pF
14
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
500 Ω
LOAD CIRCUIT
0V
tw
50%
th
tsu
VCC
Input
VCC
50%
Timing Input
50%
VCC
50%
50%
Data Input
0V
0V
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
Output
Control
(low-level
enabling)
VCC
50%
Input
50%
0V
tPHL
tPLH
In-Phase
Output
50% VCC
Out-of-Phase
Output
50% VCC
0V
tPZL
tPLZ
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
VOH
50% VCC
VOL
tPLH
tPHL
VCC
Output
Waveform 2
S1 at GND
(see Note B)
VOH
50% VCC
VOL
50%
50%
50% VCC
20% VCC
VOL
tPHZ
tPZH
VOLTAGE WAVEFORMS
[ VCC
50% VCC
80% VCC
VOH
[0V
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 2. Load Circuit and Voltage Waveforms
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