TI TMS320C6202BGNY300

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
D
D
D
D
D
Signal Processors (DSPs) TMS320C62x
– 5-, 4-, 3.33-ns Instruction Cycle Time
– 200-, 250-, 300-MHz Clock Rate
– Eight 32-Bit Instructions/Cycle
– 1600, 2 000, 2 400 MIPS
VelociTI Advanced Very Long Instruction
Word (VLIW) ’C62x CPU Core
– Eight Highly Independent Functional
Units:
– Six ALUs (32-/40-Bit)
– Two 16-Bit Multipliers (32-Bit Result)
– Load-Store Architecture With 32 32-Bit
General-Purpose Registers
– Instruction Packing Reduces Code Size
– All Instructions Conditional
Instruction Set Features
– Byte-Addressable (8-, 16-, 32-Bit Data)
– 8-Bit Overflow Protection
– Saturation
– Bit-Field Extract, Set, Clear
– Bit-Counting
– Normalization
On-Chip SRAM
– 1M-Bit (’C6204)
– 3M-Bit (’C6202/’C6202B)
– 7M-Bit (’C6203)
32-Bit External Memory Interface (EMIF)
– Glueless Interface to Synchronous
Memories: SDRAM or SBSRAM
– Glueless Interface to Asynchronous
Memories: SRAM and EPROM
– 52M-Byte Addressable External Memory
Space
Four-Channel Bootloading
Direct-Memory-Access (DMA) Controller
With an Auxiliary Channel
D Flexible Phase-Locked-Loop (PLL) Clock
Generator
D 32-Bit Expansion Bus
D
D
D
D
D
D
D
D
– Glueless/Low-Glue Interface to Popular
PCI Bridge Chips
– Glueless/Low-Glue Interface to Popular
Synchronous or Asynchronous
Microprocessor Buses
– Master/Slave Functionality
– Glueless Interface to Synchronous FIFOs
and Asynchronous Peripherals
Multichannel Buffered Serial Ports
(McBSPs)
– Direct Interface to T1/E1, MVIP, SCSA
Framers
– ST-Bus-Switching Compatible
– Up to 256 Channels Each
– AC97-Compatible
– Serial-Peripheral Interface (SPI)
Compatible (Motorola)
Two 32-Bit General-Purpose Timers
IEEE-1149.1 (JTAG†)
Boundary-Scan-Compatible
352-Pin BGA Package (GJL) (’02/02B/03)
384-Pin BGA Package (GLS) (’02/02B/03)
340-Pin BGA Package (GLW) (’C6204 only)
– Pin-Compatible With the GLS Package
Except Inner Row of Balls (Additional
Power and Ground Pins) are Removed‡
0.18-µm/5-Level Metal Process (’6202 only)
0.15-µm/5-Level Metal Process (’02B/03/04)
– CMOS Technology
3.3-V I/Os, 1.8-V Internal (’C6202 only)
3.3-V I/Os, 1.5-V Internal (’C6202B/03/04)
PRODUCT PREVIEW
D Highest Performance Fixed-Point Digital
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
VelociTI is a trademark of Texas Instruments Incorporated.
Motorola is a trademark of Motorola, Inc.
† IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
‡ For more details, see the GLS/GLW BGA package bottom view.
Copyright  2000, Texas Instruments Incorporated
This document contains information on products in more than one phase
of development. The status of each device is indicated on the page(s)
specifying its electrical characteristics.
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1
TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
Table of Contents
GJL/GLS/GLW BGA packages (bottom view) . . . . . . . . . . 3
device selection guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
’C62x device compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . 6
functional and CPU block diagram (’C62x devices) . . . . . 7
CPU description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
signal groups description . . . . . . . . . . . . . . . . . . . . . . . . . . 10
input and output clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
documentation support . . . . . . . . . . . . . . . . . . . . . . . . . . . .
clock PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
power-supply sequencing . . . . . . . . . . . . . . . . . . . . . . . . . .
absolute maximum ratings over operating case
temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . .
recommended operating conditions . . . . . . . . . . . . . . . . .
electrical characteristics over recommended ranges
of supply voltage and operating case temperature
external interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . 50
13
24
28
29
31
asynchronous memory timing . . . . . . . . . . . . . . . . . . . . . 38
synchronous-burst memory timing . . . . . . . . . . . . . . . . . 41
synchronous DRAM timing . . . . . . . . . . . . . . . . . . . . . . . . 43
HOLD/HOLDA timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
expansion bus synchronous FIFO timing . . . . . . . . . . . . 51
expansion bus asynchronous peripheral timing . . . . . . 53
expansion bus synchronous host port timing . . . . . . . . 56
expansion bus asynchronous host port timing . . . . . . . 62
32
32
XHOLD/XHOLDA timing . . . . . . . . . . . . . . . . . . . . . . . . . . 64
33
DMAC, timer, power-down timing . . . . . . . . . . . . . . . . . . 78
parameter measurement information . . . . . . . . . . . . . . . . 34
JTAG test-port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
multichannel buffered serial port timing . . . . . . . . . . . . . 66
PRODUCT PREVIEW
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
2
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TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
GJL/GLS/GLW BGA packages (bottom view)
GJL 352-PIN BALL GRID ARRAY (BGA) PACKAGE (’C6202/02B/03 ONLY)
( BOTTOM VIEW )
1
3
2
5
4
7
6
9
8
10
PRODUCT PREVIEW
AF
AE
AD
AC
AB
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
11 13 15 17 19 21 23 25
12 14 16 18 20 22 24 26
GLS 384-PIN BGA PACKAGE (’C6202/02B/03 ONLY)
GLW 340-PIN BGA PACKAGE (’C6204 ONLY)
( BOTTOM VIEW )
AB
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
3
1
2
5
4
9
7
6
8
11
10
12
13 15 17 19 21
14 16 18 20 22
These balls are NOT applicable for the ’C6204 devices GLW 340-pin BGA package.
POST OFFICE BOX 1443
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3
TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
device selection guide
Table 1 provides an overview of the TMS320C6202/02B/03/04 pin-compatible DSPs. The table shows
significant features of each device, including the capacity of on-chip RAM, the peripherals, the execution time,
and the package type with pin count, etc.
Table 1. TMS320C6202/02B/03/04 DSP Selection Guide
HARDWARE FEATURES
EMIF
DMA
Peripherals
PRODUCT PREVIEW
’C6203
√
√
√
4-Channel
4-Channel With
Throughput
Enhancements
4-Channel With
Throughput
Enhancements
4-Channel With
Throughput
Enhancements
√
√
√
√
3
3
3
2
32-Bit Timers
2
2
2
2
384K
64K
256K
256K
Block 0:
128K Bytes
Mapped Program
Block 1:
128K Bytes
Cache/Mapped
Program
Organization
128K
Internal Data
Memory
Organization
2 Blocks:
Four 16-Bit Banks
per Block
50/50 Split
Frequency
MHz
Voltage
PLL Options:
O tions:
In Both Packages
g
Additional
PLL Options:
18 x 18 mm
Packages
(GLS/GLW only)
BGA Package
’C6204
McBSPs
Size (Bytes)
Cycle Time
4
’C6202B
√
Expansion Bus
Size (Bytes)
Internal Program
Memory
’C6202
128K
200, 250
2 Blocks:
Four 16-Bit Banks
per Block
50/50 Split
250
4 ns (’6202-250)
5 ns (’6202-200)
ns
Block 0:
128K Bytes
Mapped Program
Block 1:
128K Bytes
Cache/Mapped
Program
4 ns (’6202B-250)
Block 0:
256K Bytes Mapped
Program
Block 1:
128K Bytes
Cache/Mapped
Program
512K
2 Blocks:
Four 16-Bit Banks
per Block
50/50 Split
250, 300
3.33 ns (’6203-300)
4 ns (’6203-250)
1 Block:
64K Bytes
Cache/Mapped
Program
64K
2 Blocks:
Four 16-Bit Banks
per Block
50/50 Split
200
5 ns (’6204-200)
Core (V)
1.8
1.5
1.5
1.5
I/O (V)
3.3
3.3
3.3
3.3
Bypass (x1)
√
√
√
√
x4
√
√
√
√
x8
–
√
√
–
x10
–
√
√
–
x6
–
√
√
–
x7
–
√
√
–
x9
–
√
√
–
x11
–
√
√
–
27 x 27 mm
352-pin GJL
352-pin GJL
352-pin GJL
–
18 x 18 mm
384-pin GLS
384-pin GLS
384-pin GLS
340-pin GLW
0.18 µm (18C05)
0.15 µm (15C05)
0.15 µm (15C05)
0.15 µm (15C05)
PD
PP
AI
PP
Process
Technology
µm
Product Status
Product Preview (PP)
Advance Information (AI)
Production Data (PD)
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TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
description
The TMS320C6202, TMS320C6202B, TMS320C6203, and TMS320C6204 devices are part of the
TMS320C62x fixed-point DSP family in the TMS320C6000 platform. The ’C62x devices are based on the
high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture developed by Texas
Instruments (TI), making these DSPs an excellent choice for multichannel and multifunction applications.
The TMS320C62x DSPs include an on-chip memory, with the ’C6203 device offering the most memory at
7 Mbits. For the ’C6202/’02B device, program memory consists of two blocks, with a 128K-byte block configured
as memory-mapped program space, and the other 128K-byte block user-configurable as cache or
memory-mapped program space. Data memory consists of two 64K-byte blocks of RAM. Similarly, the ’C6203
device program memory consists of two blocks, with a 256K-byte block configured as memory-mapped program
space, and the other 128K-byte block user-configurable as cache or memory-mapped program space. Data
memory consists of two 256K-byte blocks of RAM. For the ’C6204 device, program memory consists of a single
64K-byte block that is user-configured as cache or memory-mapped program space. Data memory consists of
two 32K-byte blocks of RAM.
The ’C6202/’02B/’03/’04 device has a powerful and diverse set of peripherals. The peripheral set includes
multichannel buffered serial ports (McBSPs), general-purpose timers, a 32-bit expansion bus (XB) that offers
ease of interface to synchronous or asynchronous industry-standard host bus protocols, and a glueless 32-bit
external memory interface (EMIF) capable of interfacing to SDRAM or SBSRAM and asynchronous peripherals.
The ’C62x devices have a complete set of development tools which includes: a new C compiler, an assembly
optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source
code execution.
Windows is a registered trademark of the Microsoft Corporation.
POST OFFICE BOX 1443
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5
PRODUCT PREVIEW
The TMS320C62x DSP offers cost-effective solutions to high-performance DSP programming challenges. The
TMS320C6202B/’03 has a performance of up to 2400 million instructions per second (MIPS) at 300 MHz, while
the TMS320C6202 has a performance of up to 2000 MIPS at 250 MHz, and the TMS320C6204 has a
performance of up to 1600 MIPS at 200 MHz. The ’C6202/’02B/’03/’04 DSP possesses the operational flexibility
of high-speed controllers and the numerical capability of array processors. These processors have
32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight
functional units provide six arithmetic logic units (ALUs) for a high degree of parallelism and two 16-bit multipliers
for a 32-bit result. The ’C6202/’02B/’03/’04 can produce two multiply-accumulates (MACs) per cycle. This gives
a total of 600 million MACs per second (MMACS) for the ’C6202B/’03 device, a total of 500 MMACS for the
’C6202 device, and a total of 400 MMACS for the ’C6204 device. The ’C6202/’02B/’03/’04 DSP also has
application-specific hardware logic, on-chip memory, and additional on-chip peripherals.
TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
’C62x device compatibility
The TMS320C6202, ’C6202B, ’C6203, and ’C6204 devices are pin-compatible; thus, making new system
designs easier and providing faster time to market. The following list summarizes the ’C62x device characteristic
differences:
D Core Supply Voltage (1.8 V versus 1.5 V)
D PLL Options Availability
Table 1 identifies the available PLL multiply factors [e.g., CLKIN x1 (PLL bypassed), x4] for each of the
’C62x devices. For additional details on the PLL clock module, see the Clock PLL section of this data sheet.
D On-Chip Memory Size
The ’C6202/’02B, ’C6203, and ’C6204 devices have different on-chip program memory and data memory
sizes (see Table 1).
D McBSPs
The ’C6204 device has two McBSPs while the ’C6202/’02B/’03 devices have three McBSPs on-chip.
PRODUCT PREVIEW
For a more detailed discussion on migration concerns, and similarities/differences between the ’C6202,
’C6202B, ’C6203, and ’C6204 devices, see the How to Begin Development and Migrate Across the
TMS320C6202/6202B/6203/6204 DSPs application report (literature number SPRA603) document.
6
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TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
functional and CPU block diagram (’C62x devices)
’C6202/’02B/’03/’04 Digital Signal Processors
Program
Bus
SDRAM or
SBSRAM
32
SRAM
External Memory
Interface (EMIF)
ROM/FLASH
Program
Access/Cache
Controller
Internal Program Memory
(see Table 1)
I/O Devices
’C62x CPU
Instruction Fetch
Timer 1
Synchronous
FIFOs
I/O Devices
Instruction Dispatch
Data Path A
32
Expansion
Bus
Data Path B
A Register File
.L1
Direct Memory
Access Controller
(DMA)
(see Table 1)
HOST CONNECTION
Master /Slave
TI PCI2040
Power PC
683xx
960
.S1
.M1 .D1
PLL
(see Table 1)
PowerDown
Logic
Test
B Register File
.D2 .M2
Data Bus
DMA Buses
Multichannel
Buffered Serial
Port 1
Multichannel
Buffered Serial
Port 2†
Control
Logic
Instruction Decode
Multichannel
Buffered Serial
Port 0
Framing Chips:
H.100, MVIP,
SCSA, T1, E1
AC97 Devices,
SPI Devices,
Codecs
Control
Registers
Data
Access
Controller
.S2
In-Circuit
Emulation
.L2
Interrupt
Control
PRODUCT PREVIEW
Timer 0
Internal Data
Memory
(see Table 1)
† McBSP2 is not applicable for the ’C6204 device.
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7
TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
CPU description
The CPU fetches VelociTI advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight
32-bit instructions to the eight functional units during every clock cycle. The VelociTI VLIW architecture features
controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. The
first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the
previous instruction, or whether it should be executed in the following clock as a part of the next execute packet.
Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The variable-length
execute packets are a key memory-saving feature, distinguishing the ’C62x CPU from other VLIW architectures.
The CPU features two sets of functional units. Each set contains four units and a register file. One set contains
functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files
each contain 16 32-bit registers for a total of 32 general-purpose registers. The two sets of functional units, along
with two register files, compose sides A and B of the CPU (see the Functional and CPU Block Diagram and
Figure 1). The four functional units on each side of the CPU can freely share the 16 registers belonging to that
side. Additionally, each side features a single data bus connected to all the registers on the other side, by which
the two sets of functional units can access data from the register files on the opposite side. While register access
by functional units on the same side of the CPU as the register file can service all the units in a single clock cycle,
register access using the register file across the CPU supports one read and one write per cycle.
PRODUCT PREVIEW
Another key feature of the ’C62x CPU is the load/store architecture, where all instructions operate on registers
(as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data
transfers between the register files and the memory. The data address driven by the .D units allows data
addresses generated from one register file to be used to load or store data to or from the other register file. The
’C62x CPU supports a variety of indirect addressing modes using either linear- or circular-addressing modes
with 5- or 15-bit offsets. All instructions are conditional, and most can access any one of the 32 registers. Some
registers, however, are singled out to support specific addressing or to hold the condition for conditional
instructions (if the condition is not automatically “true”). The two .M functional units are dedicated for multiplies.
The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results
available every clock cycle.
The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory.
The 32-bit instructions destined for the individual functional units are “linked” together by “1” bits in the least
significant bit (LSB) position of the instructions. The instructions that are “chained” together for simultaneous
execution (up to eight in total) compose an execute packet. A “0” in the LSB of an instruction breaks the chain,
effectively placing the instructions that follow it in the next execute packet. If an execute packet crosses the
fetch-packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of
the current fetch packet is padded with NOP instructions. The number of execute packets within a fetch packet
can vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one
per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch
packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units
for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit
registers, they can be subsequently moved to memory as bytes or half-words as well. All load and store
instructions are byte-, half-word, or word-addressable.
8
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TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
ÁÁÁÁ
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src1
src2
.L1
Á
ST1
Data Path A
dst
long dst
long src
long src
long dst
dst
.S1
src1
32
8
Á
Á
DA1
DA2
LD2
.D1
.D2
dst
src1
dst
src1
src2
2X
1X
src2
src1
dst
Á
Á
Á
Á
src2
.M2
src1
dst
src2
Data Path B
src1
dst
long dst
long src
.S2
Á
ST2
long src
long dst
dst
.L2
src2
src1
Register
File A
(A0–A15)
Á
Á
Á
Á
src2
LD1
8
8
src2
.M1
ÁÁÁÁÁÁ
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PRODUCT PREVIEW
CPU description (continued)
Register
File B
(B0–B15)
8
32
8
Á
Á
Á
Á
8
Control
Register
File
Figure 1. TMS320C62x CPU Data Paths
POST OFFICE BOX 1443
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9
TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
signal groups description
CLKIN
CLKOUT2
CLKOUT1
CLKMODE0
CLKMODE1†
CLKMODE2†
PLLV
PLLG
PLLF
PRODUCT PREVIEW
TMS
TDO
TDI
TCK
TRST
EMU1
EMU0
Clock/PLL
Reset and
Interrupts
IEEE Standard
1149.1
(JTAG)
Emulation
RESET
NMI
EXT_INT7
EXT_INT6
EXT_INT5
EXT_INT4
IACK
INUM3
INUM2
INUM1
INUM0
DMA Status
DMAC3
DMAC2
DMAC1
DMAC0
Power-Down
Status
PD
RSV11
’C6204
Only
RSV10
RSV9
RSV8
RSV7
RSV6
RSV5
Reserved‡
RSV4
RSV3
RSV2
RSV1
RSV0
Control/Status
† CLKMODE1 is NOT available on the ’C6202 device GJL package.
CLKMODE2 is NOT available on the GJL packages for the ’C6202/’02B/’03 devices.
‡ RSV5 through RSV11 pins are used on the ’C6204 device only.
Figure 2. CPU Signals
10
POST OFFICE BOX 1443
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TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
signal groups description (continued)
Asynchronous
Memory
Control
32
Data
CE3
CE2
CE1
CE0
EA[21:2]
BE3
BE2
BE1
BE0
TOUT1
TINP1
Memory Map
Space Select
20
Synchronous
Memory
Control
Word Address
HOLD/
HOLDA
Byte Enables
SDA10
SDRAS/SSOE
SDCAS/SSADS
SDWE/SSWE
HOLD
HOLDA
EMIF
(External Memory Interface)
Timer 1
Timer 0
PRODUCT PREVIEW
ED[31:0]
ARE
AOE
AWE
ARDY
TOUT0
TINP0
Timers
McBSP1
McBSP0
CLKX1
FSX1
DX1
Transmit
Transmit
CLKX0
FSX0
DX0
CLKR1
FSR1
DR1
Receive
Receive
CLKR0
FSR0
DR0
CLKS1
Clock
Clock
CLKS0
McBSP2
N/A For ’C6204 Devices
Transmit
CLKX2
FSX2
DX2
Receive
CLKR2
FSR2
DR2
Clock
CLKS2
McBSPs
(Multichannel Buffered Serial Ports)
Figure 3. Peripheral Signals
POST OFFICE BOX 1443
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11
TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
signal groups description (continued)
32
XD[31:0]
XBE3/XA5
XBE2/XA4
XBE1/XA3
XBE0/XA2
XRDY
Data
Clocks
Byte-Enable
Control/
Address
Control
I/O Port
Control
XHOLD
PRODUCT PREVIEW
XHOLDA
XFCLK
XOE
XRE
XWE/XWAIT
XCE3
XCE2
XCE1
XCE0
Arbitration
Expansion Bus
Host
Interface
Control
Figure 3. Peripheral Signals (Continued)
12
XCLKIN
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• HOUSTON, TEXAS 77251–1443
XCS
XAS
XCNTL
XW/R
XBLAST
XBOFF
TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
Signal Descriptions
SIGNAL
NAME
PIN NO.
TYPE‡
DESCRIPTION
GJL
GLS
GLW†
C12
B10
B10
I
Clock Input
CLKOUT1
AD20
Y18
Y18
O
Clock output at full device speed
CLKOUT2
AC19
AB19
AB19
O
Clock output at half of device speed
• Used for synchronous memory interface
CLKMODE0
B15
B12
B12
I
CLKMODE1
C11§
A9¶
A9¶
I
CLKMODE2
–
A14¶
A14¶
I
D13
C11
C11
PLL analog VCC connection for the low-pass filter
D14
C12
C12
A||
A||
PLL low-pass filter connection to external components and a bypass capacitor
CLOCK/PLL
CLKIN
PLLV#
PLLG#
Clock mode selects
• Selects what multiply factors of the input clock frequency the CPU frequency
equals.
For more detail on CLKMODE pins and the PLL multiply factors,
factors see the Clock
PLL section of this data sheet.
PLL analog GND connection for the low-pass filter
PLLF#
C13
A11
A11
A||
TMS
AD7
Y5
Y5
I
TDO
AE6
AA4
AA4
O/Z
TDI
AF5
Y4
Y4
I
JTAG test-port data in (features an internal pullup)
TCK
AE5
AB2
AB2
I
JTAG test-port clock
TRST
AC7
AA3
AA3
I
JTAG test-port reset (features an internal pulldown)
EMU1
AF6
AA5
AA5
I/O/Z
EMU0
AC8
AB4
AB4
I/O/Z
JTAG EMULATION
PRODUCT PREVIEW
JTAG test-port mode select (features an internal pullup)
JTAG test-port data out
Emulation pin 1, pullup with a dedicated 20-kΩ resistork
Emulation pin 0, pullup with a dedicated 20-kΩ resistork
RESET AND INTERRUPTS
RESET
K2
J3
J3
I
Device reset
NMI
L2
K2
K2
I
Nonmaskable interrupt
• Edge-driven (rising edge)
EXT_INT7
V4
U2
U2
EXT_INT6
Y2
U3
U3
EXT_INT5
AA1
W1
W1
I
External interru
interrupts
ts
• Edge-driven
g
(rising
g edge)
g
EXT_INT4
W4
V2
V2
IACK
Y1
V1
V1
O
Interrupt acknowledge for all active interrupts serviced by the CPU
INUM3
V2
R3
R3
INUM2
U4
T1
T1
O
Active interrupt identification number
• Valid during IACK for all active interrupts (not just external)
• Encoding order follows the interru
interrupt-service
t-service fetchfetch-packet
acket ordering
INUM1
V3
T2
T2
INUM0
W2
T3
T3
† The GLW BGA package (’C6204 only) is a subset of the GLS package (’C6202/02B/03), with the inner row of core supply voltage (CVDD) and
ground (VSS) pins removed (see the GLS/GLW BGA package bottom view).
‡ I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
§ For the ’C6202 GJL package only, the C11 pin is ground (VSS). For all other ’C62x GJL packages, the C11 pin is CLKMODE1.
¶ For the ’C6202 GLS and ’C6204 GLW packages, the CLKMODE2 (A14) and CLKMODE1 (A9) pins are internally unconnected.
# PLLV, PLLG, and PLLF are not part of external voltage supply or ground. See the clock PLL section for information on how to connect these pins.
|| A = Analog Signal (PLL Filter)
k For emulation and normal operation, pull up EMU1 and EMU0 with a dedicated 20-kΩ resistor. For boundary scan, pull down EMU1 and EMU0
with a dedicated 20-kΩ resistor.
POST OFFICE BOX 1443
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13
TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
Signal Descriptions (Continued)
SIGNAL
NAME
PIN NO.
GJL
GLS
GLW†
TYPE‡
DESCRIPTION
POWER-DOWN STATUS
PD
AB2
Y2
Y2
O
Power-down modes 2 or 3 (active if high)
A9
C8
C8
I
Expansion bus synchronous host interface clock input
O
Expansion bus FIFO interface clock output
EXPANSION BUS
XCLKIN
PRODUCT PREVIEW
XFCLK
B9
A8
A8
XD31
D15
C13
C13
XD30
B16
A13
A13
XD29
A17
C14
C14
XD28
B17
B14
B14
XD27
D16
B15
B15
XD26
A18
C15
C15
XD25
B18
A15
A15
XD24
D17
B16
B16
XD23
C18
C16
C16
XD22
A20
A17
A17
XD21
D18
B17
B17
XD20
C19
C17
C17
XD19
A21
B18
B18
XD18
D19
A19
A19
XD17
C20
C18
C18
XD16
B21
B19
B19
XD15
A22
C19
C19
XD14
D20
B20
B20
XD13
B22
A21
A21
XD12
E25
C21
C21
XD11
F24
D20
D20
XD10
E26
B22
B22
XD9
F25
D21
D21
XD8
G24
E20
E20
XD7
H23
E21
E21
XD6
F26
D22
D22
XD5
G25
F20
F20
XD4
J23
F21
F21
XD3
G26
E22
E22
XD2
H25
G20
G20
XD1
J24
G21
G21
Expansion bus data
• Used for transfer of data,
data address,
address and control
• Also controls initialization of DSP modes and ex
ansion bus at reset via pullup/
ullu /
expansion
pulldown resistors
(N
(Note:
Reserved
R
db
boot configuration
fi
i fifields
ld should
h ld b
be pulled
ll d d
down.))
I/O/Z
–
–
–
–
–
–
–
–
XCE[3:0] memory ty
type
e
y
XBLAST polarity
XW/R polarity
l it
Asynchronous or synchronous host operation
Arbitration mode (internal or external)
FIFO mode
Littl
di /bi endian
di
Little endian/big
Boot mode
XD0
K23
G22
G22
† The GLW BGA package (’C6204 only) is a subset of the GLS package (’C6202/02B/03), with the inner row of core supply voltage (CVDD) and
ground (VSS) pins removed (see the GLS/GLW BGA package bottom view).
‡ I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
14
POST OFFICE BOX 1443
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TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
Signal Descriptions (Continued)
SIGNAL
NAME
PIN NO.
GJL
GLS
GLW†
XCE3
F2
D2
D2
XCE2
E1
B1
B1
TYPE‡
DESCRIPTION
EXPANSION BUS (CONTINUED)
F3
D3
D3
XCE0
E2
C2
C2
XBE3/XA5
C7
C5
C5
XBE2/XA4
D8
A4
A4
Expansion bus I/O port memory space enables
• Enabled by bits 28,
28 29,
29 and 30 of the word address
• Only one asserted during any I/O port
ort data access
I/O/Z
Expansion bus multiplexed byte-enable control/address signals
• Act as byte enable for host port operation
• Act as address for I/O port
ort o
operation
eration
XBE1/XA3
A6
B5
B5
XBE0/XA2
C8
C6
C6
XOE
A7
A6
A6
O/Z
Expansion bus I/O port output enable
XRE
C9
C7
C7
O/Z
Expansion bus I/O port read enable
XWE/XWAIT
D10
B7
B7
O/Z
Expansion bus I/O port write enable and host port wait signals
XCS
A10
C9
C9
I
XAS
D9
B6
B6
I/O/Z
XCNTL
B10
B9
B9
I
XW/R
D11
B8
B8
I/O/Z
Expansion bus host port write/read enable. XW/R polarity selected at reset
XRDY
A5
C4
C4
I/O/Z
Expansion bus host port ready (active low) and I/O port ready (active high)
XBLAST
B6
B4
B4
I/O/Z
Expansion bus host port burst last–polarity selected at reset
XBOFF
B11
A10
A10
I
XHOLD
B5
A2
A2
I/O/Z
Expansion bus hold request
XHOLDA
D7
B3
B3
I/O/Z
Expansion bus hold acknowledge
CE3
AB25
Y21
Y21
CE2
AA24
W20
W20
Expansion bus host port chip-select input
Expansion bus host port address strobe
Expansion bus host control. XCNTL selects between expansion bus address or data
register
Expansion bus back off
EMIF – CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY
CE1
AB26
AA22
AA22
CE0
AA25
W21
W21
BE3
Y24
V20
V20
BE2
W23
V21
V21
BE1
AA26
W22
W22
O/Z
Memory space enables
• Enabled by bits 24 and 25 of the word address
• Only one asserted during any external data access
O/Z
Byte-enable control
• Decoded from the two lowest bits of the internal address
y
y
y
• Byte-write
enables for most types
of memory
• Can
be di
directly
C b
tl connected
t d tto SDRAM read
d and
d write
it mask
k signal
i
l (SDQM)
BE0
Y25
U20
U20
† The GLW BGA package (’C6204 only) is a subset of the GLS package (’C6202/02B/03), with the inner row of core supply voltage (CVDD) and
ground (VSS) pins removed (see the GLS/GLW BGA package bottom view).
‡ I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
15
PRODUCT PREVIEW
XCE1
O/Z
TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
Signal Descriptions (Continued)
SIGNAL
NAME
PIN NO.
GJL
GLS
GLW†
J25
H20
H20
EA20
J26
H21
H21
EA19
L23
H22
H22
EA18
K25
J20
J20
EA17
L24
J21
J21
EA16
L25
K21
K21
EA15
M23
K20
K20
EA14
M24
K22
K22
EA13
M25
L21
L21
EA12
N23
L20
L20
EA11
P24
L22
L22
EA10
P23
M20
M20
EA9
R25
M21
M21
EA8
R24
N22
N22
EA7
R23
N20
N20
EA6
T25
N21
N21
EA5
T24
P21
P21
EA4
U25
P20
P20
EA3
T23
R22
R22
EA2
V26
R21
R21
ED31
AD8
Y6
Y6
ED30
AC9
AA6
AA6
ED29
AF7
AB6
AB6
ED28
AD9
Y7
Y7
ED27
AC10
AA7
AA7
ED26
AE9
AB8
AB8
ED25
AF9
Y8
Y8
ED24
AC11
AA8
AA8
ED23
AE10
AA9
AA9
ED22
AD11
Y9
Y9
ED21
AE11
AB10
AB10
ED20
AC12
Y10
Y10
ED19
AD12
AA10
AA10
ED18
AE12
AA11
AA11
ED17
AC13
Y11
Y11
ED16
AD14
AB12
AB12
ED15
AC14
Y12
Y12
TYPE‡
DESCRIPTION
EMIF – ADDRESS
PRODUCT PREVIEW
EA21
O/Z
External address (word address)
EMIF – DATA
I/O/Z
External data
ED14
AE15
AA12
AA12
† The GLW BGA package (’C6204 only) is a subset of the GLS package (’C6202/02B/03), with the inner row of core supply voltage (CVDD) and
ground (VSS) pins removed (see the GLS/GLW BGA package bottom view).
‡ I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
16
POST OFFICE BOX 1443
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TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
Signal Descriptions (Continued)
SIGNAL
NAME
PIN NO.
GJL
GLS
GLW†
ED13
AD15
AA13
AA13
ED12
AC15
Y13
Y13
ED11
AE16
AB13
AB13
ED10
AD16
Y14
Y14
ED9
AE17
AA14
AA14
ED8
AC16
AA15
AA15
TYPE‡
DESCRIPTION
EMIF – DATA (CONTINUED)
ED7
AF18
Y15
Y15
ED6
AE18
AB15
AB15
ED5
AC17
AA16
AA16
ED4
AD18
Y16
Y16
ED3
AF20
AB17
AB17
ED2
AC18
AA17
AA17
ED1
AD19
Y17
Y17
ED0
AF21
AA18
AA18
ARE
V24
T21
T21
O/Z
Asynchronous memory read enable
AOE
V25
R20
R20
O/Z
Asynchronous memory output enable
AWE
U23
T22
T22
O/Z
Asynchronous memory write enable
ARDY
W25
T20
T20
I
Asynchronous memory ready input
External data
PRODUCT PREVIEW
I/O/Z
EMIF – ASYNCHRONOUS MEMORY CONTROL
EMIF – SYNCHRONOUS DRAM (SDRAM)/SYNCHRONOUS BURST SRAM (SBSRAM) CONTROL
SDA10
AE21
AA19
AA19
O/Z
SDRAM address 10 (separate for deactivate command)
SDCAS/SSADS
AE22
AB21
AB21
O/Z
SDRAM column-address strobe/SBSRAM address strobe
SDRAS/SSOE
AF22
Y19
Y19
O/Z
SDRAM row-address strobe/SBSRAM output enable
SDWE/SSWE
AC20
AA20
AA20
O/Z
SDRAM write enable/SBSRAM write enable
EMIF – BUS ARBITRATION
HOLD
Y26
V22
V22
I
Hold request from the host
HOLDA
V23
U21
U21
O
Hold-request-acknowledge to the host
TOUT1
J4
F2
F2
O
Timer 1 or general-purpose output
TINP1
G2
F3
F3
I
Timer 1 or general-purpose input
TOUT0
F1
D1
D1
O
Timer 0 or general-purpose output
TINP0
H4
E2
E2
I
Timer 0 or general-purpose input
DMAC3
Y3
V3
V3
DMAC2
AA2
W2
W2
DMAC1
AB1
AA1
AA1
TIMERS
DMA ACTION COMPLETE STATUS
O
DMA action complete
DMAC0
AA3
W3
W3
† The GLW BGA package (’C6204 only) is a subset of the GLS package (’C6202/02B/03), with the inner row of core supply voltage (CVDD) and
ground (VSS) pins removed (see the GLS/GLW BGA package bottom view).
‡ I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
17
TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
Signal Descriptions (Continued)
SIGNAL
NAME
PIN NO.
TYPE‡
DESCRIPTION
GJL
GLS
GLW†
CLKS0
M4
K3
K3
I
CLKR0
M2
L2
L2
I/O/Z
Receive clock
CLKX0
M3
K1
K1
I/O/Z
Transmit clock
DR0
R2
M2
M2
I
Receive data
DX0
P4
M3
M3
O/Z
Transmit data
FSR0
N3
M1
M1
I/O/Z
Receive frame sync
FSX0
N4
L3
L3
I/O/Z
Transmit frame sync
MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0)
External clock source (as opposed to internal)
PRODUCT PREVIEW
MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1)
CLKS1
G1
E1
E1
I
CLKR1
J3
G2
G2
I/O/Z
External clock source (as opposed to internal)
Receive clock
CLKX1
H2
G3
G3
I/O/Z
Transmit clock
DR1
L4
H1
H1
I
Receive data
DX1
J1
H2
H2
O/Z
Transmit data
FSR1
J2
H3
H3
I/O/Z
Receive frame sync
FSX1
K4
G1
G1
I/O/Z
Transmit frame sync
MULTICHANNEL BUFFERED SERIAL PORT 2 (McBSP2) (’C6202/’C6202B/’C6203 ONLY)
CLKS2
R3
N1
–
I
CLKR2
T2
N2
–
I/O/Z
External clock source (as opposed to internal)
Receive clock
CLKX2
R4
N3
–
I/O/Z
Transmit clock
DR2
V1
R2
–
I
Receive data
DX2
T4
R1
–
O/Z
Transmit data
FSR2
U2
P3
–
I/O/Z
Receive frame sync
FSX2
T3
P2
–
I/O/Z
Transmit frame sync
RESERVED FOR TEST
RSV0
L3
J2
J2
I
Reserved for testing, pullup with a dedicated 20-kΩ resistor
RSV1
G3
E3
E3
I
Reserved for testing, pullup with a dedicated 20-kΩ resistor
RSV2
A12
B11
B11
I
Reserved for testing, pullup with a dedicated 20-kΩ resistor
RSV3
C15
B13
B13
O
Reserved (leave unconnected, do not connect to power or ground)
RSV4
D12
C10
C10
O
Reserved (leave unconnected, do not connect to power or ground)
RSV5
–
–
N1
I
Reserved (leave unconnected)
RSV6
–
–
N2
I/O
Reserved (leave unconnected)
RSV7
–
–
N3
I/O
Reserved (leave unconnected)
RSV8
–
–
R2
I
Reserved (leave unconnected)
RSV9
–
–
R1
O
Reserved (leave unconnected)
RSV10
–
–
P3
I/O
Reserved (leave unconnected)
ADDITIONAL RESERVED FOR TEST (’C6204 ONLY)
RSV11
–
–
P2
I/O
Reserved (leave unconnected)
† The GLW BGA package (’C6204 only) is a subset of the GLS package (’C6202/02B/03), with the inner row of core supply voltage (CVDD) and
ground (VSS) pins removed (see the GLS/GLW BGA package bottom view).
‡ I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
18
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TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
Signal Descriptions (Continued)
SIGNAL
NAME
PIN NO.
GJL
GLS
GLW†
A11
A3
A3
TYPE‡
DESCRIPTION
DVDD
A16
A7
A7
B7
A16
A16
B8
A20
A20
B19
D4
D4
B20
D6
D6
D7
C6
D7
C10
D9
D9
C14
D10
D10
C17
D13
D13
C21
D14
D14
G4
D16
D16
G23
D17
D17
H3
D19
D19
H24
F1
F1
K3
F4
F4
K24
F19
F19
F22
L1
F22
L26
G4
G4
N24
G19
G19
P3
J4
J4
T1
J19
J19
T26
K4
K4
K19
U3
K19
U24
L1
L1
W3
M22
M22
W24
N4
N4
Y4
N19
N19
Y23
P4
P4
AD6
P19
P19
AD10
T4
T4
AD13
T19
T19
AD17
U1
U1
AD21
U4
U4
AE7
U19
U19
AE8
U22
U22
AE19
W4
W4
AE20
W6
W6
AF11
W7
S
PRODUCT PREVIEW
SUPPLY VOLTAGE PINS
3.3-V
3.3
V supply
su ly voltage (I/O)
W7
† The GLW BGA package (’C6204 only) is a subset of the GLS package (’C6202/02B/03), with the inner row of core supply voltage (CVDD) and
ground (VSS) pins removed (see the GLS/GLW BGA package bottom view).
‡ I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
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19
TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
Signal Descriptions (Continued)
SIGNAL
NAME
PIN NO.
GJL
GLS
GLW†
AF16
W9
W9
–
W10
W10
–
W13
W13
–
W14
W14
–
W16
W16
–
W17
W17
–
W19
W19
–
AB5
AB5
–
AB9
AB9
–
AB14
AB14
–
AB18
AB18
A1
E7
E7
TYPE‡
DESCRIPTION
SUPPLY VOLTAGE PINS (CONTINUED)
PRODUCT PREVIEW
DVDD
CVDD
A2
E8
E8
A3
E10
E10
A24
E11
E11
A25
E12
E12
A26
E13
E13
B1
E15
E15
B2
E16
E16
B3
F7
–
B24
F8
–
B25
F9
–
B26
F11
–
C1
F12
–
C2
F14
–
C3
F15
–
C4
F16
–
C23
G5
G5
C24
G6
–
C25
G17
–
C26
G18
G18
D3
H5
H5
D4
H6
–
D5
H17
–
D22
H18
H18
D23
J6
–
D24
J17
–
E4
K5
K5
E23
K18
K18
S
3.3-V
3.3
V su
supply
ly voltage (I/O)
S
1.5-V supply voltage (core) (’C6202B,
( C6202B, ’C6203,
C6203, and ’C6204
C6204 only)
1.8-V
1.8
V su
supply
ly voltage (core) ((’C6202
C6202 only)
AB4
L5
L5
† The GLW BGA package (’C6204 only) is a subset of the GLS package (’C6202/02B/03), with the inner row of core supply voltage (CVDD) and
ground (VSS) pins removed (see the GLS/GLW BGA package bottom view).
‡ I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
20
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TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
Signal Descriptions (Continued)
SIGNAL
NAME
PIN NO.
GJL
GLS
GLW†
AB23
L6
–
AC3
L17
–
AC4
L18
L18
TYPE‡
DESCRIPTION
CVDD
AC5
M5
M5
AC22
M6
–
AC23
M17
–
AC24
M18
M18
AD1
N5
N5
AD2
N18
N18
AD3
P6
–
AD4
P17
–
AD23
R5
R5
AD24
R6
–
AD25
R17
–
AD26
R18
R18
AE1
T5
T5
AE2
T6
–
AE3
T17
–
AE24
T18
T18
AE25
U7
–
AE26
U8
–
AF1
U9
–
AF2
U11
–
AF3
U12
–
AF24
U14
–
AF25
U15
–
AF26
U16
–
–
V7
V7
–
V8
V8
–
V10
V10
–
V11
V11
–
V12
V12
–
V13
V13
–
V15
V15
–
V16
V16
A4
A1
A1
S
PRODUCT PREVIEW
SUPPLY VOLTAGE PINS (CONTINUED)
1.5-V supply voltage (core) (’C6202B,
( C6202B, ’C6203,
C6203, and ’C6204
C6204 only)
1.8-V
1.8
V supply
su ly voltage (core) ((’C6202
C6202 only)
GROUND PINS
VSS
A8
A5
A5
A13
A12
A12
GND
Ground pins
A14
A18
A18
† The GLW BGA package (’C6204 only) is a subset of the GLS package (’C6202/02B/03), with the inner row of core supply voltage (CVDD) and
ground (VSS) pins removed (see the GLS/GLW BGA package bottom view).
‡ I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
POST OFFICE BOX 1443
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21
TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
Signal Descriptions (Continued)
SIGNAL
NAME
PIN NO.
GJL
GLS
GLW†
A15
A22
A22
TYPE‡
DESCRIPTION
PRODUCT PREVIEW
GROUND PINS (CONTINUED)
VSS
A19
B2
B2
A23
B21
B21
C1
B4
C1
B12
C3
C3
B13
C20
C20
B14
C22
C22
B23
D5
D5
C5
C11§
D8
D8
D11
D11
C16
D12
D12
C22
D15
D15
D1
D18
D18
D2
E4
E4
D6
E5
E5
D21
E6
E6
D25
E9
E9
D26
E14
E14
E3
E17
E17
E24
E18
E18
F4
E19
E19
F23
F5
F5
H1
F6
–
H26
F10
–
K1
F13
–
K26
F17
–
M1
F18
F18
M26
H4
H4
N1
H19
H19
N2
J1
J1
N25
J5
J5
N26
J18
J18
P1
J22
J22
P2
K6
–
P25
K17
–
P26
L4
L4
R1
L19
L19
R26
M4
M4
U1
M19
M19
GND
Ground pins
U26
N6
–
† The GLW BGA package (’C6204 only) is a subset of the GLS package (’C6202/02B/03), with the inner row of core supply voltage (CVDD) and
ground (VSS) pins removed (see the GLS/GLW BGA package bottom view).
‡ I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
§ For the ’C6202 GJL package only, the C11 pin is ground (VSS). For all other ’C62x GJL packages, the C11 pin is CLKMODE1.
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TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
Signal Descriptions (Continued)
SIGNAL
NAME
PIN NO.
GJL
GLS
GLW†
W1
N17
–
W26
P1
P1
AA4
P5
P5
AA23
P18
P18
AB3
P22
P22
AB24
R4
R4
AC1
R19
R19
AC2
U5
U5
AC6
U6
–
AC21
U10
–
AC25
U13
–
AC26
U17
–
TYPE‡
DESCRIPTION
VSS
AD5
U18
U18
AD22
V4
V4
AE4
V5
V5
AE13
V6
V6
AE14
V9
V9
AE23
V14
V14
AF4
V17
V17
AF8
V18
V18
AF10
V19
V19
AF12
W5
W5
AF13
W8
W8
AF14
W11
W11
AF15
W12
W12
AF17
W15
W15
AF19
W18
W18
AF23
Y1
Y1
–
Y3
Y3
–
Y20
Y20
–
Y22
Y22
–
AA2
AA2
–
AA21
AA21
–
AB1
AB1
–
AB3
AB3
–
AB7
AB7
–
AB11
AB11
–
AB16
AB16
–
AB20
AB20
GND
PRODUCT PREVIEW
GROUND PINS (CONTINUED)
Ground pins
–
AB22
AB22
† The GLW BGA package (’C6204 only) is a subset of the GLS package (’C6202/02B/03), with the inner row of core supply voltage (CVDD) and
ground (VSS) pins removed (see the GLS/GLW BGA package bottom view).
‡ I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
POST OFFICE BOX 1443
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23
TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
development support
TI offers an extensive line of development tools for the TMS320C6000t generation of DSPs, including tools
to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully
integrate and debug software and hardware modules.
The following products support development of ’C6000-based applications:
Software Development Tools:
Code Composer Studiot Integrated Development Environment (IDE): including Editor
C/C++/Assembly Code Generation, and Debug plus additional development tools
Scalable, Real-Time Foundation Software (DSP BIOS), which provides the basic run-time target software
needed to support any DSP application.
Hardware Development Tools:
Extended Development System (XDS) Emulator (supports ’C6000 multiprocessor system debug)
EVM (Evaluation Module)
PRODUCT PREVIEW
The TMS320 DSP Development Support Reference Guide (SPRU011) contains information about
development-support products for all TMS320t family member devices, including documentation. See this
document for further information on TMS320 documentation or any TMS320 support products from Texas
Instruments. An additional document, the TMS320 Third-Party Support Reference Guide (SPRU052), contains
information about TMS320-related products from other companies in the industry. To receive TMS320 literature,
contact the Literature Response Center at 800/477-8924.
See Table 2 for a complete listing of development-support tools for the TMS320C6000 DSP family. For
information on pricing and availability, contact the nearest TI field sales office or authorized distributor.
TMS320C6000, Code Composer Studio, XDS, and TMS320 are trademarks of Texas Instruments.
24
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TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
development support (continued)
Table 2. TMS320C6000 Development-Support Tools
TOOL
PART NUMBER
DSP/
BIOS
DESCRIPTION
CODE
COMPOSER
STUDIO IDE
CODE
GENERATION
TOOLS
TMDX320DAIS-07
TMS320 DSP Algorithm
Standard Developer’s Kit
6CCSFreeTool
TMS320C6000
Code Composer Studio
Free Evaluation Tools
(FREE 30-Day Trial)†
√
√
√
TMDX324685C-07
(Windows 95/98
Windows NT)
TMS320C6000 DSP
Code Composer Studio IDE
√
√
√
TMDX3246855-07
(Windows 95/98/NT)
TMS320C6000 DSP
Code Composer Studio IDE
Compile Tools
√
√
√
TMDX3240160-07
(Windows 95/98/NT)
TMS320C6000 DSP
Code Composer Studio IDE
Debug Tools
√
√
TMDX320006211
(DSK)
TMS320C6211 DSP Starter
Kit (DSK)
256KB Code Memory Limit
√
√
TMDS3260A6201
TMS320C62x DSP
Evaluation Module (EVM)
√
√
TMDS326006201
TMS320C62x DSP EVM
Bundle
√
√
TMDX3260A6701
TMS320C67x DSP EVM
√
√
TMDX326006701
TMS320C67x DSP EVM
Bundle
√
√
TMDS00510
XDS510 DSP Emulation
Hardware
EMULATION
DRIVERS
RTDX
SIMULATOR
√
√
√
√
TARGET
HARDWARE
SOFTWARE TOOLS
√
√
√
DSK-Specific
√
C6211 DSP
EVM-Specific
√
C6201 DSP
EVM-Specific
√
EVM-Specific
√
EVM-Specific
√
PRODUCT PREVIEW
√
HARDWARE TOOLS
√
√
√
√
C6201 DSP
C6701 DSP
√
C6701 DSP
Any C6000
DSP via
JTAG
† The TMS320C6000 Code Composer Studio Free Evaluation Tools can be downloaded for a free 30-day trial from the Texas Instruments web
site at http://www.ti.com. A CD-ROM version of the TMS320C6000 Code Composer Studio Free Evaluation Tools (literature number SPRC020)
is also available. For information on pricing and availability, contact the nearest TI field sales office or authorized distributor.
Code Composer Studio, TMS320, TMS320C6000, TMS320C62x, TMS320C67x, and XDS510 are trademarks of Texas Instruments.
Windows and Windows NT are registered trademarks of Microsoft Corporation.
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TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
device and development-support tool nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all TMS320
devices and support tools. Each TMS320 member has one of three prefixes: TMX, TMP, or TMS. Texas
Instruments recommends two of three possible prefix designators for support tools: TMDX and TMDS. These
prefixes represent evolutionary stages of product development from engineering prototypes (TMX / TMDX)
through fully qualified production devices/tools (TMS / TMDS).
Device development evolutionary flow:
TMX
Experimental device that is not necessarily representative of the final device’s electrical
specifications
TMP
Final silicon die that conforms to the device’s electrical specifications but has not completed
quality and reliability verification
TMS
Fully qualified production device
PRODUCT PREVIEW
Support tool development evolutionary flow:
TMDX
Development-support product that has not yet completed Texas Instruments internal qualification
testing.
TMDS
Fully qualified development-support product
TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer:
“Developmental product is intended for internal evaluation purposes.”
TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability
of the device have been demonstrated fully. TI’s standard warranty applies.
Predictions show that prototype devices ( TMX or TMP) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type
(for example, GJL), the temperature range (for example, blank is the default commercial temperature range),
and the device speed range in megahertz (for example, -300 is 300 MHz). Figure 4 provides a legend for
reading the complete device name for any TMS320 family member.
26
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TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
device and development-support tool nomenclature (continued)
TMS 320
GJL
(A)
300
DEVICE SPEED RANGE
Experimental device
Prototype device
Qualified device
MIL-STD-883C
High Rel (non-883C)
100 MHz
120 MHz
150 MHz
167 MHz
DEVICE FAMILY
320 = TMS320 family
200 MHz
233 MHz
250 MHz
300 MHz
TEMPERATURE RANGE (DEFAULT: 0°C TO 90°C)
Blank = 0°C to 90°C, commercial temperature
A
= –40°C to 105°C, extended temperature
PACKAGE TYPE†
N
= Plastic DIP
J
= Ceramic DIP
JD = Ceramic DIP side-brazed
GB = Ceramic PGA
FZ = Ceramic CC
FN = Plastic leaded CC
FD = Ceramic leadless CC
PJ = 100-pin plastic EIAJ QFP
PQ = 132-pin plastic bumpered QFP
PZ = 100-pin plastic TQFP
PBK = 128-pin plastic TQFP
PGE = 144-pin plastic TQFP
GFN = 256-pin plastic BGA
GGU = 144-pin plastic BGA
GGP = 352-pin plastic BGA
GJC = 352-pin plastic BGA
GJL = 352-pin plastic BGA
GLS = 384-pin plastic BGA
GLW = 340-pin plastic BGA
GHK = 288-pin plastic MicroStar BGAt
TECHNOLOGY
C = CMOS
E = CMOS EPROM
F = CMOS Flash EEPROM
PRODUCT PREVIEW
PREFIX
TMX =
TMP =
TMS =
SMJ =
SM =
C 6203
DEVICE
’1x DSP:
10
14
15
16
17
’2x DSP:
25
26
’2xx DSP:
203
204
206
209
240
’3x DSP:
30
31
32
’4x DSP:
40
44
’5x DSP:
† DIP
PGA
CC
QFP
TQFP
BGA
=
=
=
=
=
=
Dual-In-Line Package
Pin Grid Array
Chip Carrier
Quad Flat Package
Thin Quad Flat Package
Ball Grid Array
50
51
52
53
56
57
541
542
543
545
546
548
6201
6202
6202B
6203
6204
6205
6211
6701
6711
’54x DSP:
’6x DSP:
Figure 4. TMS320 Device Nomenclature (Including TMS320C6202, ’C6202B, ’C6203, and ’C6204)
MicroStar BGA is a trademark of Texas Instruments.
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TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
documentation support
Extensive documentation supports all TMS320 family generations of devices from product announcement
through applications development. The types of documentation available include: data sheets, such as this
document, with design specifications; complete user’s reference guides for all devices and tools; technical
briefs; development-support tools; on-line help; and hardware and software applications. The following is a
brief, descriptive list of support documentation specific to the ’C6x devices:
The TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189) describes the
’C6000 CPU architecture, instruction set, pipeline, and associated interrupts.
The TMS320C6000 Peripherals Reference Guide (literature number SPRU190) describes the functionality of
the peripherals available on ’C6x devices, such as the external memory interface (EMIF), host-port interface
(HPI), multichannel buffered serial ports (McBSPs), direct-memory-access (DMA), enhanced
direct-memory-access (EDMA) controller, expansion bus (XB), clocking and phase-locked loop (PLL); and
power-down modes. This guide also includes information on internal data and program memories.
The TMS320C6000 Technical Brief (literature number SPRU197) gives an introduction to the ’C62x/C67x
devices, associated development tools, and third-party support.
PRODUCT PREVIEW
The How to Begin Development and Migrate Across the TMS320C6202/6202B/6203/6204 DSPs application
report (literature number SPRA603) describes the migration concerns and identifies the similarites and
differences between the ’C6202, ’C6202B, ’C6203, and ’C6204 ’C6000 DSP devices.
The tools support documentation is electronically available within the Code Composer Studiot IDE. For a
complete listing of ’C6000 latest documentation, visit the Texas Instruments web site on the Worldwide Web
at http://www.ti.com uniform resource locator (URL).
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FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
clock PLL
All of the internal ’C62x clocks are generated from a single source through the CLKIN pin. This source clock
either drives the PLL, which multiplies the source clock in frequency to generate the internal CPU clock, or
bypasses the PLL to become the internal CPU clock.
To use the PLL to generate the CPU clock, the external PLL filter circuit must be properly designed. Figure 5,
and Table 3 through Table 8 show the external PLL circuitry for either x1 (PLL bypass) or x4 PLL multiply modes.
Figure 6 shows the external PLL circuitry for a system with ONLY x1 (PLL bypass) mode.
PRODUCT PREVIEW
To minimize the clock jitter, a single clean power supply should power both the ’C62x device and the external
clock oscillator circuit. Noise coupling into PLLF directly impacts PLL clock jitter. The minimum CLKIN rise and
fall times should also be observed. For the input clock timing requirements, see the input and output clocks
electricals section.
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TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
3.3V
PLLV
C3
10 mF
C4
0.1 mF
CLKMODE0
CLKMODE1
CLKMODE2
CLKIN
Internal to
’C6202/02B/03/04
PLL
PLLMULT
PLLCLK
CLKIN
1
LOOP FILTER
0
(For the PLL Options
and CLKMODE pins setup,
see Table 3 through Table 8)
C2
PLLF
PLLG
R1
PRODUCT PREVIEW
C1
30
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CPU
CLOCK
TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
NOTES: A. Keep the lead length and the number of vias between pin PLLF, pin PLLG, R1, C1, and C2 to a minimum. In addition, place all PLL
components (R1, C1, C2, C3, C4, and EMI Filter) as close to the ’C6000 device as possible. Best performance is achieved with PLL
components on single side of the board without jumpers, switches, or components other than the ones shown.
B. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (R1, C1, C2, C3, C4,
and the EMI Filter).
C. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DVDD.
D. EMI filter manufacturer: TDK part number ACF451832-333, 223, 153, 103. Panasonic part number EXCCET103U.
Figure 5. External PLL Circuitry for Either PLL Multiply Modes or x1 (Bypass) Mode
3.3V
PLLV
CLKMODE0
CLKMODE1
CLKMODE2
PLLMULT
PLL
Internal to
’C6202/02B/03/04
PLLCLK
CLKIN
LOOP FILTER
1
0
PLLF
CPU
CLOCK
PLLG
PRODUCT PREVIEW
CLKIN
NOTES: A. For a system with ONLY PLL x1 (bypass) mode, short the PLLF to PLLG.
B. The 3.3-V supply for PLLV must be from the same 3.3-V power plane supplying the I/O voltage, DVDD.
Figure 6. External PLL Circuitry for x1 (Bypass) PLL Mode Only
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TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
clock PLL (continued)
Table 3. TMS320C6202/’02B/’03/’04 GLS/GLW Packages PLL Multiply and Bypass (x1) Options†
GLS PACKAGE – 18 x 18 mm BGA (’C6202/’02B/’03 only)
GLW PACKAGE – 18 x 18 mm BGA (’C6204 only)
DEVICES AND PLL CLOCK OPTIONS
BIT (PIN NO.)
NO )
CLKMODE2 (A14)
CLKMODE1 (A9)
CLKMODE0 (B12)
’C6202, ’C6204‡
’C6202B, ’C6203
0
0
0
Bypass (x1)
Bypass (x1)
0
0
1
x4
x4
0
1
0
Bypass (x1)
x8
0
1
1
x4
x10
1
0
0
Bypass (x1)
x6
1
0
1
x4
x9
1
1
0
Bypass (x1)
x7
1
1
1
x4
x11
Value
PRODUCT PREVIEW
† f(CPU Clock) = f(CLKIN) x (PLL mode)
‡ For the ’C6202 GLS and ’C6204 GLW packages, the CLKMODE2 (A14) and CLKMODE1 (A9) pins are internally unconnected.
Table 4. TMS320C6202/’02B/’03 GJL Package PLL Multiply and Bypass (x1) Options†§
GJL PACKAGE 27 x 27 mm BGA
BIT (PIN NO.)
NO )
CLKMODE2 (N/A)¶#
CLKMODE1 (C11)§¶
CLKMODE0 (B15)
0
0
0
N/A#
Value
DEVICES AND PLL CLOCK OPTIONS
’C6202¶
’C6202B, ’C6203¶
Bypass (x1)
Bypass (x1)
1
x4
x4
1
0
x8
1
1
N/A
CLKMODE1 pin
in
(C11) Must Be
Grounded§#
x10
† f(CPU Clock) = f(CLKIN) x (PLL mode)
§ Note: The C11 pin is CLKMODE1 on the ’C6202B/’03 GJL package and a ground pin (VSS) for the ’C6202 GJL package. If a ’C6202 GJL package
is placed in a ’C6202B/’03 GJL board with the CLKMODE1 pin pulled to the non-default state (default is GND), current is drawn through the pullup
(3.3 V/ 20 kΩ or 165 µA). If a ’C6202 GJL package is placed in a ’C6202B/’03 board with the C11 pin directly connected to the VCC plane
for the PLL mode, a ground/power is shorted through the package. For more detailed information on device compatibility, see the How to
Begin Development and Migrate Across the TMS320C6202/6202B/6203/6204 DSPs application report (literature number SPRA603).
¶ CLKMODE2 and CLKMODE1 pins are not available on the ’C6202 GJL package.
The CLKMODE2 pin is not available on the ’C6202B/’C6203 GJL package.
# N/A = Not Applicable
Table 5. TMS320C6202 PLL Component Selection Table||
CLKMODE
CLKIN
RANGE
(MHz)
CPU CLOCK
FREQUENCY
(CLKOUT1)
RANGE (MHz)
CLKOUT2
RANGE
(MHz)
R1
(Ω)
C1
(nF)
C2
(pF)
TYPICAL
LOCK TIME
(µs)
x4
32.5–62.5
130–250
65–125
60.4
27
560
75
|| Under some operating conditions, the maximum PLL lock time may vary as much as 150% from the specified typical value. For example, if the
typical lock time is specified as 100 µs, the maximum value may be as long as 250 µs.
32
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FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
clock PLL (continued)
Table 6. TMS320C6202B PLL Component Selection Table†
CLKMODE‡
CLKIN
RANGE
(MHz)
x4
32.5–62.5
x6
21.7–41.7
x7
18.6–35.7
x8
16.3–31.3
x9
14.4–27.8
x10
13–25
x11
11.8–22.7
CPU CLOCK
FREQUENCY
RANGE (MHz)
CLKOUT2
RANGE
(MHz)
R1
(Ω)
C1
(nF)
C2
(pF)
TYPICAL
LOCK TIME
(µs)
130–250
130
250
65–125
65
125
60.4
27
560
75
† Under some operating conditions, the maximum PLL lock time may vary as much as 150% from the specified typical value. For example, if the
typical lock time is specified as 100 µs, the maximum value may be as long as 250 µs.
‡ CLKMODE x1, x4, x6, x7, x8, x9, x10, and x11 apply to the GLS device. The GJL device is restricted to x1, x4, x8, and x10 multiply factors.
CLKMODE‡
CLKIN
RANGE
(MHz)
x4
32.5–75
x6
21.7–50
x7
18.6–42.9
x8
16.3–37.5
x9
14.4–33.3
x10
13–30
CPU CLOCK
FREQUENCY
RANGE (MHz)
CLKOUT2
RANGE
(MHz)
R1
(Ω)
C1
(nF)
C2
(pF)
TYPICAL
LOCK TIME
(µs)
130–300
130
300
65–150
65
150
60.4
27
560
75
x11
11.8–27.3
† Under some operating conditions, the maximum PLL lock time may vary as much as 150% from the specified typical value. For example, if the
typical lock time is specified as 100 µs, the maximum value may be as long as 250 µs.
‡ CLKMODE x1, x4, x6, x7, x8, x9, x10, and x11 apply to the GLS device. The GJL device is restricted to x1, x4, x8, and x10 multiply factors.
Table 8. TMS320C6204 PLL Component Selection Table†
CLKMODE
CLKIN
RANGE
(MHz)
CPU CLOCK
FREQUENCY
RANGE (MHz)
CLKOUT2
RANGE
(MHz)
R1
(Ω)
C1
(nF)
C2
(pF)
TYPICAL
LOCK TIME
(µs)
x4
32.5–50
130–200
65–100
60.4
27
560
75
† Under some operating conditions, the maximum PLL lock time may vary as much as 150% from the specified typical value. For example, if the
typical lock time is specified as 100 µs, the maximum value may be as long as 250 µs.
power-supply sequencing
For ’C6202B, ’C6203, and ’C6204 devices only, the 1.5-V supply powers the core and the 3.3-V supply powers
the I/O buffers. For the ’C6202 device only, the 1.8-V supply powers the core and the 3.3-V supply powers the
I/O buffers. For internal device reliability, there are no specific sequencing requirements between the core
supply and the I/O supply. The only constraint is that neither supply should be powered on for extended periods
of time if the other supply is below the valid operating voltage.
System-level issues, such as bus contention, may require supply sequencing to be implemented. In this case,
the core supply should be powered up first, or at the same time as the I/O buffers. This is to ensure that the I/O
buffers have valid inputs from the core before the output buffers are powered up, thus preventing bus contention
with other chips on the board.
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PRODUCT PREVIEW
Table 7. TMS320C6203 PLL Component Selection Table†
TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
absolute maximum ratings over operating case temperature range (unless otherwise noted)†
Supply voltage range, CVDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 2.3 V
Supply voltage range, DVDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V
Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V
Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V
Operating case temperature range, TC: (default) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0_C to 90_C
(A version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40_C to105_C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55_C to 150_C
Temperature cycle range, (1000-cycle performance) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40_C to 125_C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
PRODUCT PREVIEW
’C6202B, ’C6203, and ’C6204 only
MIN
NOM
MAX
1.425
1.5
1.575
UNIT
1.71
1.8
1.89
3.14
3.30
3.46
V
0
0
0
V
CVDD
Supply voltage (CORE)
DVDD
Supply voltage (I/O)
VSS
VIH
Supply ground
VIL
IOH
Low-level input voltage
0.8
V
High-level output current
–8
mA
IOL
TC
Low-level output current
8
mA
90
_C
34
’C6202 only
High-level input voltage
2.0
Operating case temperature
0
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V
TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
electrical characteristics over recommended ranges of supply voltage and operating case
temperature (unless otherwise noted)
II
IOZ
TEST CONDITIONS
High-level output voltage
DVDD = MIN,
Low-level output voltage
Input current†
DVDD = MIN,
IOH = MAX
IOL = MAX
IDD2V
Off-state output current
Supply
Su
ly current, CPU + CPU memory
access‡
Supply current,
current peripherals‡
’C6202B, CVDD = NOM, CPU clock = 200 MHz
Supply current,
current I/O pins‡
Ci
Input capacitance
MAX
UNIT
V
0.6
V
±10
uA
±10
uA
520
mA
TBD
mA
’C6203, CVDD = NOM, CPU clock = 200 MHz
mA
’C6204, CVDD = NOM, CPU clock = 200 MHz
TBD
mA
’C6202, CVDD = NOM, CPU clock = 200 MHz
390
mA
’C6202B, CVDD = NOM, CPU clock = 200 MHz
TBD
mA
’C6203, CVDD = NOM, CPU clock = 200 MHz
TBD
mA
’C6204, CVDD = NOM, CPU clock = 200 MHz
TBD
mA
’C6202, DVDD = NOM, CPU clock = 200 MHz
IDD3V
TYP
2.4
VI = VSS to DVDD
VO = DVDD or 0 V
’C6202, CVDD = NOM, CPU clock = 200 MHz
IDD2V
MIN
70
mA
’C6202B, DVDD = NOM, CPU clock = 200 MHz
TBD
mA
’C6203, DVDD = NOM, CPU clock = 200 MHz
TBD
mA
’C6204, DVDD = NOM, CPU clock = 200 MHz
TBD
mA
10
pF
Co
Output capacitance
10
pF
† TMS and TDI are not included due to internal pullups. TRST is not included due to internal pulldown.
‡ Measured with average activity (50% high / 50% low power). For more detailed information on CPU/peripheral/I/O activity, see the TMS320C6000
Power Consumption Summary application report (literature number SPRA486).
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PRODUCT PREVIEW
PARAMETER
VOH
VOL
TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
PARAMETER MEASUREMENT INFORMATION
IOL
Tester Pin
Electronics
50 Ω
Vref
Output
Under
Test
CT = 30 pF†
IOH
† Typical distributed load circuit capacitance
Figure 7. Test Load Circuit
PRODUCT PREVIEW
signal transition levels
All input and output timing parameters are referenced to 1.5 V for both “0” and “1” logic levels.
Vref = 1.5 V
Figure 8. Input and Output Voltage Reference Levels for ac Timing Measurements
36
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FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
INPUT AND OUTPUT CLOCKS
timing requirements for CLKIN (PLL used)†‡§ (see Figure 9)
-200
NO
NO.
1
2
3
4
MIN
-250
MAX
MIN
-300
MAX
MIN
MAX
UNIT
tc(CLKIN)
tw(CLKINH)
Cycle time, CLKIN
5*M
4*M
3.33 * M
ns
Pulse duration, CLKIN high
0.4C
0.4C
0.4C
ns
tw(CLKINL)
tt(CLKIN)
Pulse duration, CLKIN low
0.4C
0.4C
Transition time, CLKIN
0.4C
5
5
ns
5
ns
† The reference points for the rise and fall transitions are measured at 20% and 80%, respectively, of VIH.
‡ M = the PLL multiplier factor (x4, x6, x7, x8, x9, x10, or x11) For more detail, see the clock PLL section.
§ C = CLKIN cycle time in ns. For example, when CLKIN frequency is 10 MHz, use C = 100 ns.
timing requirements for CLKIN [PLL bypassed (x1)]†§ (see Figure 9)
1
2
3
-250
MIN
MAX
MIN
-300
MAX
MIN
MAX
UNIT
tc(CLKIN)
tw(CLKINH)
Cycle time, CLKIN
5
4
3.33
ns
Pulse duration, CLKIN high
0.45C
0.45C
0.45C
ns
tw(CLKINL)
tt(CLKIN)
Pulse duration, CLKIN low
0.45C
0.45C
0.45C
ns
4
Transition time, CLKIN
0.6
0.6
† The reference points for the rise and fall transitions are measured at 20% and 80%, respectively, of VIH.
§ C = CLKIN cycle time in ns. For example, when CLKIN frequency is 10 MHz, use C = 100 ns.
1
0.6
PRODUCT PREVIEW
-200
NO
NO.
ns
4
2
CLKIN
3
4
Figure 9. CLKIN Timings
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TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
INPUT AND OUTPUT CLOCKS (CONTINUED)
timing requirements for XCLKIN† (see Figure 10)
-200
-250
-300
NO.
MIN
1
2
tc(XCLKIN)
tw(XCLKINH)
Cycle time, XCLKIN
Pulse duration, XCLKIN high
3
tw(XCLKINL) Pulse duration, XCLKIN low
† P = 1/CPU clock frequency in ns.
1
2
XCLKIN
PRODUCT PREVIEW
3
Figure 10. XCLKIN Timings
38
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UNIT
MAX
4P
ns
1.8P
ns
1.8P
ns
TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
INPUT AND OUTPUT CLOCKS (CONTINUED)
switching characteristics for CLKOUT2† (see Figure 11)
NO.
1
2
-200
-250
-300
PARAMETER
tc(CKO2)
tw(CKO2H)
Cycle time, CLKOUT2
Pulse duration, CLKOUT2 high
3
tw(CKO2L)
Pulse duration, CLKOUT2 low
† P = 1/CPU clock frequency in ns.
UNIT
MIN
MAX
2P – 0.7
2P + 0.7
ns
P – 0.7
P + 0.7
ns
P – 0.7
P + 0.7
ns
1
2
CLKOUT2
3
PRODUCT PREVIEW
Figure 11. CLKOUT2 Timings
switching characteristics for XFCLK†‡ (see Figure 12)
NO.
-200
-250
-300
PARAMETER
MIN
1
2
tc(XFCK)
tw(XFCKH)
Cycle time, XFCLK
Pulse duration, XFCLK high
3
tw(XFCKL)
Pulse duration, XFCLK low
† P = 1/CPU clock frequency in ns.
‡ D = 8, 6, 4, or 2; FIFO clock divide ratio, user-programmable
UNIT
MAX
D * P – 0.7
D * P + 0.7
ns
(D/2) * P – 0.7
(D/2) * P + 0.7
ns
(D/2) * P – 0.7
(D/2) * P + 0.7
ns
1
2
XFCLK
3
Figure 12. XFCLK Timings
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TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
ASYNCHRONOUS MEMORY TIMING
timing requirements for asynchronous memory cycles†‡§¶ (see Figure 13 – Figure 16)
-200
-250
-300
NO.
UNIT
MIN
3
tsu(EDV-AREH)
th(AREH-EDV)
Setup time, EDx valid before ARE high
tsu(ARDYH-AREL)
th(AREL-ARDYH)
Setup time, ARDY high before ARE low
tsu(ARDYL-AREL)
th(AREL-ARDYL)
Setup time, ARDY low before ARE low
10
11
tw(ARDYH)
Pulse width, ARDY high
15
tsu(ARDYH-AWEL)
th(AWEL-ARDYH)
Setup time, ARDY high before AWE low
tsu(ARDYL-AWEL)
th(AWEL-ARDYL)
Setup time, ARDY low before AWE low
4
6
7
9
PRODUCT PREVIEW
16
18
19
ns
3.5
ns
–[(RST – 3) * P – 6]
ns
(RST – 3) * P + 2
ns
–[(RST – 3) * P – 6]
ns
(RST – 3) * P + 2
ns
2P
ns
–[(WST – 3) * P – 6]
ns
(WST – 3) * P + 2
ns
–[(WST – 3) * P – 6]
ns
Hold time, EDx valid after ARE high
Hold time, ARDY high after ARE low
Hold time, ARDY low after ARE low
Hold time, ARDY high after AWE low
Hold time, ARDY low after AWE low
MAX
1
(WST – 3) * P + 2
ns
† To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. If ARDY does meet setup or hold
time, it may be recognized in the current cycle or the next cycle. Thus, ARDY can be an asynchronous input.
‡ RS = Read Setup, RST = Read Strobe, RH = Read Hold, WS = Write Setup, WST = Write Strobe, WH = Write Hold. These parameters are
programmed via the EMIF CE space control registers.
§ P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
¶ The sum of RS and RST (or WS and WST) must be a minimum of 4 in order to use ARDY input to extend strobe width.
switching characteristics for asynchronous memory cyclesद# (see Figure 13 РFigure 16)
NO.
-200
-250
-300
PARAMETER
MIN
1
UNIT
TYP
MAX
Output setup time, select signals valid to ARE low
RS * P – 2
ns
2
tosu(SELV-AREL)
toh(AREH-SELIV)
Output hold time, ARE high to select signals invalid
RH * P – 2
ns
5
tw(AREL)
Pulse width, ARE low
8
td(ARDYH-AREH)
tosu(SELV-AWEL)
Delay time, ARDY high to ARE high
toh(AWEH-SELIV)
tw(AWEL)
Output hold time, AWE high to select signals invalid
12
13
14
RST * P
Output setup time, select signals valid to AWE low
Pulse width, AWE low
3P
WS * P – 3
ns
ns
WH * P – 2
ns
WST * P
17
ns
4P + 5
ns
td(ARDYH-AWEH) Delay time, ARDY high to AWE high
3P
4P + 5
ns
‡ RS = Read Setup, RST = Read Strobe, RH = Read Hold, WS = Write Setup, WST = Write Strobe, WH = Write Hold. These parameters are
programmed via the EMIF CE space control registers.
§ P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
¶ The sum of RS and RST (or WS and WST) must be a minimum of 4 in order to use ARDY input to extend strobe width.
# Select signals include: CEx, BE[3:0], EA[21:2], AOE; and for writes, include ED[31:0], with the exception that CEx can stay active for an additional
7P ns following the end of the cycle.
40
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FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
ASYNCHRONOUS MEMORY TIMING (CONTINUED)
Setup = 2
Strobe = 3
Hold = 2
CLKOUT1
1
2
1
2
1
2
CEx
BE[3:0]
EA[21:2]
3
4
ED[31:0]
1
2
AOE
ARE
PRODUCT PREVIEW
5
6
7
AWE
ARDY
Figure 13. Asynchronous Memory Read Timing (ARDY Not Used)
Setup = 2
Strobe = 3
Not Ready
Hold = 2
CLKOUT1
1
2
1
2
1
2
CEx
BE[3:0]
EA[21:2]
3
4
ED[31:0]
1
2
AOE
8
10
9
ARE
AWE
11
ARDY
Figure 14. Asynchronous Memory Read Timing (ARDY Used)
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TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
ASYNCHRONOUS MEMORY TIMING (CONTINUED)
Setup = 2 Strobe = 3
Hold = 2
CLKOUT1
12
13
12
13
12
13
12
13
CEx
BE[3:0]
EA[21:2]
ED[31:0]
AOE
15
ARE
16
PRODUCT PREVIEW
14
AWE
ARDY
Figure 15. Asynchronous Memory Write Timing (ARDY Not Used)
Setup = 2 Strobe = 3
Not Ready
Hold = 2
CLKOUT1
12
13
12
13
12
13
12
13
CEx
BE[3:0]
EA[21:2]
ED[31:0]
AOE
ARE
17
18
19
AWE
11
ARDY
Figure 16. Asynchronous Memory Write Timing (ARDY Used)
42
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
SYNCHRONOUS-BURST MEMORY TIMING
timing requirements for synchronous-burst SRAM cycles (see Figure 17)
-200
NO
NO.
7
8
MIN
tsu(EDV-CKO2H)
th(CKO2H-EDV)
-250
MAX
MIN
-300
MAX
MIN
MAX
UNIT
Setup time, read EDx valid before CLKOUT2 high
2.5
2.0
1.7
ns
Hold time, read EDx valid after CLKOUT2 high
2.0
2.0
1.5
ns
switching characteristics for synchronous-burst SRAM cycles†‡ (see Figure 17 and Figure 18)
PARAMETER
MIN
1
tosu(CEV-CKO2H)
Output setup time, CEx valid before
CLKOUT2 high
2
toh(CKO2H-CEV)
Output hold time, CEx valid after
CLKOUT2 high
3
tosu(BEV-CKO2H)
Output setup time, BEx valid before
CLKOUT2 high
4
toh(CKO2H-BEIV)
Output hold time, BEx invalid after
CLKOUT2 high
5
tosu(EAV-CKO2H)
Output setup time, EAx valid before
CLKOUT2 high
6
toh(CKO2H-EAIV)
Output hold time, EAx invalid after
CLKOUT2 high
9
Output setup time, SDCAS/SSADS
tosu(ADSV-CKO2H)
valid before CLKOUT2 high
10
toh(CKO2H-ADSV)
11
-250
MAX
MIN
-300
MAX
MIN
MAX
UNIT
P – 0.8
P – 0.8
P + 0.1
ns
P–4
P–3
P – 2.3
ns
P – 0.8
P – 0.8
P + 0.1
ns
P–4
P–3
P – 2.3
ns
P – 0.8
P – 0.8
P + 0.1
ns
P–4
P–3
P – 2.3
ns
P – 0.8
P – 0.8
P + 0.1
ns
Output hold time, SDCAS/SSADS
valid after CLKOUT2 high
P–4
P–3
P – 2.3
ns
tosu(OEV-CKO2H)
Output setup time, SDRAS/SSOE
valid before CLKOUT2 high
P – 0.8
P – 0.8
P + 0.1
ns
12
toh(CKO2H-OEV)
Output hold time, SDRAS/SSOE
valid after CLKOUT2 high
P–4
P–3
P – 2.3
ns
13
tosu(EDV-CKO2H)
Output setup time, EDx valid before
CLKOUT2 high§
P – 1.2
P – 1.2
P + 0.1
ns
14
toh(CKO2H-EDIV)
Output hold time, EDx invalid after
CLKOUT2 high
P–4
P–3
P – 2.3
ns
15
tosu(WEV-CKO2H)
Output setup time, SDWE/SSWE
valid before CLKOUT2 high
P – 0.8
P – 0.8
P + 0.1
ns
16
toh(CKO2H-WEV)
Output hold time, SDWE/SSWE
valid after CLKOUT2 high
P–4
P–3
P – 2.3
ns
PRODUCT PREVIEW
-200
NO
NO.
† P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
‡ SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM accesses.
§ For the first write in a series of one or more consecutive adjacent writes, the write data is generated one CLKOUT2 cycle early to accommodate
the ED enable time.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
43
TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)
CLKOUT2
1
2
CEx
BE[3:0]
3
BE1
BE2
BE3
BE4
4
EA[21:2]
5
A1
A2
A3
A4
6
7
Q1
ED[31:0]
8
Q2
Q3
9
Q4
10
SDCAS/SSADS†
11
12
PRODUCT PREVIEW
SDRAS/SSOE†
SDWE/SSWE†
† SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM accesses.
Figure 17. SBSRAM Read Timing
CLKOUT2
1
2
CEx
BE[3:0]
3
BE1
BE2
BE3
BE4
4
EA[21:2]
5
A1
A2
A3
A4
Q1
Q2
Q3
Q4
6
13
14
ED[31:0]
9
10
15
16
SDCAS/SSADS†
SDRAS/SSOE†
SDWE/SSWE†
† SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM accesses.
Figure 18. SBSRAM Write Timing
44
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
SYNCHRONOUS DRAM TIMING
timing requirements for synchronous DRAM cycles (see Figure 19)
-200
NO
NO.
7
8
MIN
tsu(EDV-CKO2H)
th(CKO2H-EDV)
Setup time, read EDx valid before CLKOUT2 high
Hold time, read EDx valid after CLKOUT2 high
-250
MAX
MIN
MAX
-300
MIN
MAX
UNIT
1.2
1.2
0.5
ns
3
2.7
2
ns
switching characteristics for synchronous DRAM cycles†‡ (see Figure 19–Figure 24)
PARAMETER
MIN
1
tosu(CEV-CKO2H)
Output setup time, CEx valid
before CLKOUT2 high
2
toh(CKO2H-CEV)
Output hold time, CEx valid after
CLKOUT2 high
3
tosu(BEV-CKO2H)
Output setup time, BEx valid
before CLKOUT2 high
4
toh(CKO2H-BEIV)
Output hold time, BEx invalid after
CLKOUT2 high
5
tosu(EAV-CKO2H)
Output setup time, EAx valid
before CLKOUT2 high
6
toh(CKO2H-EAIV)
Output hold time, EAx invalid after
CLKOUT2 high
9
tosu(CASV-CKO2H)
Output setup time,
SDCAS/SSADS valid before
CLKOUT2 high
10
toh(CKO2H-CASV)
Output hold time, SDCAS/SSADS
valid after CLKOUT2 high
11
tosu(EDV-CKO2H)
Output setup time, EDx valid
before CLKOUT2 high§
12
toh(CKO2H-EDIV)
Output hold time, EDx invalid after
CLKOUT2 high
13
tosu(WEV-CKO2H)
Output setup time, SDWE/SSWE
valid before CLKOUT2 high
14
toh(CKO2H-WEV)
15
-250
MAX
MIN
-300
MAX
MIN
MAX
UNIT
P–1
P – 0.9
P + 0.6
ns
P – 3.5
P – 2.9
P – 1.8
ns
P–1
P – 0.9
P + 0.6
ns
P – 3.5
P – 2.9
P – 1.8
ns
P–1
P – 0.9
P + 0.6
ns
P – 3.5
P – 2.9
P – 1.8
ns
P–1
P – 0.9
P + 0.6
ns
P – 3.5
P – 2.9
P – 1.8
ns
P–1
P – 1.5
P + 0.6
ns
P – 3.5
P – 2.8
P – 1.8
ns
P–1
P – 0.9
P + 0.6
ns
Output hold time, SDWE/SSWE
valid after CLKOUT2 high
P – 3.5
P – 2.9
P – 1.8
ns
tosu(SDA10V-CKO2H)
Output setup time, SDA10 valid
before CLKOUT2 high
P–1
P – 0.9
P + 0.6
ns
16
toh(CKO2H-SDA10IV)
Output hold time, SDA10 invalid
after CLKOUT2 high
P – 3.5
P – 2.9
P – 1.8
ns
17
tosu(RASV-CKO2H)
Output setup time, SDRAS/SSOE
valid before CLKOUT2 high
P–1
P – 0.9
P + 0.6
ns
18
toh(CKO2H-RASV)
Output hold time, SDRAS/SSOE
valid after CLKOUT2 high
P – 3.5
P – 2.9
P – 1.8
ns
PRODUCT PREVIEW
-200
NO
NO.
† P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
‡ SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.
§ For the first write in a series of one or more consecutive adjacent writes, the write data is generated one CLKOUT2 cycle early to accommodate
the ED enable time.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
45
TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
SYNCHRONOUS DRAM TIMING (CONTINUED)
READ
READ
READ
CLKOUT2
1
2
CEx
3
BE[3:0]
5
EA[15:2]
4
BE1
BE2
CA2
CA3
BE3
6
CA1
7
8
D1
ED[31:0]
15
16
9
10
D2
D3
SDA10
PRODUCT PREVIEW
SDRAS/SSOE†
SDCAS/SSADS†
SDWE/SSWE†
† SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.
Figure 19. Three SDRAM READ Commands
WRITE
WRITE
WRITE
CLKOUT2
1
2
CEx
3
BE[3:0]
4
BE1
5
EA[15:2]
BE3
CA2
CA3
D2
D3
6
CA1
11
D1
ED[31:0]
BE2
12
15
16
9
10
13
14
SDA10
SDRAS/SSOE†
SDCAS/SSADS†
SDWE/SSWE†
† SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.
Figure 20. Three SDRAM WRT Commands
46
POST OFFICE BOX 1443
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TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
SYNCHRONOUS DRAM TIMING (CONTINUED)
ACTV
CLKOUT2
1
2
CEx
BE[3:0]
5
Bank Activate/Row Address
EA[15:2]
ED[31:0]
15
Row Address
SDA10
17
18
SDRAS/SSOE†
PRODUCT PREVIEW
SDCAS/SSADS†
SDWE/SSWE†
† SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.
Figure 21. SDRAM ACTV Command
DCAB
CLKOUT2
1
2
15
16
17
18
CEx
BE[3:0]
EA[15:2]
ED[31:0]
SDA10
SDRAS/SSOE†
SDCAS/SSADS†
13
14
SDWE/SSWE†
† SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.
Figure 22. SDRAM DCAB Command
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
47
TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
SYNCHRONOUS DRAM TIMING (CONTINUED)
REFR
CLKOUT2
1
2
CEx
BE[3:0]
EA[15:2]
ED[31:0]
SDA10
17
18
SDRAS/SSOE†
9
10
PRODUCT PREVIEW
SDCAS/SSADS†
SDWE/SSWE†
† SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.
Figure 23. SDRAM REFR Command
MRS
CLKOUT2
1
2
5
6
CEx
BE[3:0]
EA[15:2]
MRS Value
ED[31:0]
SDA10
17
18
9
10
13
14
SDRAS/SSOE†
SDCAS/SSADS†
SDWE/SSWE†
† SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.
Figure 24. SDRAM MRS Command
48
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
HOLD/HOLDA TIMING
timing requirements for the HOLD/HOLDA cycles† (see Figure 25)
-200
-250
-300
NO.
MIN
3
toh(HOLDAL-HOLDL) Hold time, HOLD low after HOLDA low
† P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
UNIT
MAX
P
ns
switching characteristics for the HOLD/HOLDA cycles†‡ (see Figure 25)
PARAMETER
MIN
1
2
4
tR(HOLDL-EMHZ)
td(EMHZ-HOLDAL)
Response time, HOLD low to EMIF Bus high impedance
tR(HOLDH-EMLZ)
td(EMLZ-HOLDAH)
Response time, HOLD high to EMIF Bus low impedance
UNIT
3P
MAX
§
ns
0
2P
ns
3P
7P
ns
Delay time, EMIF Bus high impedance to HOLDA low
5
Delay time, EMIF Bus low impedance to HOLDA high
0
2P
ns
† P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
‡ EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE, and SDA10.
§ All pending EMIF transactions are allowed to complete before HOLDA is asserted. The worst case for this is an asynchronous read or write with
external ARDY used or a minimum of eight consecutive SDRAM reads or writes when RBTR8 = 1. If no bus transactions are occurring, then the
minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1.
External Requestor
Owns Bus
DSP Owns Bus
DSP Owns Bus
3
HOLD
2
5
HOLDA
EMIF Bus†
1
4
’C62x
’C62x
† EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE, and SDA10.
Figure 25. HOLD/HOLDA Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
49
PRODUCT PREVIEW
NO.
-200
-250
-300
TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
RESET TIMING
timing requirements for reset† (see Figure 26)
-200
-250
-300
NO.
MIN
MAX
Width of the RESET pulse (PLL stable)‡
10P
ns
250
µs
5P
ns
1
tw(RST)
Width of the RESET pulse (PLL needs to sync up)§
10
tsu(XD)
th(XD)
Setup time, XD configuration bits valid before RESET high¶
Hold time, XD configuration bits valid after RESET high¶
ns
† P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
‡ This parameter applies to CLKMODE x1 when CLKIN is stable, and applies to CLKMODE x4, x6, x7, x8, x9, x10, and x11 when CLKIN and PLL
are stable.
§ This parameter applies to CLKMODE x4, x6, x7, x8, x9, x10, and x11 only (It does not apply to CLKMODE x1). The RESET signal is not connected
internally to the clock PLL circuit. The PLL, however, may need up to 250 µs to stabilize following device power up or after PLL configuration
has been changed. During that time, RESET must be asserted to ensure proper device operation. See the clock PLL section for PLL lock times.
¶ XD[31:0] are the boot configuration pins during device reset.
PRODUCT PREVIEW
11
UNIT
5P
switching characteristics during reset†# (see Figure 26)
NO.
PARAMETER
-200
-250
-300
MIN
2
3
4
5
6
7
8
9
td(RSTL-CKO2IV)
td(RSTH-CKO2V)
Delay time, RESET low to CLKOUT2 invalid
td(RSTL-HIGHIV)
td(RSTH-HIGHV)
Delay time, RESET low to high group invalid
td(RSTL-LOWIV)
td(RSTH-LOWV)
Delay time, RESET low to low group invalid
td(RSTL-ZHZ)
td(RSTH-ZV)
Delay time, RESET low to Z group high impedance
MAX
P
Delay time, RESET high to CLKOUT2 valid
ns
4P
P
Delay time, RESET high to high group valid
ns
ns
4P
P
Delay time, RESET high to low group valid
Delay time, RESET high to Z group valid
UNIT
ns
ns
4P
P
ns
ns
4P
ns
† P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
# High group consists of:
XFCLK, HOLDA
Low group consists of:
IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1
Z group consists of:
EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE,
SDA10, CLKX0, CLKX1, CLKX2, FSX0, FSX1, FSX2, DX0, DX1, DX2, CLKR0, CLKR1, CLKR2, FSR0, FSR1,
FSR2, XCE[3:0], XBE[3:0]/XA[5:2], XOE, XRE, XWE/XWAIT, XAS, XW/R, XRDY, XBLAST, XHOLD,
and XHOLDA
50
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
RESET TIMING (CONTINUED)
CLKOUT1
1
10
11
RESET
2
3
4
5
6
7
8
9
CLKOUT2
HIGH GROUP†
LOW GROUP†
Z GROUP†
† High group consists of:
Low group consists of:
Z group consists of:
XFCLK, HOLDA
IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1.
EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE,
SDA10, CLKX0, CLKX1, CLKX2, FSX0, FSX1, FSX2, DX0, DX1, DX2, CLKR0, CLKR1, CLKR2, FSR0, FSR1,
FSR2, XCE[3:0], XBE[3:0]/XA[5:2], XOE, XRE, XWE/XWAIT, XAS, XW/R, XRDY, XBLAST, XHOLD,
and XHOLDA.
‡ XD[31:0] are the boot configuration pins during device reset.
Figure 26. Reset Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
51
PRODUCT PREVIEW
Boot Configuration
XD[31:0]‡
TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
EXTERNAL INTERRUPT TIMING
timing requirements for interrupt response cycles† (see Figure 27)
-200
-250
-300
NO.
MIN
2
3
tw(ILOW)
tw(IHIGH)
UNIT
MAX
Width of the interrupt pulse low
2P
ns
Width of the interrupt pulse high
2P
ns
† P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
switching characteristics during interrupt response cycles† (see Figure 27)
NO.
-200
-250
-300
PARAMETER
MIN
PRODUCT PREVIEW
1
4
5
6
UNIT
MAX
tR(EINTH – IACKH)
td(CKO2L-IACKV)
Response time, EXT_INTx high to IACK high
Delay time, CLKOUT2 low to IACK valid
9P
0
10
ns
ns
td(CKO2L-INUMV)
td(CKO2L-INUMIV)
Delay time, CLKOUT2 low to INUMx valid
0
10
ns
Delay time, CLKOUT2 low to INUMx invalid
0
10
ns
† P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
1
CLKOUT2
2
3
EXT_INTx, NMI
Intr Flag
4
4
IACK
6
5
Interrupt Number
INUMx
Figure 27. Interrupt Timing
52
POST OFFICE BOX 1443
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TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
EXPANSION BUS SYNCHRONOUS FIFO TIMING
timing requirements for synchronous FIFO interface (see Figure 28, Figure 29, and Figure 30)
-200
-250
-300
NO.
MIN
5
6
tsu(XDV-XFCKH)
th(XFCKH-XDV)
Setup time, read XDx valid before XFCLK high
Hold time, read XDx valid after XFCLK high
UNIT
MAX
3
ns
2.5
ns
switching characteristics for synchronous FIFO interface (see Figure 28, Figure 29, and Figure 30)
’C6202-200,
’C6202-250
PARAMETER
MIN
1
2
3
4
7
8
MAX
MIN
UNIT
MAX
td(XFCKH-XCEV)
td(XFCKH-XAV)
Delay time, XFCLK high to XCEx valid
1.5
5.2
1.5
4.5
ns
Delay time, XFCLK high to XBE[3:0]/XA[5:2] valid†
1.5
5.2
1.5
4.5
ns
td(XFCKH-XOEV)
td(XFCKH-XREV)
Delay time, XFCLK high to XOE valid
1.5
5.2
1.5
4.5
ns
Delay time, XFCLK high to XRE valid
1.5
5.2
1.5
4.5
ns
td(XFCKH-XWEV)
td(XFCKH-XDV)
Delay time, XFCLK high to XWE/XWAIT‡ valid
1.5
5.2
1.5
4.5
ns
4.5
ns
Delay time, XFCLK high to XDx valid
5.2
9
td(XFCKH-XDIV)
Delay time, XFCLK high to XDx invalid
† XBE[3:0]/XA[5:2] operates as address signals XA[5:2] during synchronous FIFO accesses.
‡ XWE/XWAIT operates as the write enable signal XWE during synchronous FIFO accesses.
1.5
1.5
PRODUCT PREVIEW
NO.
’C6202B-250
’C6202B-300
’C6203-250
’C6203-300
’C6204-200
ns
XFCLK
1
1
XCE3†
2
XBE[3:0]/XA[5:2]‡
2
XA1
XA2
XA3
XA4
3
3
XOE
4
4
XRE
XWE/XWAIT§
6
5
XD[31:0]
D1
D2
D3
D4
† FIFO read (glueless) mode only available in XCE3.
‡ XBE[3:0]/XA[5:2] operates as address signals XA[5:2] during synchronous FIFO accesses.
§ XWE/XWAIT operates as the write enable signal XWE during synchronous FIFO accesses.
Figure 28. FIFO Read Timing (Glueless Read Mode)
POST OFFICE BOX 1443
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53
TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
EXPANSION BUS SYNCHRONOUS FIFO TIMING (CONTINUED)
XFCLK
1
1
XCEx
2
XBE[3:0]/XA[5:2]†
2
XA1
XA2
XA3
XA4
3
3
XOE
4
4
XRE
XWE/XWAIT‡
6
5
XD[31:0]
D1
D2
D3
D4
PRODUCT PREVIEW
† XBE[3:0]/XA[5:2] operates as address signals XA[5:2] during synchronous FIFO accesses.
‡ XWE/XWAIT operates as the write enable signal XWE during synchronous FIFO accesses.
Figure 29. FIFO Read Timing
XFCLK
1
1
XCEx
2
XBE[3:0]/XA[5:2]†
2
XA1
XA2
XA3
XA4
XOE
XRE
7
7
XWE/XWAIT‡
9
8
XD[31:0]
D1
D2
† XBE[3:0]/XA[5:2] operates as address signals XA[5:2] during synchronous FIFO accesses.
‡ XWE/XWAIT operates as the write enable signal XWE during synchronous FIFO accesses.
Figure 30. FIFO Write Timing
54
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
D3
D4
TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
EXPANSION BUS ASYNCHRONOUS PERIPHERAL TIMING
timing requirements for asynchronous peripheral cycles†‡§¶ (see Figure 31–Figure 34)
-200
-250
-300
UNIT
MIN
3
tsu(XDV-XREH)
th(XREH-XDV)
Setup time, XDx valid before XRE high
tsu(XRDYH-XREL)
th(XREL-XRDYH)
Setup time, XRDY high before XRE low
tsu(XRDYL-XREL)
th(XREL-XRDYL)
Setup time, XRDY low before XRE low
10
11
tw(XRDYH)
Pulse width, XRDY high
15
tsu(XRDYH-XWEL)
th(XWEL-XRDYH)
Setup time, XRDY high before XWE low
tsu(XRDYL-XWEL)
th(XWEL-XRDYL)
Setup time, XRDY low before XWE low
4
6
7
9
16
18
19
ns
1
ns
–[(RST – 3) * P – 6]
ns
(RST – 3) * P + 2
ns
–[(RST – 3) * P – 6]
ns
(RST – 3) * P + 2
ns
2P
ns
–[(WST – 3) * P – 6]
ns
(WST – 3) * P + 2
ns
–[(WST – 3) * P – 6]
ns
Hold time, XDx valid after XRE high
Hold time, XRDY high after XRE low
Hold time, XRDY low after XRE low
Hold time, XRDY high after XWE low
Hold time, XRDY low after XWE low
MAX
4.5
(WST – 3) * P + 2
ns
† To ensure data setup time, simply program the strobe width wide enough. XRDY is internally synchronized. If XRDY does meet setup or hold
time, it may be recognized in the current cycle or the next cycle. Thus, XRDY can be an asynchronous input.
‡ RS = Read Setup, RST = Read Strobe, RH = Read Hold, WS = Write Setup, WST = Write Strobe, WH = Write Hold. These parameters are
programmed via the XBUS XCE space control registers.
§ P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
¶ The sum of RS and RST (or WS and WST) must be a minimum of 4 in order to use XRDY input to extend strobe width.
switching characteristics for asynchronous peripheral cycles‡§¶# (see Figure 31–Figure 34)
NO.
-200
-250
-300
PARAMETER
MIN
1
UNIT
TYP
MAX
Output setup time, select signals valid to XRE low
RS * P – 2
ns
2
tosu(SELV-XREL)
toh(XREH-SELIV)
Output hold time, XRE low to select signals invalid
RH * P – 2
ns
5
tw(XREL)
Pulse width, XRE low
8
td(XRDYH-XREH)
tosu(SELV-XWEL)
Delay time, XRDY high to XRE high
toh(XWEH-SELIV)
tw(XWEL)
Output hold time, XWE low to select signals invalid
12
13
14
RST * P
3P
Output setup time, select signals valid to XWE low
Pulse width, XWE low
ns
4P + 5
WS * P – 2
ns
ns
WH * P – 2
ns
WST * P
ns
17
td(XRDYH-XWEH) Delay time, XRDY high to XWE high
3P
4P + 5
ns
‡ RS = Read Setup, RST = Read Strobe, RH = Read Hold, WS = Write Setup, WST = Write Strobe, WH = Write Hold. These parameters are
programmed via the XBUS XCE space control registers.
§ P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
¶ The sum of RS and RST (or WS and WST) must be a minimum of 4 in order to use XRDY input to extend strobe width.
# Select signals include: XCEx, XBE[3:0], XA[5:2], XOE; and for writes, include XD[31:0], with the exception that XCEx can stay active for an
additional 7P ns following the end of the cycle.
POST OFFICE BOX 1443
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55
PRODUCT PREVIEW
NO.
TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
EXPANSION BUS ASYNCHRONOUS PERIPHERAL TIMING (CONTINUED)
Setup = 2
Strobe = 3
Hold = 2
CLKOUT1
1
2
1
2
XCEx
XBE[3:0]/
XA[5:2]†
3
4
XD[31:0]
1
2
XOE
5
6
7
PRODUCT PREVIEW
XRE
XWE/XWAIT‡
XRDY§
† XBE[3:0]/XA[5:2] operates as address signals XA[5:2] during expansion bus asynchronous peripheral accesses.
‡ XWE/XWAIT operates as the write enable signal XWE during expansion bus asynchronous peripheral accesses.
§ XRDY operates as active-high ready input during expansion bus asynchronous peripheral accesses.
Figure 31. Expansion Bus Asynchronous Peripheral Read Timing (XRDY Not Used)
Setup = 2
Strobe = 3
Not Ready
Hold = 2
CLKOUT1
1
2
1
2
XCEx
XBE[3:0]/
XA[5:2]†
3
4
XD[31:0]
1
2
XOE
8
10
9
XRE
XWE/XWAIT‡
11
XRDY§
† XBE[3:0]/XA[5:2] operates as address signals XA[5:2] during expansion bus asynchronous peripheral accesses.
‡ XWE/XWAIT operates as the write enable signal XWE during expansion bus asynchronous peripheral accesses.
§ XRDY operates as active-high ready input during expansion bus asynchronous peripheral accesses.
Figure 32. Expansion Bus Asynchronous Peripheral Read Timing (XRDY Used)
56
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
EXPANSION BUS ASYNCHRONOUS PERIPHERAL TIMING (CONTINUED)
Setup = 2
Strobe = 3
Hold = 2
CLKOUT1
12
13
12
13
12
13
XCEx
XBE[3:0]/
XA[5:2]†
XD[31:0]
XOE
XRE
15
16
14
XWE/XWAIT‡
PRODUCT PREVIEW
XRDY§
† XBE[3:0]/XA[5:2] operates as address signals XA[5:2] during expansion bus asynchronous peripheral accesses.
‡ XWE/XWAIT operates as the write enable signal XWE during expansion bus asynchronous peripheral accesses.
§ XRDY operates as active-high ready input during expansion bus asynchronous peripheral accesses.
Figure 33. Expansion Bus Asynchronous Peripheral Write Timing (XRDY Not Used)
Setup = 2 Strobe = 3
Not Ready
Hold = 2
CLKOUT1
12
13
12
13
12
13
XCEx
XBE[3:0]/
XA[5:2]†
XD[31:0]
XOE
XRE
17
18
19
XWE/XWAIT‡
11
XRDY§
† XBE[3:0]/XA[5:2] operates as address signals XA[5:2] during expansion bus asynchronous peripheral accesses.
‡ XWE/XWAIT operates as the write enable signal XWE during expansion bus asynchronous peripheral accesses.
§ XRDY operates as active-high ready input during expansion bus asynchronous peripheral accesses.
Figure 34. Expansion Bus Asynchronous Peripheral Write Timing (XRDY Used)
POST OFFICE BOX 1443
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57
TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
EXPANSION BUS SYNCHRONOUS HOST PORT TIMING
timing requirements with external device as bus master (see Figure 35 and Figure 36)
-200
-250
-300
NO.
MIN
1
2
3
4
5
6
7
8
PRODUCT PREVIEW
9
10
16
17
18
19
UNIT
MAX
tsu(XCSV-XCKIH)
th(XCKIH-XCS)
Setup time, XCS valid before XCLKIN high
3.5
ns
Hold time, XCS valid after XCLKIN high
2.8
ns
tsu(XAS-XCKIH)
th(XCKIH-XAS)
Setup time, XAS valid before XCLKIN high
3.5
ns
Hold time, XAS valid after XCLKIN high
2.8
ns
tsu(XCTL-XCKIH)
th(XCKIH-XCTL)
Setup time, XCNTL valid before XCLKIN high
3.5
ns
Hold time, XCNTL valid after XCLKIN high
2.8
ns
tsu(XWR-XCKIH)
th(XCKIH-XWR)
Setup time, XW/R valid before XCLKIN high†
Hold time, XW/R valid after XCLKIN high†
3.5
ns
2.8
ns
tsu(XBLTV-XCKIH)
th(XCKIH-XBLTV)
Setup time, XBLAST valid before XCLKIN high‡
Hold time, XBLAST valid after XCLKIN high‡
3.5
ns
2.8
ns
tsu(XBEV-XCKIH)
th(XCKIH-XBEV)
Setup time, XBE[3:0]/XA[5:2] valid before XCLKIN high§
Hold time, XBE[3:0]/XA[5:2] valid after XCLKIN high§
3.5
ns
2.8
ns
tsu(XD-XCKIH)
th(XCKIH-XD)
Setup time, XDx valid before XCLKIN high
3.5
ns
Hold time, XDx valid after XCLKIN high
2.8
ns
† XW/R input/output polarity selected at boot.
‡ XBLAST input polarity selected at boot.
§ XBE[3:0]/XA[5:2] operates as byte enables XBE[3:0] during host-port accesses.
switching characteristics with external device as bus master¶ (see Figure 35 and Figure 36)
NO.
-200
-250
-300
PARAMETER
MIN
11
12
13
14
15
20
Delay time, XCLKIN high to XDx low impedance
0
td(XCKIH-XDIV)
td(XCKIH-XDHZ)
Delay time, XCLKIN high to XDx invalid
5
Delay time, XCLKIN high to XDx high impedance
Delay time, XCLKIN high to XRDY valid#
5
Delay time, XCLKIN high to XDx valid
Delay time, XCLKIN high to XRDY low impedance
td(XCKIH-XRYHZ)
Delay time, XCLKIN high to XRDY high impedance#
¶ P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
# XRDY operates as active-low ready input/output during host-port accesses.
21
58
MAX
td(XCKIH-XDLZ)
td(XCKIH-XDV)
td(XCKIH-XRY)
td(XCKIH-XRYLZ)
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
UNIT
ns
16.5
ns
ns
4P
ns
16.5
ns
5
16.5
ns
2P + 5
3P + 16.5
ns
TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
EXPANSION BUS SYNCHRONOUS HOST PORT TIMING (CONTINUED)
XCLKIN
2
1
XCS
4
3
XAS
6
5
XCNTL
8
7
XW/R†
8
7
XW/R†
XBE[3:0]/XA[5:2]‡
10
9
XBLAST§
PRODUCT PREVIEW
10
9
XBLAST§
11
D1
XD[31:0]
20
13
14
12
D2
D3
15
D4
15
21
XRDY¶
† XW/R input/output polarity selected at boot
‡ XBE[3:0]/XA[5:2] operates as byte enables XBE[3:0] during host-port accesses.
§ XBLAST input polarity selected at boot
¶ XRDY operates as active-low ready input/output during host-port accesses.
Figure 35. External Host as Bus Master—Read
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
59
TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
EXPANSION BUS SYNCHRONOUS HOST PORT TIMING (CONTINUED)
XCLKIN
2
1
XCS
4
3
XAS
6
5
XCNTL
8
7
XW/R†
8
7
XW/R†
17
16
XBE[3:0]/XA[5:2]‡
XBE1
XBE2
XBE3
XBE4
10
PRODUCT PREVIEW
9
XBLAST§
10
9
XBLAST§
19
18
D1
XD[31:0]
20
D2
D3
D4
15
XRDY¶
† XW/R input/output polarity selected at boot
‡ XBE[3:0]/XA[5:2] operates as byte enables XBE[3:0] during host-port accesses.
§ XBLAST input polarity selected at boot
¶ XRDY operates as active-low ready input/output during host-port accesses.
Figure 36. External Host as Bus Master—Write
60
POST OFFICE BOX 1443
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15
21
TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
EXPANSION BUS SYNCHRONOUS HOST PORT TIMING (CONTINUED)
timing requirements with ’C62x as bus master (see Figure 37, Figure 38, and Figure 39)
-200
-250
-300
NO.
MIN
9
UNIT
MAX
tsu(XDV-XCKIH)
th(XCKIH-XDV)
Setup time, XDx valid before XCLKIN high
3.5
ns
Hold time, XDx valid after XCLKIN high
2.8
ns
tsu(XRY-XCKIH)
th(XCKIH-XRY)
Setup time, XRDY valid before XCLKIN high†
Hold time, XRDY valid after XCLKIN high†
3.5
ns
2.8
ns
tsu(XBFF-XCKIH)
th(XCKIH-XBFF)
Setup time, XBOFF valid before XCLKIN high
3.5
ns
15
Hold time, XBOFF valid after XCLKIN high
† XRDY operates as active-low ready input/output during host-port accesses.
2.8
ns
10
11
12
14
NO.
PARAMETER
-200
-250
-300
MIN
1
2
3
4
5
6
7
8
UNIT
MAX
td(XCKIH-XASV)
td(XCKIH-XWRV)
Delay time, XCLKIN high to XAS valid
5
16.5
ns
Delay time, XCLKIN high to XW/R valid‡
5
16.5
ns
td(XCKIH-XBLTV)
td(XCKIH-XBEV)
Delay time, XCLKIN high to XBLAST valid§
5
16.5
ns
Delay time, XCLKIN high to XBE[3:0]/XA[5:2] valid¶
5
16.5
ns
td(XCKIH-XDLZ)
td(XCKIH-XDV)
Delay time, XCLKIN high to XDx low impedance
0
td(XCKIH-XDIV)
td(XCKIH-XDHZ)
Delay time, XCLKIN high to XDx invalid
Delay time, XCLKIN high to XDx valid
16.5
5
Delay time, XCLKIN high to XDx high impedance
13
td(XCKIH-XWTV)
Delay time, XCLKIN high to XWE/XWAIT valid#
‡ XW/R input/output polarity selected at boot.
§ XBLAST output polarity is always active low.
¶ XBE[3:0]/XA[5:2] operates as byte enables XBE[3:0] during host-port accesses.
# XWE/XWAIT operates as XWAIT output signal during host-port accesses.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
ns
5
ns
ns
4P
ns
16.5
ns
61
PRODUCT PREVIEW
switching characteristics with ’C62x as bus master (see Figure 37, Figure 38, and Figure 39)
TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
EXPANSION BUS SYNCHRONOUS HOST PORT TIMING (CONTINUED)
XCLKIN
1
1
XAS
2
2
XW/R†
XW/R†
3
3
XBLAST‡
4
4
XBE[3:0]/XA[5:2]§
5
7
6
AD
XD[31:0]
BE
9
8
10
D2
D1
D3
D4
11
12
PRODUCT PREVIEW
XRDY
13
13
XWE/XWAIT¶
† XW/R input/output polarity selected at boot
‡ XBLAST output polarity is always active low.
§ XBE[3:0]/XA[5:2] operates as byte enables XBE[3:0] during host-port accesses.
¶ XWE/XWAIT operates as XWAIT output signal during host-port accesses.
Figure 37. ’C62x as Bus Master—Read
XCLKIN
1
1
XAS
XW/R†
2
2
XW/R†
3
3
XBLAST‡
4
4
6
7
XBE[3:0]/XA[5:2]§
5
XD[31:0]
Addr
8
D1
D2
D3
D4
11
XRDY
12
13
13
XWE/XWAIT¶
† XW/R input/output polarity selected at boot
‡ XBLAST output polarity is always active low.
§ XBE[3:0]/XA[5:2] operates as byte enables XBE[3:0] during host-port accesses.
¶ XWE/XWAIT operates as XWAIT output signal during host-port accesses.
Figure 38. ’C62x as Bus Master—Write
62
POST OFFICE BOX 1443
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TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
EXPANSION BUS SYNCHRONOUS HOST PORT TIMING (CONTINUED)
XCLKIN
1
1
XAS
XW/R†
2
2
4
4
XW/R†
XBLAST‡
XBE[3:0]/XA[5:2]§
6
7
5
XD[31:0]
8
Addr
D1
11
D2
12
XRDY
15
PRODUCT PREVIEW
14
XBOFF
XHOLD¶
XHOLDA¶
XHOLD#
XHOLDA#
† XW/R input/output polarity selected at boot
‡ XBLAST output polarity is always active low.
§ XBE[3:0]/XA[5:2] operates as byte enables XBE[3:0] during host-port accesses.
¶ Internal arbiter enabled
# External arbiter enabled
|| This diagram illustrates XBOFF timing. Bus arbitration timing is shown in Figure 42 and Figure 43.
Figure 39. ’C62x as Bus Master—BOFF Operation||
POST OFFICE BOX 1443
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63
TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
EXPANSION BUS ASYNCHRONOUS HOST PORT TIMING
timing requirements with external device as asynchronous bus master† (see Figure 40 and
Figure 41)
-200
-250
-300
NO.
MIN
MAX
1
tw(XCSL)
Pulse duration, XCS low
4P
ns
2
tw(XCSH)
tsu(XSEL-XCSL)
Pulse duration, XCS high
4P
ns
1
ns
3
ns
3
4
10
11
12
13
14
PRODUCT PREVIEW
UNIT
th(XCSL-XSEL)
th(XRYL-XCSL)
Setup time, expansion bus select signals‡ valid before XCS low
Hold time, expansion bus select signals‡ valid after XCS low
P + 1.5
ns
tsu(XBEV-XCSH)
th(XCSH-XBEV)
Hold time, XCS low after XRDY low
Setup time, XBE[3:0]/XA[5:2] valid before XCS high§
Hold time, XBE[3:0]/XA[5:2] valid after XCS high§
1
ns
3
ns
tsu(XDV-XCSH)
th(XCSH-XDV)
Setup time, XDx valid before XCS high
1
ns
Hold time, XDx valid after XCS high
3
ns
† P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
‡ Expansion bus select signals include XCNTL and XR/W.
§ XBE[3:0]/XA[5:2] operates as byte enables XBE[3:0] during host-port accesses.
switching characteristics with external device as asynchronous bus master† (see Figure 40 and
Figure 41)
NO.
PARAMETER
-200
-250
-300
MIN
5
6
7
8
td(XCSL-XDLZ)
td(XCSH-XDIV)
Delay time, XCS low to XDx low impedance
0
Delay time, XCS high to XDx invalid
0
td(XCSH-XDHZ)
td(XRYL-XDV)
Delay time, XCS high to XDx high impedance
Delay time, XRDY low to XDx valid
9
td(XCSH-XRYH)
Delay time, XCS high to XRDY high
† P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
64
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
UNIT
MAX
ns
12
ns
4P
ns
–4
1
ns
0
12
ns
TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
EXPANSION BUS ASYNCHRONOUS HOST PORT TIMING (CONTINUED)
1
1
2
10
10
XCS
3
3
4
4
XCNTL
XBE[3:0]/XA[5:2]†
3
3
4
4
XR/W‡
3
3
4
4
XR/W‡
5
7
6
8
5
7
6
8
Word
XD[31:0]
9
9
PRODUCT PREVIEW
XRDY
† XBE[3:0]/XA[5:2] operates as byte enables XBE[3:0] during host-port accesses.
‡ XW/R input/output polarity selected at boot
Figure 40. External Device as Asynchronous Master—Read
1
10
2
10
1
XCS
3
3
4
4
XCNTL
11
11
12
12
XBE[3:0]/XA[5:2]†
3
3
4
4
XR/W‡
3
3
4
4
XR/W‡
13
XD[31:0]
14
13
14
word
Word
9
9
XRDY
† XBE[3:0]/XA[5:2] operates as byte enables XBE[3:0] during host-port accesses.
‡ XW/R input/output polarity selected at boot
Figure 41. External Device as Asynchronous Master—Write
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
65
TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
XHOLD/XHOLDA TIMING
timing requirements for expansion bus arbitration (internal arbiter enabled)† (see Figure 42)
-200
-250
-300
NO.
MIN
3
toh(XHDAH-XHDH)
Output hold time, XHOLD high after XHOLDA high
† P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
UNIT
MAX
P
ns
switching characteristics for expansion bus arbitration (internal arbiter enabled)†‡ (see Figure 42)
NO.
-200
-250
-300
PARAMETER
MIN
1
PRODUCT PREVIEW
2
4
5
tR(XHDH-XBHZ)
td(XBHZ-XHDAH)
Response time, XHOLD high to XBus high impedance
tR(XHDL-XHDAL)
td(XHDAL-XBLZ)
Response time, XHOLD low to XHOLDA low
3P
MAX
§
ns
0
2P
ns
Delay time, XBus high impedance to XHOLDA high
3P
Delay time, XHOLDA low to XBus low impedance
0
† P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
‡ XBus consists of XBE[3:0]/XA[5:2], XAS, XW/R, and XBLAST.
§ All pending XBus transactions are allowed to complete before XHOLDA is asserted.
External Requestor
Owns Bus
DSP Owns Bus
DSP Owns Bus
3
XHOLD (input)
2
4
XHOLDA (output)
1
XBus†
5
’C62x
’C62x
† XBus consists of XBE[3:0]/XA[5:2], XAS, XW/R, and XBLAST.
Figure 42. Expansion Bus Arbitration—Internal Arbiter Enabled
66
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
UNIT
ns
2P
ns
TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
XHOLD/XHOLDA TIMING (CONTINUED)
switching characteristics for expansion bus arbitration (internal arbiter disabled)† (see Figure 43)
NO.
-200
-250
-300
PARAMETER
MIN
1
2
td(XHDAH-XBLZ)
td(XBHZ-XHDL)
Delay time, XHOLDA high to XBus low impedance‡
Delay time, XBus high impedance to XHOLD low‡
UNIT
MAX
2P 2P + 10
0
2P
ns
ns
† P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
‡ XBus consists of XBE[3:0]/XA[5:2], XAS, XW/R, and XBLAST.
2
XHOLD (output)
XHOLDA (input)
1
XBus†
’C62x
PRODUCT PREVIEW
† XBus consists of XBE[3:0]/XA[5:2], XAS, XW/R, and XBLAST.
Figure 43. Expansion Bus Arbitration—Internal Arbiter Disabled
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
67
TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
MULTICHANNEL BUFFERED SERIAL PORT TIMING
timing requirements for McBSP†‡ (see Figure 44)
-200
-250
-300
NO.
2
PRODUCT PREVIEW
3
tc(CKRX)
tw(CKRX)
Cycle time, CLKR/X
CLKR/X ext
MIN
2P§
Pulse duration, CLKR/X high or CLKR/X low
CLKR/X ext
P – 1¶
5
tsu(FRH-CKRL)
Setup time,
time external FSR high before CLKR low
6
th(CKRL-FRH)
Hold time,
time external FSR high after CLKR low
7
tsu(DRV-CKRL)
time DR valid before CLKR low
Setup time,
8
th(CKRL-DRV)
Hold time,
time DR valid after CLKR low
10
tsu(FXH-CKXL)
Setup time,
time external FSX high before CLKX low
11
th(CKXL-FXH)
Hold time,
time external FSX high after CLKX low
CLKR int
9
CLKR ext
2
CLKR int
6
CLKR ext
3
CLKR int
8
CLKR ext
0.5
CLKR int
3
CLKR ext
4
CLKX int
9
CLKX ext
2
CLKX int
6
CLKX ext
3
UNIT
MAX
ns
ns
ns
ns
ns
ns
ns
ns
† CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
‡ P = 1/CPU clock frequency in ns.
§ The maximum McBSP bit rate is 100 MHz; therefore, the minimum CLKR/X clock cycle is either twice the CPU cycle time (2P), or 10 ns (100 MHz),
whichever value is larger. For example, when running parts at 250 MHz (P = 4 ns), use 10 ns as the minimum CLKR/X clock cycle (by setting
the appropriate CLKGDV ratio or external clock source). When running parts at 100 MHz (P = 10 ns), use 2P = 20 ns (50 MHz) as the minimum
CLKR/X clock cycle. The maximum McBSP bit rate applies to the following hardware configuration: the serial port is a master of the clock and
frame syncs (with CLKR connected to CLKX, FSR connected to FSX, CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data delay 1 or 2 mode
(R/XDATDLY = 01b or 10b) and the other device the McBSP communicates to is a slave.
¶ The minimum CLKR/X pulse duration is either (P – 1) or 4 ns, whichever is larger. For example, when running parts at 250 MHz (P = 4 ns), use
4 ns as the minimum CLKR/X pulse duration. When running parts at 100 MHz (P = 10 ns), use (P – 1) = 9 ns as the minimum CLKR/X pulse
duration.
68
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
switching characteristics for McBSP†‡ (see Figure 44)
PARAMETER
Delay time, CLKS high to CLKR/X high for internal
CLKR/X generated from CLKS input
UNIT
MIN
MAX
4
16
1
td(CKSH-CKRXH)
2
tc(CKRX)
tw(CKRX)
Cycle time, CLKR/X
CLKR/X int
2P§¶
3
Pulse duration, CLKR/X high or CLKR/X low
CLKR/X int
C – 1#
C + 1#
ns
4
td(CKRH-FRV)
Delay time, CLKR high to internal FSR valid
CLKR int
–2
3
ns
CLKX int
–2
3
CLKX ext
3
9
CLKX int
–1
5
CLKX ext
2
9
CLKX int
–1
4
CLKX ext
2
11
FSX int
–1
5
FSX ext
0
10
9
td(CKXH-FXV)
Delay time,
time CLKX high to internal FSX valid
12
tdis(CKXH-DXHZ)
Disable time, DX high impedance
im edance following last data bit from
CLKX high
13
td(CKXH-DXV)
Delay time,
time CLKX high to DX valid
14
td(FXH-DXV)
Delay time, FSX high to DX valid
ONLY applies when in data delay 0 (XDATDLY = 00b) mode.
ns
ns
ns
ns
ns
ns
† CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
‡ Minimum delay times also represent minimum output hold times.
§ P = 1/CPU clock frequency in ns.
¶ The maximum McBSP bit rate is 100 MHz; therefore, the minimum CLKR/X clock cycle is either twice the CPU cycle time (2P), or 10 ns (100 MHz),
whichever value is larger. For example, when running parts at 250 MHz (P = 4 ns), use 10 ns as the minimum CLKR/X clock cycle (by setting
the appropriate CLKGDV ratio or external clock source). When running parts at 100 MHz (P = 10 ns), use 2P = 20 ns (50 MHz) as the minimum
CLKR/X clock cycle. The maximum McBSP bit rate applies to the following hardware configuration: the serial port is a master of the clock and
frame syncs (with CLKR connected to CLKX, FSR connected to FSX, CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data delay 1 or 2 mode
(R/XDATDLY = 01b or 10b) and the other device the McBSP communicates to is a slave.
# C = H or L
S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the 100 MHz limit.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
69
PRODUCT PREVIEW
NO.
-200
-250
-300
TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
CLKS
1
2
3
3
CLKR
4
4
FSR (int)
5
6
FSR (ext)
7
DR
8
Bit(n-1)
(n-2)
(n-3)
2
3
3
CLKX
PRODUCT PREVIEW
9
FSX (int)
11
10
FSX (ext)
FSX (XDATDLY=00b)
12
DX
Bit 0
14
13
Bit(n-1)
13
(n-2)
Figure 44. McBSP Timings
70
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
(n-3)
TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
timing requirements for FSR when GSYNC = 1 (see Figure 45)
-200
-250
-300
NO.
MIN
2
tsu(FRH-CKSH)
th(CKSH-FRH)
MAX
Setup time, FSR high before CLKS high
4
ns
Hold time, FSR high after CLKS high
4
ns
CLKS
1
2
FSR external
CLKR/X (no need to resync)
CLKR/X(needs resync)
PRODUCT PREVIEW
1
UNIT
Figure 45. FSR Timing When GSYNC = 1
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
71
TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0†‡ (see Figure 46)
-200
-250
-300
NO.
MASTER
MIN
4
tsu(DRV-CKXL)
th(CKXL-DRV)
Setup time, DR valid before CLKX low
UNIT
SLAVE
MAX
MIN
12
5
Hold time, DR valid after CLKX low
4
† P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
MAX
2 – 3P
ns
5 + 6P
ns
PRODUCT PREVIEW
switching characteristics for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0†‡
(see Figure 46)
NO.
-200
-250
-300
PARAMETER
MASTER§
2
th(CKXL-FXL)
td(FXL-CKXH)
Hold time, FSX low after CLKX low¶
Delay time, FSX low to CLKX high#
3
td(CKXH-DXV)
Delay time, CLKX high to DX valid
6
tdis(CKXL-DXHZ)
Disable time, DX high impedance following last data bit from
CLKX low
7
tdis(FXH-DXHZ)
Disable time, DX high impedance following last data bit from FSX
high
1
UNIT
SLAVE
MIN
MAX
MIN
T–2
T+3
ns
L–2
L+3
ns
–3
4
L–2
L+3
3P + 4
MAX
5P + 17
ns
ns
P+3
3P + 17
ns
8
td(FXL-DXV)
Delay time, FSX low to DX valid
2P + 2 4P + 17
ns
† P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
§ S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the 100 MHz limit.
¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
# FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
72
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
CLKX
1
2
FSX
7
6
DX
8
3
Bit 0
Bit(n-1)
4
Bit 0
(n-3)
(n-4)
5
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 46. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
PRODUCT PREVIEW
DR
(n-2)
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
73
TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0†‡ (see Figure 47)
-200
-250
-300
NO.
MASTER
MIN
4
tsu(DRV-CKXH)
th(CKXH-DRV)
Setup time, DR valid before CLKX high
UNIT
SLAVE
MAX
MIN
12
5
Hold time, DR valid after CLKX high
4
† P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
MAX
2 – 3P
ns
5 + 6P
ns
PRODUCT PREVIEW
switching characteristics for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0†‡
(see Figure 47)
NO.
-200
-250
-300
PARAMETER
MASTER§
MIN
2
th(CKXL-FXL)
td(FXL-CKXH)
Hold time, FSX low after CLKX low¶
Delay time, FSX low to CLKX high#
3
td(CKXL-DXV)
tdis(CKXL-DXHZ)
1
6
UNIT
SLAVE
MAX
MIN
MAX
L–2
L+3
ns
T–2
T+3
ns
Delay time, CLKX low to DX valid
–2
4
3P + 4
5P + 17
ns
Disable time, DX high impedance following last data bit from
CLKX low
–2
4
3P + 3
5P + 17
ns
7
td(FXL-DXV)
Delay time, FSX low to DX valid
H–2 H+4
2P + 2 4P + 17
ns
† P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
§ S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the 100 MHz limit.
¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
# FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
74
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
CLKX
1
2
6
Bit 0
7
FSX
DX
3
Bit(n-1)
4
Bit 0
(n-3)
(n-4)
5
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 47. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
PRODUCT PREVIEW
DR
(n-2)
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
75
TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1†‡ (see Figure 48)
-200
-250
-300
NO.
MASTER
MIN
4
tsu(DRV-CKXH)
th(CKXH-DRV)
Setup time, DR valid before CLKX high
UNIT
SLAVE
MAX
MIN
12
5
Hold time, DR valid after CLKX high
4
† P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
MAX
2 – 3P
ns
5 + 6P
ns
PRODUCT PREVIEW
switching characteristics for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1†‡
(see Figure 48)
NO.
-200
-250
-300
PARAMETER
MASTER§
MIN
2
th(CKXH-FXL)
td(FXL-CKXL)
Hold time, FSX low after CLKX high¶
Delay time, FSX low to CLKX low#
3
td(CKXL-DXV)
Delay time, CLKX low to DX valid
6
tdis(CKXH-DXHZ)
Disable time, DX high impedance following last data bit from
CLKX high
7
tdis(FXH-DXHZ)
Disable time, DX high impedance following last data bit from
FSX high
1
UNIT
SLAVE
MAX
MIN
MAX
T–2
T+3
ns
H–2
H+3
ns
–2
4
H–2
H+3
3P + 4
5P + 17
ns
ns
P+3
3P + 17
ns
8
td(FXL-DXV)
Delay time, FSX low to DX valid
2P + 2 4P + 17
ns
† P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
§ S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the 100 MHz limit.
¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
# FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
76
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
CLKX
1
2
FSX
7
6
DX
8
3
Bit 0
Bit(n-1)
4
Bit 0
(n-3)
(n-4)
5
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 48. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
PRODUCT PREVIEW
DR
(n-2)
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
77
TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1†‡ (see Figure 49)
-200
-250
-300
NO.
MASTER
MIN
4
tsu(DRV-CKXL)
th(CKXL-DRV)
Setup time, DR valid before CLKX low
UNIT
SLAVE
MAX
MIN
12
5
Hold time, DR valid after CLKX low
4
† P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
MAX
2 – 3P
ns
5 + 6P
ns
PRODUCT PREVIEW
switching characteristics for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1†‡
(see Figure 49)
NO.
-200
-250
-300
PARAMETER
MASTER§
UNIT
SLAVE
MIN
MAX
MIN
MAX
H–2
H+3
ns
T–2
T+2
ns
2
th(CKXH-FXL)
td(FXL-CKXL)
Hold time, FSX low after CLKX high¶
Delay time, FSX low to CLKX low#
3
td(CKXH-DXV)
Delay time, CLKX high to DX valid
–3
4
3P + 4
5P + 17
ns
tdis(CKXH-DXHZ)
Disable time, DX high impedance following last data bit from
CLKX high
–2
4
3P + 3
5P + 17
ns
1
6
7
td(FXL-DXV)
Delay time, FSX low to DX valid
L–2
L+5
2P + 2 4P + 17
ns
† P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
§ S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the 100 MHz limit.
¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
# FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
78
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TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
CLKX
1
2
FSX
7
6
DX
3
Bit 0
Bit(n-1)
4
Bit 0
(n-3)
(n-4)
5
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 49. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
PRODUCT PREVIEW
DR
(n-2)
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79
TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
DMAC, TIMER, POWER-DOWN TIMING
switching characteristics for DMAC outputs† (see Figure 50)
NO.
-200
-250
-300
PARAMETER
MIN
1
tw(DMACH) Pulse duration, DMAC high
† P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
UNIT
MAX
2P – 3
ns
1
DMAC[3:0]
Figure 50. DMAC Timing
PRODUCT PREVIEW
timing requirements for timer inputs† (see Figure 51)
-200
-250
-300
NO.
MIN
1
2
tw(TINPH)
tw(TINPL)
UNIT
MAX
Pulse duration, TINP high
2P
ns
Pulse duration, TINP low
2P
ns
† P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
switching characteristics for timer outputs† (see Figure 51)
NO.
-200
-250
-300
PARAMETER
MIN
3
4
tw(TOUTH)
tw(TOUTL)
MAX
Pulse duration, TOUT high
2P – 3
ns
Pulse duration, TOUT low
2P – 3
ns
† P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
2
1
TINPx
4
3
TOUTx
Figure 51. Timer Timing
80
UNIT
POST OFFICE BOX 1443
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TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
DMAC, TIMER, POWER-DOWN TIMING (CONTINUED)
switching characteristics for power-down outputs† (see Figure 52)
NO.
-200
-250
-300
PARAMETER
MIN
1
tw(PDH)
Pulse duration, PD high
† P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
2P
UNIT
MAX
ns
1
PD
PRODUCT PREVIEW
Figure 52. Power-Down Timing
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81
TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
JTAG TEST-PORT TIMING
timing requirements for JTAG test port (see Figure 53)
-200
-250
-300
NO.
MIN
1
UNIT
MAX
Cycle time, TCK
50
ns
3
tc(TCK)
tsu(TDIV-TCKH)
Setup time, TDI/TMS/TRST valid before TCK high
11
ns
4
th(TCKH-TDIV)
Hold time, TDI/TMS/TRST valid after TCK high
9
ns
switching characteristics for JTAG test port (see Figure 53)
NO.
PRODUCT PREVIEW
2
-200
-250
-300
PARAMETER
td(TCKL-TDOV)
Delay time, TCK low to TDO valid
MIN
MAX
–4.5
12
1
TCK
2
2
TDO
4
3
TDI/TMS/TRST
Figure 53. JTAG Test-Port Timing
82
POST OFFICE BOX 1443
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UNIT
ns
TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
MECHANICAL DATA
GJL (S-PBGA-N352)
PLASTIC BALL GRID ARRAY
27,20
SQ
26,80
25,20
SQ
24,80
25,00 TYP
1,00
16,30 NOM
0,50
AF
AE
AD
AC
AB
AA
Y
1,00
W
V
16,30 NOM
U
T
R
P
N
M
0,50
PRODUCT PREVIEW
L
K
J
H
G
F
E
D
C
B
A
1
3
2
Heat Slug
5
4
7
6
9
8
11 13 15 17 19 21 23 25
10 12 14 16 18 20 22 24 26
See Note E
3,50 MAX
1,00 NOM
Seating Plane
0,70
0,50
NOTES: A.
B.
C.
D.
E.
F.
∅ 0,10 M
0,60
0,40
0,15
4173516-2/D 01/00
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Thermally enhanced plastic package with heat slug (HSL)
Flip chip application only
Possible protrusion in this area, but within 3,50 max package height specification
Falls within JEDEC MO-151/AAL-1
thermal resistance characteristics (S-PBGA package)
NO
1
°C/W
Air Flow LFPM†
N/A
RΘJC
RΘJA
Junction-to-case
0.47
Junction-to-free air
14.2
0
RΘJA
RΘJA
Junction-to-free air
12.3
100
Junction-to-free air
10.2
250
RΘJA
Junction-to-free air
† LFPM = Linear Feet Per Minute
8.6
500
2
3
4
5
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83
TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
MECHANICAL DATA
GLS (S-PBGA-N384)
PLASTIC BALL GRID ARRAY
18,10
SQ
17,90
16,80 TYP
0,80
0,40
AB
AA
Y
W
V
0,80
U
T
R
P
N
M
L
K
0,40
J
H
PRODUCT PREVIEW
G
F
E
D
C
B
A
3
1
2
5
4
9
7
6
8
11 13 15 17 19 21
10 12 14 16 18 20 22
Heat Slug
2,80 MAX
1,00 NOM
Seating Plane
0,55
0,45
0,10 M
0,45
0,35
0,15
4188959/B 12/98
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Thermally enhanced plastic package with heat slug (HSL)
Flip chip application only
thermal resistance characteristics (S-PBGA package)
NO
1
°C/W
Air Flow LFPM†
N/A
RΘJC
RΘJA
Junction-to-case
0.85
Junction-to-free air
21.6
0
RΘJA
RΘJA
Junction-to-free air
17.9
100
Junction-to-free air
14.2
250
RΘJA
Junction-to-free air
† LFPM = Linear Feet Per Minute
11.8
500
2
3
4
5
84
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TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
MECHANICAL DATA
GLW (S-PBGA-N340)
PLASTIC BALL GRID ARRAY (CAVITY DOWN)
18,10
SQ
17,90
16,80 TYP
0,80
0,40
AB
AA
Y
W
V
0,80
U
T
R
P
N
M
L
K
0,40
J
H
G
PRODUCT PREVIEW
F
E
D
C
B
A
3
1
2
5
4
9
7
6
8
10
11 13 15 17 19 21
12 14 16 18 20 22
Heat Slug
2,80 MAX
Seating Plane
0,55
0,45
∅ 0,10 M
0,45
0,35
0,15
4200619/A 10/99
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Thermally enhanced plastic package with heat slug (HSL)
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
85
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