TB62747AFG/AFNG/AFNAG/BFNAG TOSHIBA Bi-CMOS Integrated Circuit Silicon Monolithic TB62747AFG,TB62747AFNG, TB62747AFNAG,TB62747BFNAG 16-Output Constant Current LED Driver TB62747AFG The TB62747 series is comprised of constant-current drivers designed for LEDs and LED panel displays. The regulated current sources are designed to provide a constant current, which is adjustable through one external resistor. The TB62747 series incorporates 16 channels of shift registers, latches, AND gates and constant-current outputs. Fabricated using the Bi-CMOS process, the TB62747 series satisfies the system requirement of high-speed data transmission. The TB62747 series is RoHS compatible SSOP24-P-300-1.00B TB62747AFNG SSOP24-P-300-0.65A TB62747AFNAG/BFNAG SSOP24-P-150-0.64 Features Weight SSOP24-P-300-1.00B : 0.29 g (typ.) SSOP24-P-300-0.65A : 0.14 g (typ.) SSOP24-P-150-0.64: 0.14 g (typ.) • Power supply voltages: VDD = 3.3 V to 5.0 V • 16-output built-in • Output current setting range : 1.5 to 35 mA @ VDD = 3.3 V, VO = 0.4 to 1.0 V • Constant current output voltage: VO = 26 V (max) • Current accuracy (@ REXT = 1.2 kΩ, VO = 0.4 V, VDD = 3.3 V, 5.0 V) : Between outputs: ± 1.5 % (max) : Between devices: ± 1.5 % (max) • Fast response of output current : twOE(L) = 100 ns (min) • Control data format: serial-in, parallel-out • Input signal voltage level: 3.3 V and 5 V CMOS interfaces (Schmitt trigger input) • Serial data transfer rate: 25 MHz (max) @cascade connection : 1.5 to 45 mA @ VDD = 5.0 V, VO = 0.4 to 1.2 V • Operation temperature range: Topr = −40 to 85 °C • Power on reset (POR) • Package : AFG type : AFNG type : AFNAG type : BFNAG type : SSOP24-P-300-1.00B : SSOP24-P-300-0.65A : SSOP24-P-150-0.64 : SSOP24-P-150-0.64 1 2009-01-21 TB62747AFG/AFNG/AFNAG/BFNAG Pin Assignment (top view) TB62747AFG/AFNG/AFNAG TB62747BFNAG GND VDD OUT14 OUT13 SIN REXT OUT15 OUT12 SCK SOUT OE OUT11 SOUT OUT10 SLAT OE OUT0 OUT15 REXT OUT9 OUT1 OUT14 VDD OUT8 OUT2 OUT13 GND OUT7 OUT3 OUT12 SIN OUT6 OUT4 OUT11 SCK OUT5 OUT5 OUT10 SLAT OUT4 OUT6 OUT9 OUT0 OUT3 OUT7 OUT8 OUT1 OUT2 Note1: Short circuiting an output pin to a power supply pin (VDD or VLED*), or short-circuiting the REXT pin to the GND pin will likely exceed the rating, which in turn may result in smoldering and/or permanent damage. Please keep this in mind when determining the wiring layout for the power supply and GND pins. *VLED: LED power supply 2 2009-01-21 TB62747AFG/AFNG/AFNAG/BFNAG Block Diagram OUT0 OUT1 OUT15 VDD OUT0 OUT1 OUT15 B.G Constant current outputs POR GND REXT OE SLAT SIN G D0 Q15 Q0 Q1 16-bit D-latch D0 D1 D15 R Q15 Q0 Q1 16-bit shift register Q15 R SOUT SCK 3 2009-01-21 TB62747AFG/AFNG/AFNAG/BFNAG Truth Table SCK SLAT OE SIN OUT0 … OUT7 … OUT15 *1 SOUT H L Dn Dn … Dn − 7 … Dn − 15 Dn − 15 L L Dn + 1 No Change Dn − 14 H L Dn + 2 Dn + 2 … Dn − 5 … Dn − 13 Dn − 13 −*2 L Dn + 3 Dn + 2 … Dn − 5 … Dn − 13 Dn − 13 −*2 H Dn + 3 OFF Dn − 13 Note1: When OUT0 to OUT15 output pins are set to "H" the respective output will be ON and when set to "L" the respective output will be OFF. Note2: “-“ is irrelevant to the truth table. Timing Diagram n=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 H SCK L H SIN L H SLAT L H OE L ON OUT0 OFF ON OUT1 OFF ON OUT2 OFF ON OUT15 OFF H SOUT L Note 1: Note 2: The latch circuit is a leveled-latch circuit. Please exercise precaution as it is not triggered-latch circuit. Keep the SLAT pin is set to “L” to enable the latch circuit to hold data. In addition, when the SLAT pin is set to “H” the latch circuit does not hold data. The data will instead pass onto output. When the OE pin is set to “L” the OUT0 to OUT15 output pins will go ON and OFF in response to the data. In addition, when the OE pin is set to “H” all the output pins will be forced OFF regardless of the data. 4 2009-01-21 TB62747AFG/AFNG/AFNAG/BFNAG Pin Functions Pin No AFG AFNG Pin Name I/O Function BFNAG AFNAG 1 7 GND ⎯ 2 8 SIN I The serial data input pin. 3 9 SCK I The serial data transfer clock input pin. 4 10 SLAT I The latch signal input pin. Data is saved at L level. 5 11 OUT0 O A sink type constant current output pin. 6 12 OUT1 O A sink type constant current output pin. 7 13 OUT2 O A sink type constant current output pin. 8 14 OUT3 O A sink type constant current output pin. 9 15 OUT4 O A sink type constant current output pin. 10 16 OUT5 O A sink type constant current output pin. 11 17 OUT6 O A sink type constant current output pin. 12 18 OUT7 O A sink type constant current output pin. 13 19 OUT8 O A sink type constant current output pin. 14 20 OUT9 O A sink type constant current output pin. 15 21 OUT10 O A sink type constant current output pin. 16 22 OUT11 O A sink type constant current output pin. 17 23 OUT12 O A sink type constant current output pin. 18 24 OUT13 O A sink type constant current output pin. 19 1 OUT14 O A sink type constant current output pin. 20 2 OUT15 O A sink type constant current output pin. The ground pin. 21 3 OE I The constant current output enable signal input pin. During the “H” level, the output will be forced off. 22 4 SOUT O The serial data output pin. 23 5 REXT ⎯ The constant current value setting resistor connection pin. 24 6 VDD ⎯ The power supply input pin. 5 2009-01-21 TB62747AFG/AFNG/AFNAG/BFNAG Absolute Maximum Ratings (Ta = 25°C) Characteristics Symbol Rating *1 Unit VDD −0.4 to 6.0 V Output current IO 55 mA Logic input voltage VIN −0.3 to VDD + 0.3 *2 V Output voltage VO −0.3 to 26 V Operating temperature Topr −40 to 85 °C Storage temperature Tstg −55 to 150 °C Rth(j-a) 94 (AFG) *3, 120 (AFNG) *3, 80.07(AFNAG/BFNAG) When mounted PCB °C/W PD*4 1.32 (AFG) *3, 1.04 (AFNG) *3, 1.56(AFNAG/BFNAG) When mounted PCB W Power supply voltage Thermal resistance Power dissipation Note1: Voltage is ground referenced. Note2: However, do not exceed 6V. Note3: PCB condition 76.2 x 114.3 x 1.6 mm, Cu 30% (SEMI conforming) Note4: The power dissipation decreases the reciprocal of the saturated thermal resistance (1/ Rth(j-a)) for each degree (1°C) that the ambient temperature is exceeded (Ta = 25°C). Operating Conditions DC Items (Unless otherwise specified, VDD = 3.0 to 5.5 V, Ta = −40°C to 85°C) Characteristics Power supply voltage Output voltage when OFF Symbol Test Conditions Min Typ. Max Unit VDD ⎯ 3.0 ⎯ 5.5 V VO (ON) OUTn 0.4 ⎯ 4.0 V ⎯ VDD V High level logic input voltage VIH SIN,SCK, SLAT , OE 0.7 × VDD Low level logic input voltage VIL SIN,SCK, SLAT , OE GND ⎯ 0.3 × VDD V High level SOUT output current IOH ⎯ ⎯ −1 mA Low level SOUT output current IOL mA Constant current output ⎯ ⎯ ⎯ 1 IO1 OUTn , VDD = 3.3 V, VO = 0.4 to 1.0 V ⎯ 1.5 ⎯ 35 IO2 OUTn , VDD = 5.0 V, VO = 0.4 to 1.2 V 1.5 ⎯ 45 mA AC Items (Unless otherwise specified, VDD = 3.0 to 5.5 V, Ta = −40°C to 85°C) Characteristics Serial data transfer frequency Hold time Setup time Symbol Test Circuits Test Conditions Min Typ. Max Unit fSCK 6 ⎯ ⎯ ⎯ 25 MHz tHOLD1 6 ⎯ 5 ⎯ ⎯ ns tHOLD2 6 ⎯ 5 ⎯ ⎯ ns tSETUP1 6 ⎯ 5 ⎯ ⎯ ns tSETUP2 6 5 ⎯ ⎯ ns Maximum clock rise time tr 6 *1 ⎯ ⎯ ⎯ 500 ns Maximum clock fall time tf 6 *1 ⎯ ⎯ 500 ns Note1: If the device is connected in a cascade and the tr/tf of the clock waveform increases due to deceleration of the clock waveform,it may not be possible to achieve the timing required for data transfer. Please keep these timing conditions in mind when designing your application. 6 2009-01-21 TB62747AFG/AFNG/AFNAG/BFNAG Electrical Characteristics (Unless otherwise specified, VDD = 3.3V, Ta = 25°C) Symbol Test Circuits High level logic output voltage VOH 1 Low level logic output voltage VOL High level logic input current Low level logic input current Characteristics Min Typ. Max Unit IOH = −1 mA VDD − 0.4 ⎯ ⎯ V 1 IOL = +1 mA ⎯ ⎯ 0.4 V IIH 2 VIN = VDD, OE , SIN, SCK ⎯ ⎯ 1 µA IIL 3 VIN = GND, SLAT , SIN, SCK ⎯ ⎯ −1 µA IDD1 4 VO = 25 V, REXT = OPEN, SCK = “L”, OE = “H” ⎯ ⎯ 1.0 mA IDD2 4 REXT = 1.2 kΩ, All output off ⎯ ⎯ 4.0 mA IDD3 4 REXT = 1.2 kΩ, All output on ⎯ ⎯ 8.0 mA Output current IO 5 VDD = 3.3 V, VO = 0.4 V, REXT = 1.2 kΩ, OUT0 to OUT15 ⎯ 14 ⎯ mA Constant current error(Ch to Ch) ∆IO 5 VDD = 3.3 V, VO = 0.4 V, REXT = 1.2 kΩ, OUT0 to OUT15 ⎯ ±1 ±1.5 % Constant current error(IC to IC) ∆IO(IC) 5 VDD = 3.3 V, VO = 0.4 V, REXT = 1.2 kΩ, OUT0 to OUT15 ⎯ ±1 ±1.5 % IOK 5 VDD = 3.3 V, VO = 25 V, REXT = 1.2 kΩ, OUT0 to OUT15 ⎯ ⎯ 0.5 µA %VDD 5 VDD = 3.0 to 3.6 V, VO = 0.4 V, REXT = 1.2 kΩ, OUT0 to OUT15 ⎯ ±1 ±2 % %VO 5 VDD = 3.3 V, VO = 0.4 to 3.0 V, REXT = 1.2 kΩ, OUT0 to OUT15 ⎯ ±1 ⎯ %/V RUP 3 OE 250 500 800 kΩ RDOWN 2 SLAT 250 500 800 kΩ Power supply current Output OFF leak current Constant current power supply voltage regulation Constant current regulation output voltage Pull-up resistor Pull-down resistor Test Conditions Electrical Characteristics (Unless otherwise specified, VDD = 5.0V, Ta = 25°C) Symbol Test Circuits High level logic output voltage VOH 1 Low level logic output voltage VOL 1 High level logic input current IIH Low level logic input current IIL IDD1 Characteristics Power supply current Test Conditions Min Typ. Max Unit IOH = −1 mA VDD − 0.4 ⎯ ⎯ V IOL = +1 mA ⎯ ⎯ 0.4 V 2 VIN = VDD, OE , SIN, SCK ⎯ ⎯ 1 µA 3 VIN = GND, SLAT , SIN, SCK ⎯ ⎯ −1 µA 4 VO = 25 V, REXT = OPEN, SCK = “L”, OE = “H” ⎯ ⎯ 1.0 mA IDD2 4 REXT = 1.2 kΩ, All output off ⎯ ⎯ 4.5 mA IDD3 4 REXT = 1.2 kΩ, All output on ⎯ ⎯ 8.0 mA ⎯ 14 ⎯ mA Output current IO 5 VDD = 5.0 V, VO = 0.4 V, REXT = 1.2 kΩ, OUT0 to OUT15 Constant current error(Ch to Ch) ∆IO 5 VDD = 5.0 V, VO = 0.4 V, REXT = 1.2 kΩ, OUT0 to OUT15 ⎯ ±1 ±1.5 % Constant current error(IC to IC) ∆IO(IC) 5 VDD = 5.0 V, VO = 0.4 V, REXT = 1.2 kΩ, OUT0 to OUT15 ⎯ ±1 ±1.5 % IOK 5 VDD = 5.0 V, VO = 25 V, REXT = 1.2 kΩ, OUT0 to OUT15 ⎯ ⎯ 0.5 µA %VDD 5 VDD = 4.5 to 5.5 V, VO = 0.4 V, REXT = 1.2 kΩ, OUT0 to OUT15 ⎯ ±1 ±2 % %VO 5 VDD = 5.0 V, VO = 0.4 to 3.0 V, REXT = 1.2 kΩ, OUT0 to OUT15 ⎯ ±1 ⎯ %/V Output OFF leak current Constant current power supply voltage regulation Constant current regulation Pull-up resistor Pull-down resistor output voltage RUP 3 OE 250 500 800 kΩ RDOWN 2 SLAT 250 500 800 kΩ 7 2009-01-21 TB62747AFG/AFNG/AFNAG/BFNAG Switching Characteristics (Unless otherwise specified, VDD = 3.3V, Ta = 25°C) Symbol Test Circuits SCK- OUT0 tpLH1 6 SLAT - OUT0 tpLH2 6 OE - OUT0 tpLH3 delay SCK-SOUT Characteristics Propagation time Test Conditions Min Typ. Max Unit SLAT = “H”, OE = “L” ⎯ 20 300 ns OE = “L” ⎯ 20 300 ns 6 SLAT = “H” ⎯ 20 300 ns tpLH 6 CL=10.5 pF 10 20 35 ns SCK- OUT0 tpHL1 6 SLAT = “H”, OE = “L” ⎯ 30 340 ns SLAT - OUT0 tpHL2 6 OE = “L” ⎯ 70 340 ns OE - OUT0 tpHL3 6 SLAT = “H” ⎯ 70 340 ns SCK-SOUT tpHL 6 CL=10.5 pF 10 20 35 ns Output rise time tor 6 10 to 90% of voltage waveform ⎯ 20 90 ns Output fall time tof 6 90 to 10% of voltage waveform ⎯ 25 180 ns Enable pulse width twOE(L) 6 OE = “L” *1 100 ⎯ ⎯ ns Clock pulse width twSCK 6 SCK = “H” or “L” 20 ⎯ ⎯ ns Latch pulse width twSLAT 6 SLAT = “H” 20 ⎯ ⎯ ns Note1: At the condition of twOE(H) = 250ns or more Switching Characteristics (Unless otherwise specified, VDD = 5.0V, Ta = 25°C) Symbol Test Circuits SCK- OUT0 tpLH1 6 SLAT - OUT0 tpLH2 6 Characteristics Test Conditions Min Typ. Max Unit SLAT = “H”, OE = “L” ⎯ 20 300 ns OE = “L” ⎯ 20 300 ns OE - OUT0 tpLH3 6 SLAT = “H” ⎯ 20 30 ns delay SCK-SOUT tpLH 6 CL=10.5 pF 10 20 35 ns SCK- OUT0 tpHL1 6 SLAT = “H”, OE = “L” ⎯ 30 340 ns SLAT - OUT0 tpHL2 6 OE = “L” ⎯ 70 340 ns OE - OUT0 tpHL3 6 SLAT = “H” ⎯ 70 340 ns SCK-SOUT tpHL 6 CL=10.5 pF 10 20 35 ns Output rise time tor 6 10 to 90% of voltage waveform ⎯ 20 90 ns Output fall time tof 6 90 to 10% of voltage waveform ⎯ 25 180 ns twOE(L) 6 OE = “L” *1 100 ⎯ ⎯ ns Propagation time Enable pulse width Clock pulse width twSCK 6 SCK = “H” or “L” 20 ⎯ ⎯ ns Latch pulse width twSLAT 6 SLAT = “H” 20 ⎯ ⎯ ns Note1: At the condition of twOE(H) = 250ns or more 8 2009-01-21 TB62747AFG/AFNG/AFNAG/BFNAG I/O Equivalent Circuits 1. SCK, SIN 2. OE VDD VDD (SCK) (SIN) OE GND GND 3. SLAT 4. SOUT VDD VDD SOUT SLAT GND GND 5. OUT0 to OUT15 OUT0 to OUT15 GND 9 2009-01-21 TB62747AFG/AFNG/AFNAG/BFNAG Test Circuits Test Circuit1: High level logic input voltage / Low level logic input voltage SCK SIN F.G VDD OUT0 SLAT OUT7 OE OUT15 SOUT CL = 10.5 pF V VDD = 3.3 V, 5.0 V GND REXT REXT IO = -1mA to 1mA VIH = VDD VIL = 0 V tr = tf = 10 ns (10 to 90%) Test Circuit2: High level logic input current / Pull-down resistor VIN = VDD A A SCK SIN VDD OUT0 SLAT A OUT7 OE A OUT15 VDD = 3.3 V, 5.0 V SOUT CL = 10.5 pF GND REXT REXT Test Circuit3: Low level logic input current / Pull-up resistor VDD OUT0 SLAT OUT7 OE OUT15 GND SOUT 10 VDD = 3.3 V, 5.0 V REXT CL = 10.5 pF A A SCK SIN REXT A A 2009-01-21 TB62747AFG/AFNG/AFNAG/BFNAG Test Circuit4: Power supply current F.G SCK SIN VDD OUT0 SLAT OUT7 OE OUT15 A SOUT VO = 0.4 V VDD = 3.3 V, 5.0 V GND CL = 10.5 pF REXT REXT = 1.2kΩ VIH = VDD VIL = 0 V tr = tf = 10 ns (10 to 90%) Test Circuit5: Constant current output / Output OFF leak current / Constant current error Test Circuit5: Constant current power supply voltage regulation / Constant current output voltage regulation VDD OUT0 A OUT7 A OUT15 A SLAT OE SOUT VDD = 3.3 V, 5.0 V GND CL = 10.5 pF REXT REXT = 1.2kΩ VIH = VDD VIL = 0 V tr = tf = 10 ns (10 to 90%) VO = 0.4 V, 25 V F.G SCK SIN Test Circuit6: Switching Characteristics RL = 300 Ω VDD OUT0 CL SLAT OUT7 OE CL GND SOUT CL = 10.5 pF REXT = 1.2kΩ REXT 11 RL CL = 10.5 pF VDD = 3.0 V, 5.5 V OUT15 VIH = VDD VIL = 0 V tr = tf = 10 ns (10 to 90%) RL VLED = 4.9 V F.G SCK SIN 2009-01-21 TB62747AFG/AFNG/AFNAG/BFNAG Timing Waveforms 1. SCK, SIN, SOUT twSCK 50% SCK 50% tSETUP1 SIN 90% 50% twSCK 50% 90% 10% 10% tr tf 50% tHOLD1 SOUT 50% tpLH/tpHL 2. SCK, SIN, SLAT , OE , OUT0 SCK 50% 50% SIN tHOLD2 SLAT tSETUP2 50% 50% twSLAT twOE(L) 50% OE OUT0 50% 50% tpHL1/tpLH1 tpHL2/tpLH2 3. OE , OUT0 twOE 50% 50% OE tpLH3 tpHL3 OFF 90% 50% 50% 90% OUT0 10% 10% tof ON tor 12 2009-01-21 TB62747AFG/AFNG/AFNAG/BFNAG Reference data *This data is provided for reference only. Thorough evaluation and testing should be implemented when designing your application's mass production design. Output Current – REXT Resistor IOUT - REXT 50 Theoretical value IOUT (A) = 1.13 (V) ÷ REXT (Ω) × 14.9 45 40 IOUT (mA) 35 30 25 VDD=5.0V VO=1.0V Ta=25°C 20 15 All output on Ta=25°C VOUT=0.7V 10 5 0 100 1000 REXT (Ω ) 17 10000 2009-01-21 TB62747AFG/AFNG/AFNAG/BFNAG Reference data *This data is provided for reference only. Thorough evaluation and testing should be implemented when designing your application's mass production design. Output Current – Duty (LED turn-on rate) IO - Duty 50 AFNG AFNAG/BFNAG AFG 40 40 35 35 30 30 25 20 Ta=25°C VDD=5.0V VO=1.0V ON PCB 15 10 5 AFNAG/BFNAG 45 IO (mA) IO (mA) 45 IO - Duty 50 AFNG 25 20 Ta=55°C VDD=5.0V VO=1.0V ON PCB 15 10 5 0 AFG 0 0 20 40 60 Duty - Turn on rate (%) 80 100 0 20 40 60 Duty - Turn on rate (%) 80 100 IO - Duty 50 AFNAG/BFNAG 45 40 IO (mA) 35 AFG 30 AFNG 25 20 Ta=85°C VDD=5.0V VO=1.0V ON PCB 15 10 5 0 0 20 40 60 Duty - Turn on rate (%) 80 100 Power dissipation – Ta PD - Ta 1.8 AFNAG/BFNAG 1.6 1.4 AFG PD (W) 1.2 1.0 AFNG 0.8 0.6 0.4 0.2 0.0 0 10 20 30 40 50 Ta (℃) 60 70 80 90 18 2009-01-21 TB62747AFG/AFNG/AFNAG/BFNAG Package Dimensions Weight: 0.29 g (typ.) 19 2009-01-21 TB62747AFG/AFNG/AFNAG/BFNAG Package Dimensions Weight: 0.14 g (typ.) 20 2009-01-21 TB62747AFG/AFNG/AFNAG/BFNAG Package Dimensions SSOP24-P-150-0.64 Unit : Inch 0.337 to 0.344 0.229 to 0.244 0.150 to 0.157 0.0325(REF) 0.008 to 0.012 0.054 to 0.068 0.025 0.004 to 0.098 0.010(TYP) 0.016 to 0.034 Weight: 0.14 g (typ.) 21 2009-01-21 TB62747AFG/AFNG/AFNAG/BFNAG Notes on Contents 1. Block Diagrams Some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified for explanatory purposes. 2. Equivalent Circuits The equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory purposes. 3. Timing Charts Timing charts may be simplified for explanatory purposes. 4. Application Circuits The application circuits shown in this document are provided for reference purposes only. Thorough evaluation is required, especially at the mass production design stage. Toshiba does not grant any license to any industrial property rights by providing these examples of application circuits. 5. Test Circuits Components in the test circuits are used only to obtain and confirm the device characteristics. These components and circuits are not guaranteed to prevent malfunction or failure from occurring in the application equipment. 22 2009-01-21 TB62747AFG/AFNG/AFNAG/BFNAG IC Usage Considerations Notes on handling of ICs [1] The absolute maximum ratings of a semiconductor device are a set of ratings that must not be exceeded, even for a moment. Do not exceed any of these ratings. Exceeding the rating(s) may cause the device breakdown, damage or deterioration, and may result injury by explosion or combustion. [2] Use an appropriate power supply fuse to ensure that a large current does not continuously flow in case of over current and/or IC failure. The IC will fully break down when used under conditions that exceed its absolute maximum ratings, when the wiring is routed improperly or when an abnormal pulse noise occurs from the wiring or load, causing a large current to continuously flow and the breakdown can lead smoke or ignition. To minimize the effects of the flow of a large current in case of breakdown, appropriate settings, such as fuse capacity, fusing time and insertion circuit location, are required. [3] If your design includes an inductive load such as a motor coil, incorporate a protection circuit into the design to prevent device malfunction or breakdown caused by the current resulting from the inrush current at power ON or the negative current resulting from the back electromotive force at power OFF. IC breakdown may cause injury, smoke or ignition. Use a stable power supply with ICs with built-in protection functions. If the power supply is unstable, the protection function may not operate, causing IC breakdown. IC breakdown may cause injury, smoke or ignition. [4] Do not insert devices in the wrong orientation or incorrectly. Make sure that the positive and negative terminals of power supplies are connected properly. Otherwise, the current or power consumption may exceed the absolute maximum rating, and exceeding the rating(s) may cause the device breakdown, damage or deterioration, and may result injury by explosion or combustion. In addition, do not use any device that is applied the current with inserting in the wrong orientation or incorrectly even just one time. [5] Carefully select external components (such as inputs and negative feedback capacitors) and load components (such as speakers), for example, power amp and regulator. If there is a large amount of leakage current such as input or negative feedback condenser, the IC output DC voltage will increase. If this output voltage is connected to a speaker with low input withstand voltage, overcurrent or IC failure can cause smoke or ignition. (The over current can cause smoke or ignition from the IC itself.) In particular, please pay attention when using a Bridge Tied Load (BTL) connection type IC that inputs output DC voltage to a speaker directly. Points to remember on handling of ICs (1) Heat Radiation Design In using an IC with large current flow such as power amp, regulator or driver, please design the device so that heat is appropriately radiated, not to exceed the specified junction temperature (TJ) at any time and condition. These ICs generate heat even during normal use. An inadequate IC heat radiation design can lead to decrease in IC life, deterioration of IC characteristics or IC breakdown. In addition, please design the device taking into considerate the effect of IC heat radiation with peripheral components. (2) Back-EMF When a motor rotates in the reverse direction, stops or slows down abruptly, a current flow back to the motor’s power supply due to the effect of back-EMF. If the current sink capability of the power supply is small, the device’s motor power supply and output pins might be exposed to conditions beyond maximum ratings. To avoid this problem, take the effect of back-EMF into consideration in system design. 23 2009-01-21 TB62747AFG/AFNG/AFNAG/BFNAG RESTRICTIONS ON PRODUCT USE 20070701-EN • The information contained herein is subject to change without notice. • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc. • The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.).These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in his document shall be made at the customer’s own risk. • The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. • The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties. • Please use these products in this document in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances. Toshiba assumes no liability for damage or losses occurring as a result of noncompliance with applicable laws and regulations. • The products described in this document are subject to foreign exchange and foreign trade control laws. 24 2009-01-21