10 Base-T Interface Module with all Resistors Integrated ELECTRONICS INC. EPE6121G • Optimized for AMD 79C940 (MACE) • • Robust construction allows for the toughest reflow processing • • Complies with or exceeds IEEE 802.3, 10 Base-T Requirements • Electrical Parameters @ 25° C Cut-off Frequency (MHz) Insertion Loss (dB Max.) Return Loss (dB Min.) ± 1.0 MHz 1-10 MHz 5-10 MHz Common Mode Rejection (dB Min.) Attenuation (1)(dB Min.) @ 20 MHz @ 25 MHz @ 30 MHz @ 40 MHz @30- 100 MHz Crosstalk (dB Min.) @ 200 MHz @ 1-10 MHz Xmit Rcv Xmit Rcv Xmit Rcv Xmit Rcv Xmit Rcv Xmit Rcv Xmit Rcv Xmit Rcv Xmit Rcv Xmit Rcv 17 17 -1 -1 -15 -15 -7 -5 -18 -11 -30 -18 -35 -26 -30 -30 -30 -30 -35 -35 Isolation : meets or exceeds 802.3 IEEE Requirements • Characteristic Filter Impedance : 100 Ω • • 1) Referenced to the filter output @ 5MHz, for filter only, excluding resistor network. • • Schematic 1 61.9Ω Transmit Channel 422Ω 2 LPF 1.21KΩ Receive Channel 16 3 1:1 61.9Ω 8 49.9Ω 100Ω 15 6 49.9Ω 4 9 LPF 11 1:1 14 422Ω 5 Chip Side UTP Side 12 Chip Side UTP Side Dimensions Package A Dim. J Pin 1 I.D. N PCA EPE6121G Date Code B D Pad Layout Q E P K L PCA ELECTRONICS, INC. 16799 SCHOENBORN ST. NORTH HILLS, CA 91343 A B C D E F G H I J K L M N P Q M C H 100Ω F (Inches) Min. Max. Nom. .890 .360 .360 .700 .005 .100 .490 .016 .008 .090 0° .025 .910 .380 .380 Typ. .015 Typ. .510 .020 .012 Typ. 8° .045 (Millimeters) Min. Max. Nom. 22.61 9.14 9.14 17.78 .127 2.54 12.45 .406 .203 2.29 0° .635 .040 .100 .100 .540 23.11 9.65 9.65 Typ. .381 Typ. 12.95 .508 .305 Typ. 8° 1.14 1.02 2.54 2.54 13.72 I G CSE6121Ga Rev. 1 9/5/97 Product performance is limited to specified parameters. Data is subject to change without prior notice. TEL: (818) 892-0761 FAX: (818) 894-5791 http://www.pca.com 10 Base-T Interface Module with all Resistors Integrated ELECTRONICS INC. EPE6121G The circuit below is a guideline for interconnecting PCA’s EPE6121G with AMD MACE 10 Base-T PHY chip over UTP cable. Further details of system design, such as chip pin-out, etc. can be obtained from the specific chip manufacturer. Typical insertion loss of the isolation transformer/filter is 0.7dB. This parameter covers the entire spectrum of the encoded signals in 10 Base-T protocols. However, the predistortion resistor network introduces some loss which has to be taken into account in determining how well your design meets the Standard Template requirements. Additionally, the following need to be considered while selecting resistor values : a. The filter needs 100Ω termination, thus the Thevenin’s equivalent resistance seen by the filter looking into the transmit outputs from the chip must be equal to a value close to 100Ω. The typical driver output impedance is 5Ω. Thus choose R1 and R2 values that are lowered by 5Ω on each leg. Following these guidelines will guarantee that the return loss specifications are satisfied at all extremes of cable impedance (i.e. 85Ω to 115Ω) while the module is installed in your system. b. That the template requirements are satisfied under the worst case Vcc (i.e. 4.5V), will impose a further constraint on resistor selection, in that they ought to be the minimum derived from the calculations. Add R3 for more flexibility in setting voltage levels at the outputs. Values given here provide an effective termination of 2(61.9//422)//1200Ω or approximently 100Ω. Thus, bench measurement of return loss is done by shooting all input pins of the transmit channel. This assumes, as is evident from above, that the MACE output driver impedance is less than 1Ω or 2Ω at the most. Note that some systems have auto polarity detection and some do not. If not, be certain to follow the proper polarity. It is recommended that system designers ground the chip side center taps via a low voltage capacitor. Taking the cable side center taps to chassis via capacitors, is not recommended, as this will add cost without containing EMI. This may worsen EMI, specifically if the primary “common mode termination” is pulled to ground as shown. The pulldown resistors used around the RJ45 connector have been known to suppress unwanted radiation that unused wires pick up from the immediate environment. Their placement and use are to be considered carefully before a design is finalized. It is recommended that there be a neat separation of ground planes in the layout. It is generally accepted practice to limit the plane off at least 0.08 inches away from the chip side pins of EPE6121G. There need not be any ground plane beyond this point. For best results, PCB designer should design the outgoing traces preferably to be 50Ω, balanced and well coupled to achieve minimum radiation from these traces. Typical Application Circuit for UTP with Integrated Resistor Network TX+ TXd+ AMD 79C940 TXTXdRX+ 1 8 1 2 6 2 5 9 3 3 11 6 4 EPE6121G 16 12 TX+ TX- RJ45* RX+ RX4 5 7 8 14 RXChassis Ground Notes: PCA ELECTRONICS, INC. 16799 SCHOENBORN ST. NORTH HILLS, CA 91343 *Pin-outs shown are for NIC only CSE6121Gb Rev. 1 9/5/97 TEL: (818) 892-0761 FAX: (818) 894-5791 http://www.pca.com