PSEMI PE43704DS

Product Specification
PE43704
UltraCMOS® RF Digital Step
Attenuator, 7-bit, 31.75 dB
with Optional VssEXT Bypass Mode
9 kHz - 8 GHz
Product Description
The PE43704 is a HaRP™ technology-enhanced, high
linearity, 7-bit 50Ω RF Digital Step Attenuator (DSA). It
offers maximum power handling of 28 dBm up to 8 GHz
and covers a 31.75 dB attenuation range in 0.25 dB,
0.5 dB, or 1.0 dB steps. The PE43704 is a pin-compatible
version of PE43703. It provides multiple CMOS control
interfaces and an optional VssEXT bypass mode to
improve spurious performance. It maintains high
attenuation accuracy over frequency and temperature and
exhibits very low insertion loss and low power
consumption. No blocking capacitors are required if DC
voltage is not present on the RF ports.
The PE43704 is manufactured on Peregrine’s
UltraCMOS® process, a patented variation of silicon-oninsulator (SOI) technology on a sapphire substrate,
offering the performance of GaAs with the economy and
integration of conventional CMOS.
Features
 HaRP™ technology enhanced
 Safe attenuation state transitions
 Attenuation options: covers a 31.75 dB




Figure 1. Package Type
32-lead 5x5 QFN


range in 0.25 dB, 0.5 dB, or 1.0 dB steps
 0.25 dB monotonicity for ≤ 6 GHz
 0.50 dB monotonicity for ≤ 7 GHz
 1.00 dB monotonicity for ≤ 8 GHz
High power handling @ 8 GHz in 50Ω
 28 dBm CW
 31 dBm instantaneous power
High linearity
 IIP3 of 61 dBm
1.8V/3.3V control logic
Programming modes
 Direct parallel
 Latched parallel
 Serial
 Serial Addressable
High-attenuation state @ power-up (PUP)
ESD performance
 1.5kV HBM on all pins
Figure 2. Functional Diagram
DOC-02161
Document No. DOC-16514-6 |
www.psemi.com
©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 20
PE43704
Product Specification
Table 1. Electrical Specifications: 0.25 dB steps @ +25°C, VDD = 2.3V to 5.5V, VssEXT = 0V or
VDD = 3.4V to 5.5V, VssEXT = -3.4V (ZS = ZL = 50Ω) unless otherwise noted
Parameter
Condition
Frequency
Operating frequency
Min
Typ
9 kHz
Attenuation range
0.25 dB Step
Unit
6000 MHz
As shown
0 – 31.75
9 kHz – 2 GHz
2 GHz – 4 GHz
4 GHz – 6 GHz
Insertion loss
Max
dB
1.3
1.7
2.4
1.4
1.9
2.7
+ (0.15 + 3% of
Attenuation Setting)
- (0.1 + 1% of
Attenuation Setting)
9 KHz ≤ 4 GHz
0 dB – 15.75 dB Attenuation settings
+ (0.15 + 5% of
Attenuation Setting)
- 0.15
4 GHz – 6 GHz
Attenuation error
+ (0.15 + 3%
Attenuation Setting)
- (0.1 + 1% of
Attenuation Setting)
9 KHz ≤ 4 GHz
16 dB – 31.75 dB Attenuation settings
+ (0.25 + 5% of
Attenuation Setting)
0.0
4 GHz – 6 GHz
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Return loss
Input port
9 kHz – 4 GHz
4 GHz – 6 GHz
20
15
dB
dB
Return loss
Output port
9 kHz – 4 GHz
4 GHz – 6 GHz
17
13
dB
dB
0 dB – 31.75 dB Attenuation settings
9 kHz – 6 GHz
58
deg
34
dBm
61
dBm
dBm
Relative phase
Input 1dB compression point
IIP3
1
50 MHz – 6 GHz
Two tones at +18 dBm, 20 MHz spacing
2
32
50 MHz – 6 GHz
Typical spurious value
VssEXT = 0V
–140
RF Trise/Tfall
10% / 90% RF
600
ns
Settling time
RF settled to within 0.05 dB of final value
2
µs
Switching time
50% CTRL to 90% or 10% RF
1.1
µs
Notes: 1. The input 1dB compression point is a linearity figure of merit. Refer to Table 5 for the RF input power PIN (50Ω)
2. To prevent negative voltage generator spurs, supply –3.4 volts to VssEXT
©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 20
Document No. DOC-16514-6 |
UltraCMOS® RFIC Solutions
PE43704
Product Specification
Table 2. Electrical Specifications: 0.5 dB steps @ +25°C, VDD = 2.3V to 5.5V, VssEXT = 0V or
VDD = 3.4V to 5.5V, VssEXT = -3.4V (ZS = ZL = 50Ω) unless otherwise noted
Parameter
Condition
Frequency
Operating frequency
Min
Typ
9 kHz
Attenuation range
0.5 dB Step
Unit
7000 MHz
As shown
0 – 31.5
9 kHz – 2 GHz
2 GHz – 4 GHz
4 GHz – 6 GHz
6 GHz – 7 GHz
Insertion loss
Max
1.3
1.7
2.4
2.5
dB
1.4
1.9
2.7
2.9
(0.15 + 3% of
Attenuation Setting)
- (0.1 + 2% of
Attenuation Setting)
9 KHz ≤ 4 GHz
0 dB – 15.5 dB Attenuation settings
4 GHz – 7 GHz
+ (0.25 + 5% of
Attenuation Setting)
- 0.25
9 KHz ≤ 4 GHz
+ (0.15 + 3% of
Attenuation Setting)
- (0.1 + 2% of
Attenuation Setting)
Attenuation error
16 dB – 31.5 dB Attenuation settings
+ (0.25 + 6% of
Attenuation Setting)
- (0.25 + 2.5% of
Attenuation Setting)
4 GHz – 7 GHz
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Return loss
Input port
9 kHz – 4 GHz
4 GHz – 7 GHz
20
16
dB
dB
Return loss
Output port
9 kHz – 4 GHz
4 GHz – 7 GHz
17
14
dB
dB
0 dB – 31.5 dB Attenuation settings
9 kHz – 7 GHz
65
deg
34
dBm
61
dBm
Relative phase
Input 1dB compression point
1
IIP3
50 MHz – 7 GHz
Two tones at +18 dBm, 20 MHz spacing
2
32
50 MHz – 7 GHz
Typical spurious value
VssEXT = 0V
–140
dBm
RF Trise/Tfall
10% / 90% RF
600
ns
Settling time
RF settled to within 0.05 dB of final value
2
µs
Switching time
50% CTRL to 90% or 10% RF
1.1
µs
Notes: 1. The input 1dB compression point is a linearity figure of merit. Refer to Table 5 for the RF input power PIN (50Ω)
2. To prevent negative voltage generator spurs, supply –3.4 volts to VssEXT
Document No. DOC-16514-6 |
www.psemi.com
©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 3 of 20
PE43704
Product Specification
Table 3. Electrical Specifications: 1 dB steps @ +25°C, VDD = 2.3V to 5.5V, VssEXT = 0V or
VDD = 3.4V to 5.5V, VssEXT = -3.4V (ZS = ZL = 50Ω) unless otherwise noted
Parameter
Condition
Frequency
Operating frequency
Min
Typ
9 kHz
Attenuation range
1 dB Step
1.3
1.7
2.4
2.9
As shown
dB
1.4
1.9
2.7
3.2
+ (0.25 + 6% of
Attenuation Setting)
- (0.25 + 2% of
Attenuation Setting)
4 GHz ≤ 7 GHz
+ (0.25 + 7% of
Attenuation Setting)
- (0.25 + 2% of
Attenuation Setting)
7 GHz – 8 GHz
Attenuation error
+ (0.15 + 3% of
Attenuation Setting)
- (0.1 + 1% of
Attenuation Setting)
9 kHz ≤ 4 GHz
16dB – 31 dB Attenuation settings
8000 MHz
+ (0.15 + 3% of
Attenuation Setting)
- (0.1 + 1% of
Attenuation Setting)
9 kHz ≤ 4 GHz
0 dB – 15 dB Attenuation settings
Unit
0 - 31
9 kHz – 2 GHz
2 GHz – 4 GHz
4 GHz – 6 GHz
6 GHz – 8 GHz
Insertion loss
Max
+ (0.25 + 6% of
Attenuation Setting)
- (0.25 + 3% of
Attenuation Setting)
4 GHz ≤ 7 GHz
+ (0.25 + 7% of
Attenuation Setting)
- (0.25 + 4% of
Attenuation Setting)
7 GHz – 8 GHz
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Return loss
Input port
9 kHz – 4 GHz
4 GHz – 8 GHz
20
14.5
dB
dB
Return loss
Output port
9 kHz – 4 GHz
4 GHz – 8 GHz
17
12.5
dB
dB
0 dB – 31 dB Attenuation settings
9 kHz – 8 GHz
80
deg
34
dBm
61
dBm
Relative phase
Input 1dB compression point
IIP3
1
50 MHz – 8 GHz
Two tones at +18 dBm, 20 MHz spacing
2
32
50 MHz – 8 GHz
Typical spurious value
VssEXT = 0V
–140
dBm
RF Trise/Tfall
10% / 90% RF
600
ns
Settling time
RF settled to within 0.05 dB of final value
2
µs
Switching time
50% CTRL to 90% or 10% RF
1.1
µs
Notes: 1. The input 1dB compression point is a linearity figure of merit. Refer to Table 5 for the RF input power PIN (50Ω)
2. To prevent negative voltage generator spurs, supply –3.4 volts to VssEXT
©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 4 of 20
Document No. DOC-16514-6 |
UltraCMOS® RFIC Solutions
PE43704
Product Specification
Figure 3. Pin Configuration (Top View)
Table 5. Operating Ranges
Symbol
Min
Supply voltage (normal
mode, VssEXT = 0V)1
VDD
2.3
Supply voltage (bypass
mode, VssEXT = -3.4V,
VDD≥ 3.4V for full spec.
compliance)2
VDD
2.7
Negative supply voltage
(bypass mode)2
VssEXT
-3.6
Supply current (normal
mode, VssEXT = 0V)1
IDD
Supply current (bypass
mode, VssEXT = -3.4V)2
IDD
Negative supply current
(bypass mode, VssEXT =
-3.4V)2
ISS
-40
Digital input high
VIH
1.17
3.6
V
Digital input low
VIL
-0.3
0.6
V
ICTRL
15
μA
PMAX,CW
see
Fig. 4
+28
dBm
dBm
see
Fig. 4
+31
dBm
dBm
+85
°C
Parameter
Table 4. Pin Descriptions
Pin #
Pin Name
Description
1
N/C
No connect
2
VDD
Supply voltage
3
P/S
Serial/parallel mode select
4
A0
Address bit A0 connection
5, 6,
8-17, 19
GND
Ground
7
RF11
RF1 port (RF input)
Operating temperature
range
18
RF21
RF2 port (RF output)
Notes:
20
VssEXT2
21
A2
Address bit A2 connection
22
A1
Address bit A1 connection
23
LE
Serial interface latch enable input
24
CLK
25
SI
External Vss negative voltage control
Unit
5.5
V
5.5
V
-2.4
V
130
200
μA
50
80
μA
3.4
-16
RF input power, pulsed4
9 kHz < 50 MHz PMAX,PULSED
50 MHz ≤ 8 GHz
TOP
-40
25
μA
1. Normal mode: connect VssEXT (pin 20) to GND (VssEXT = 0V) to
enable internal negative voltage generator
2. Bypass mode: use VssEXT (pin 20) to bypass and disable internal
negative voltage generator
3. 100% duty cycle, all bands, 50Ω
4. Pulsed, 5% duty cycle of 4620 µs period, 50Ω
Serial interface data input
3
C16 (D6)
27
3
Parallel control bit, 8 dB
3
Parallel control bit, 4 dB
3
Parallel control bit, 2 dB
Parallel control bit, 16 dB
C8 (D5)
C4 (D4)
29
C2 (D3)
30
C1 (D2)3
31
Max
Serial interface clock input
26
28
Digital input current
RF input power, CW3
9 kHz < 50 MHz
50 MHz ≤ 8 GHz
Typ
Parallel control bit, 1 dB
3
C0.5 (D1)
3
32
C0.25 (D0)
Pad
GND
Parallel control bit, 0.5 dB
Parallel control bit, 0.25 dB
Exposed pad: ground for proper operation
Notes: 1. RF pins 7 and 18 must be at 0V DC. The RF pins do not require DC
blocking capacitors for proper operation if the 0V DC
requirement is met
2. Use VssEXT (pin 20) to bypass and disable internal
negative voltage generator. Connect VssEXT (pin 20) to GND (VssEXT = 0V)
to enable internal negative voltage generator
3. Ground C0.25, C0.5, C1 C2, C4, C8, C16 if not in use
Document No. DOC-16514-6 |
www.psemi.com
©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 5 of 20
PE43704
Product Specification
Table 6. Absolute Maximum Ratings
Parameter/Condition
Switching Frequency
Symbol
Min
Max
Unit
VDD
-0.3
5.5
V
Digital input voltage
VCTRL
-0.3
3.6
V
RF input power, max
PMAX,ABS
+34
dBm
+150
°C
VESD,HBM
1500
V
ESD voltage MM , all pins
VESD,MM
200
V
ESD voltage CDM3, all pins
VESD,CDM
250
V
Supply voltage
Storage temperature range
1
ESD voltage HBM , all pins
2
Notes:
TST
-65
1. Human Body Model (MIL-STD 883 Method 3015)
2. Machine Model (JEDEC JESD22-A115)
3. Charged Device Model (JEDEC JESD22-C101)
Exceeding absolute maximum ratings may cause
permanent damage. Operation should be
restricted to the limits in the Operating Ranges
table. Operation between operating range
maximum and absolute maximum for extended
periods may reduce reliability.
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS® device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the specified rating.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS®
devices are immune to latch-up.
Moisture Sensitivity Level
The Moisture Sensitivity Level rating for the
PE43704 in the 5x5 QFN package is MSL1.
©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 6 of 20
The PE43704 has a maximum 25 kHz switching
rate when the internal negative voltage generator
is used (pin 20 = GND). The rate at which the
PE43704 can be switched is only limited to the
switching time (Tables 1-3) if an external negative
supply is provided (pin 20 = VssEXT).
Switching frequency is defined to be the speed at
which the DSA can be toggled across attenuation
states. Switching time is the time duration
between the point the control signal reaches 50%
of the final value and the point the output signal
reaches within 10% or 90% of its target value.
Optional External Vss Control (VssEXT)
For proper operation, the VssEXT control pin must
be grounded or tied to the Vss voltage specified in
Table 5. When the VssEXT control pin is grounded,
FETs in the switch are biased with an internal
voltage generator. For applications that require
the lowest possible spur performance, VssEXT can
be applied externally to bypass the internal
negative voltage generator.
Table 7. Latch and Clock Specifications
Latch Enable
Shift Clock
Function
0
↑
Shift register clocked
↑
X
Contents of shift register
transferred to attenuator core
Safe Attenuation State Transitions
The PE43704 features a novel architecture to
provide safe transition behavior when changing
attenuation states. When RF input power is
applied, positive output power spikes are
prevented during attenuation state changes by
optimized internal timing control.
Document No. DOC-16514-6 |
UltraCMOS® RFIC Solutions
PE43704
Product Specification
Figure 4. Power De-rating Curve (50Ω, -40°C to 85°C Ambient)
35
Input Power (dBm)
30
25
20
Max. RF Input Power, CW & Pulsed (9k ‐ < 50MHz)
15
Max. RF Input Power, CW (50M ‐ 8GHz)
Max. RF Input Power, Pulsed (50M ‐ 8GHz)
10
5
0
1
10
100
1,000
10,000
100,000
1,000,000
10,000,000
Frequency (kHz)
Document No. DOC-16514-6 |
www.psemi.com
©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 7 of 20
PE43704
Product Specification
Table 8. Parallel Truth Table
Table 9. Serial Attenuation Word Truth Table
Parallel Control Setting
Attenuation Word
D7
D6
D5
D4
D3
D2
D1
D0
(LSB)
Attenuation
Setting
RF1-RF2
D6
D5
D4
D3
D2
D1
D0
Attenuation
Setting
RF1-RF2
L
L
L
L
L
L
L
Reference I.L.
L
L
L
L
L
L
L
L
Reference I.L.
L
L
L
L
L
L
H
0.25 dB
L
L
L
L
L
L
L
H
0.25 dB
L
L
L
L
L
H
L
0.5 dB
L
L
L
L
L
L
H
L
0.5 dB
L
L
L
L
H
L
L
1 dB
L
L
L
L
L
H
L
L
1 dB
L
L
L
H
L
L
L
2 dB
L
L
L
L
H
L
L
L
2 dB
L
L
H
L
L
L
L
4 dB
L
L
L
H
L
L
L
L
4 dB
L
H
L
L
L
L
L
8 dB
L
L
H
L
L
L
L
L
8 dB
H
L
L
L
L
L
L
16 dB
L
H
L
L
L
L
L
L
16 dB
31.75 dB
L
H
H
H
H
H
H
H
31.75 dB
H
H
H
H
H
H
H
Table 10. Serial Address Word Truth Table
Address Word
A0
Address
Setting
L
L
000
L
H
001
A7
(MSB)
A6
A5
A4
A3
A2
A1
X
X
X
X
X
L
X
X
X
X
X
L
X
X
X
X
X
L
H
L
010
X
X
X
X
X
L
H
H
011
X
X
X
X
X
H
L
L
100
X
X
X
X
X
H
L
H
101
X
X
X
X
X
H
H
L
110
X
X
X
X
X
H
H
H
111
Table 11. Serial-Addressable Register Map
Bits can either be set to logic high or logic low
MSB (last in)
LSB (first in)
D7 must be set to logic low
Q15
Q14
Q13
Q12
Q11
Q10
Q9
Q8
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Address Word
Attenuation Word
Attenuation Word is derived directly from the attenuation value. For example, to program the 18.25 dB state
at address 3:
Address word: XXXXX011
Attenuation Word: Multiply by 4 and convert to binary → 4 * 18.25 dB → 73 → 01001001
Serial Input: XXXXX01101001001
©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 8 of 20
Document No. DOC-16514-6 |
UltraCMOS® RFIC Solutions
PE43704
Product Specification
Programming Options
Parallel/Serial Selection
Either a parallel or serial-addressable interface can be
used to control the PE43704. The P/S bit provides this
selection, with P/S = LOW selecting the parallel
interface and P/S = HIGH selecting the serialaddressable interface.
Parallel Mode Interface
The parallel interface consists of seven CMOScompatible control lines that select the desired
attenuation state, as shown in Table 8.
The parallel interface timing requirements are defined
by Figure 6 (Parallel Interface Timing Diagram),
Table 13 (Parallel and Direct Interface AC
Characteristics) and switching time (Tables 1-3).
For latched-parallel programming the Latch Enable (LE)
should be held LOW while changing attenuation state
control values, then pulse LE HIGH to LOW (per
Figure 6) to latch new attenuation state into device.
For direct parallel programming, the Latch Enable (LE)
line should be pulled HIGH. Changing attenuation state
control values will change device state to new
attenuation. Direct mode is ideal for manual control of
the device (using hardwire, switches, or jumpers).
Serial Interface
The serial-addressable interface is a 16-bit serial-in,
parallel-out shift register buffered by a transparent
latch. The 16-bits make up two words comprised of 8bits each. The first word is the Attenuation Word, which
controls the state of the DSA. The second word is the
Address Word, which is compared to the static (or
programmed) logical states of the A0, A1 and A2 digital
inputs. If there is an address match, the DSA changes
state; otherwise its current state will remain unchanged.
Figure 5 illustrates an example timing diagram for
programming a state. It is required that all parallel
control inputs be grounded when the DSA is used in
serial-addressable mode.
The serial-interface is controlled using three CMOScompatible signals: Serial-In (SI), Clock (CLK), and
Latch Enable (LE). The SI and CLK inputs allow data to
be serially entered into the shift register. Serial data is
clocked in LSB first, beginning with the Attenuation
Word.
Document No. DOC-16514-6 |
www.psemi.com
The shift register must be loaded while LE is held
LOW to prevent the attenuator value from changing
as data is entered. The LE input should then be
toggled HIGH and brought LOW again, latching the
new data into the DSA. Attenuation Word and
Address Word truth tables are listed in Table 9 and
Table 10. A programming example of the serial
register is illustrated in Table 11. The serial timing
diagram is illustrated in Figure 5.
Power-up Control Settings
The PE43704 will always initialize to the maximum
attenuation setting (31.75 dB) on power-up for both
the serial-addressable and latched-parallel modes
of operation and will remain in this setting until the
user latches in the next programming word. In direct
-parallel mode, the DSA can be preset to any state
within the 31.75 dB range by pre-setting the parallel
control pins prior to power-up. In this mode, there is
a 400-µs delay between the time the DSA is
powered-up to the time the desired state is set.
During this power-up delay, the device attenuates
to the maximum attenuation setting (31.75 dB)
before defaulting to the user defined state. If the
control pins are left floating in this mode during
power-up, the device will default to the minimum
attenuation setting (insertion loss state).
Dynamic operation between serial and parallel
programming modes is possible.
If the DSA powers up in serial mode (P/S = HIGH),
all the parallel control inputs DI[6:0] must be set to
logic low. Prior to toggling to parallel mode, the
DSA must be programmed serially to ensure D[7] is
set to logic low.
If the DSA powers up in either latched or directparallel mode, all parallel pins DI[6:0] must be set to
logic low prior to toggling to serial-addressable
mode (P/S = HIGH), and held low until the DSA has
been programmed serially to ensure bit D[7] is set
to logic low.
The sequencing is only required once on power-up.
Once completed, the DSA may be toggled between
serial and parallel programming modes at will.
©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 9 of 20
PE43704
Product Specification
Figure 5. Serial Timing Diagram
Bits can either be set to logic high or logic low
D[7] must be set to logic low
DI[6:0]
T
T
DISU
DIH
P/S
T
T
PSSU
D[0]
SI
T
D[1]
D[2]
D[3]
D[4]
D[5]
PSIH
D[7]
D[6]
SISU
T
SIH
CLK
T
T
CLKL
T
CLKH
LESU
LE
T
LEPW
T
DO[6:0]
PD
VALID
Figure 6. Latched-Parallel/Direct-Parallel Timing Diagram
P/S
TPSSU
DI[6:0]
TPSH
VALID
TDISU
TDIH
LE
TLEPW
DO[6:0]
VALID
TPD
TDIPD
Table 12. Serial Interface AC Characteristics
VDD = 3.4V or 5.0V, -40°C < TA < 85°C, unless otherwise specified
Parameter
Symbol
Min
Max
Unit
Table 13. Parallel and Direct Interface
AC Characteristics
VDD = 3.4V or 5.0V, -40°C < TA < 85°C, unless otherwise
specified
Serial clock frequency
FCLK
-
10
MHz
Serial clock HIGH time
TCLKH
30
-
ns
Serial clock LOW time
TCLKL
30
-
ns
TLEPW
Last serial clock rising edge setup
time to Latch Enable rising edge
TLESU
10
-
ns
Latch enable min. pulse width
TLEPW
30
-
ns
Serial data setup time
TSISU
10
-
ns
Serial data hold time
TSIH
10
-
ns
Parallel data setup time
TDISU
100
-
ns
Parallel data hold time
TDIH
100
-
ns
Address setup time
TASU
100
-
ns
Address hold time
TAH
100
-
ns
Parallel/serial setup time
TPSSU
100
-
ns
Parallel/serial hold time
TPSH
100
-
ns
Digital register delay (internal)
TPD
-
10
ns
©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 10 of 20
Symbol
Parameter
Min
Max
Unit
Latch enable minimum pulse
width
30
-
ns
TDISU
Parallel data setup time
100
-
ns
TDIH
Parallel data hold time
100
-
ns
TPSSU
Parallel/serial setup time
100
-
ns
TPSIH
Parallel/serial hold time
100
-
ns
TPD
Digital register delay (internal)
-
10
ns
TDIPD
Digital register delay (internal,
direct mode only)
-
5
ns
Document No. DOC-16514-6 |
UltraCMOS® RFIC Solutions
PE43704
Product Specification
Typical Performance Data, 0.25 dB Step @ 25°C and VDD = 3.4V unless otherwise specified
Figure 7. 0.25 dB Step Attenuation vs. Frequency*
Step Attenuation (dB)
0.25
0.2GHz
0.125
0.9GHz
1.8GHz
0
2.2GHz
3GHz
4GHz
‐0.125
5GHz
6GHz
‐0.25
0
4
8
12
16
20
Attenuation Setting (dB)
24
28
32
* Monotonicity is held so long as step-attenuation does not cross below –0.25 dB
Figure 8. 0.25 dB Step, Actual vs. Frequency
35
Actual Attenuation (dB)
30
25
0.9GHz
20
1.8GHz
2.2GHz
15
3GHz
10
4GHz
5GHz
5
6GHz
0
0
4
8
12
16
20
Ideal Attenuation (dB)
24
28
32
Figure 10. 0.25 dB Attenuation Error vs.
Frequency
Figure 9. 0.25 dB Major State Bit Error vs.
Attenuation Setting
1.5
0.25dB
1
Attenuation Error (dB)
0.5dB
1dB
0.5
2dB
4dB
0
8dB
Attenuation Error (dB)
1.5
0.2GHz
1
0.9GHz
1.8GHz
0.5
2.2GHz
3GHz
4GHz
0
5GHz
16dB
‐0.5
31.75dB
0
1
2
3
4
Frequency (GHz)
Document No. DOC-16514-6 |
www.psemi.com
5
6
6GHz
‐0.5
0
4
8
12
16
20
Attenuation Setting (dB)
24
28
32
©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 11 of 20
PE43704
Product Specification
Typical Performance Data, 0.5 dB Step @ 25°C and VDD = 3.4V unless otherwise specified
Figure 11. 0.5 dB Step Attenuation vs. Frequency*
Step Attenuation (dB)
0.5
0.2GHz
0.25
0.9GHz
1.8GHz
2.2GHz
0
3GHz
4GHz
‐0.25
5GHz
6GHz
7GHz
‐0.5
0
4
8
12
16
20
Attenuation Setting (dB)
24
28
32
* Monotonicity is held so long as step-attenuation does not cross below –0.5 dB
Figure 12. 0.5 dB Step, Actual vs. Frequency
35
Actual Attenuation (dB)
30
0.9GHz
25
1.8GHz
20
2.2GHz
15
3GHz
4GHz
10
5GHz
5
6GHz
7GHz
0
0
4
8
12
16
20
Ideal Attenuation (dB)
24
28
32
Figure 14. 0.5 dB Attenuation Error vs.
Frequency
Figure 13. 0.5 dB Major State Bit Error vs.
Attenuation Setting
1.5
1.5
Attenuation Error (dB)
1dB
2dB
0.5
4dB
8dB
0
16dB
Attenuation Error (dB)
0.2GHz
0.5dB
1
1
0.9GHz
1.8GHz
2.2GHz
0.5
3GHz
4GHz
5GHz
0
6GHz
31.5dB
‐0.5
7GHz
‐0.5
0
1
2
3
4
Frequency (GHz)
5
6
7
©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 12 of 20
0
4
8
12
16
20
Attenuation Setting (dB)
Document No. DOC-16514-6 |
24
28
32
UltraCMOS® RFIC Solutions
PE43704
Product Specification
Typical Performance Data, 1 dB Step @ 25°C and VDD = 3.4V unless otherwise specified
Figure 15. 1 dB Step Attenuation vs. Frequency*
1
Step Attenuation (dB)
0.2GHz
0.9GHz
0.5
1.8GHz
2.2GHz
0
3GHz
4GHz
5GHz
‐0.5
6GHz
7GHz
‐1
8GHz
0
4
8
12
16
20
Attenuation Setting (dB)
24
28
32
* Monotonicity is held so long as step-attenuation does not cross below –1.0 dB
Figure 16. 1 dB Step, Actual vs. Frequency
35
Actual Attenuation (dB)
30
25
0.9GHz
2.2GHz
20
3GHz
15
4GHz
5GHz
10
6GHz
5
7GHz
8GHz
0
0
4
8
12
16
20
Ideal Attenuation (dB)
24
28
32
Figure 17. 1 dB Major State Bit Error vs.
Attenuation Setting
1.5
Attenuation Error (dB)
1
1dB
2dB
0.5
4dB
0
8dB
16dB
‐0.5
31dB
‐1
0
1
2
3
4
5
Frequency (GHz)
Document No. DOC-16514-6 |
6
www.psemi.com
7
8
©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 13 of 20
PE43704
Product Specification
Typical Performance Data, 1 dB Step @ 25°C and VDD = 3.4V unless otherwise specified
Figure 18. 1 dB Attenuation Error vs. Frequency
1.5
Attenuation Error (dB)
0.2GHz
0.9GHz
1
1.8GHz
2.2GHz
0.5
3GHz
4GHz
0
5GHz
6GHz
‐0.5
7GHz
8GHz
‐1
0
4
8
12
16
20
Attenuation Setting (dB)
24
28
32
Figure 19. Insertion Loss vs. Temperature
Figure 20. Input Return Loss vs.
Attenuation Setting
0
0
‐0.5
‐5
0dB
‐10
‐2
‐2.5
‐40C
‐3
25C
‐3.5
85C
‐4
‐4.5
‐5
Return Loss (dB)
Insertion Loss (dB)
‐1
‐1.5
0.25dB
‐15
0.5dB
‐20
1dB
‐25
2dB
4dB
‐30
8dB
‐35
16dB
31.75dB
‐40
0
1
2
3
4
5
Frequency (GHz)
6
7
8
9
0
1
2
3
4
5
Frequency (GHz)
6
7
8
9
Figure 21. Output Return Loss vs.
Attenuation Setting
0
‐5
0dB
Return Loss (dB)
‐10
0.25dB
‐15
0.5dB
‐20
1dB
‐25
2dB
4dB
‐30
8dB
‐35
16dB
31.75dB
‐40
0
1
2
3
4
5
Frequency (GHz)
6
7
8
9
©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 14 of 20
Document No. DOC-16514-6 |
UltraCMOS® RFIC Solutions
PE43704
Product Specification
Typical Performance Data, 1 dB Step @ 25°C and VDD = 3.4V unless otherwise specified
Figure 22. Input Return Loss vs. Temperature
for 16 dB Attenuation Setting
Figure 23. Output Return Loss vs. Temperature
for 16 dB Attenuation Setting
0
‐5
‐5
‐10
‐10
‐15
‐20
‐40C
25C
‐25
85C
Return Loss (dB)
Return Loss (dB)
0
‐15
‐20
‐40C
‐25
25C
85C
‐30
‐30
‐35
‐35
‐40
‐40
0
1
2
3
4
5
Frequency (GHz)
Document No. DOC-16514-6 |
6
7
www.psemi.com
8
9
0
1
2
3
4
5
Frequency (GHz)
6
7
8
9
©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 15 of 20
PE43704
Product Specification
Typical Performance Data @ 25°C and VDD = 3.4V unless otherwise specified
Figure 24. Relative Phase Error vs.
Attenuation Setting
Figure 25. Relative Phase Error for 31.75 dB
Attenuation Setting vs. Frequency
70
100
0dB
0.25dB
60
0.5dB
1dB
40
2dB
4dB
8dB
20
Relative Phase Error (deg)
Relative Phase Error (deg)
60
80
31.75dB
0
1
2
3
4
5
Frequency (GHz)
6
7
2GHz
3GHz
30
4GHz
5GHz
20
6GHz
0
‐40
8
Figure 26. Attenuation Error @ 900 MHz vs.
Temperature
25
Temperature (deg C)
85
Figure 27. Attenuation Error @ 1800 MHz vs.
Temperature
0.75
0.25
‐40C
0
25C
‐0.25
Attenuation Error (dB)
0.5
Attenuation Error (dB)
1.8GHz
40
10
16dB
0
0.9GHz
50
0.5
‐40C
0.25
25C
0
‐0.25
85C
85C
‐0.5
‐0.5
0
4
8
12
16
20
Attenuation Setting (dB)
24
28
0
32
Figure 28. Attenuation Error @ 3000 MHz vs.
Temperature
4
8
12
16
20
Attenuation Setting (dB)
24
28
32
Figure 29. IIP3 vs. Attenuation Setting
0.75
74
72
‐40C
0.25
25C
0
Input IP3 (dBm) Attenuation Error (dB)
0.5
70
68
0dB
8dB
66
16dB
64
‐0.25
85C
62
‐0.5
0
4
8
12
16
20
Attenuation Setting (dB)
24
28
32
©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 16 of 20
60
2
3
4
5
6
7
8
Frequency (GHz)
Document No. DOC-16514-6 |
UltraCMOS® RFIC Solutions
PE43704
Product Specification
Figure 31. Evaluation Board Layout
Evaluation Kit
The Digital Attenuator Evaluation Board (EVB) was
designed to ease customer evaluation of the
PE43704 Digital Step Attenuator. PE43704 EVB
supports direct-parallel, latched-parallel, and serial
modes.
A0
Evaluation Kit Setup
Connect the EVB with the USB dongle board and
USB cable as shown in Figure 30.
Figure 30. Evaluation Kit
PRT-13505
Direct-Parallel Programming Procedure
Direct-parallel programming is suitable for manual
operation without software programming. For
manual direct-parallel programming, position the
Parallel/Serial (P/S) select switch to the Parallel (or
left) position. The LE pin of J1 (pin 15) must be tied
to HIGH voltage. Switches D0–D6 are SP3T
switches that enable the user to manually program
the parallel bits. When D0–D6 are toggled to the
‘HIGH’ position, logic high is presented to the
parallel input. When toggled to the ‘LOW’ position,
logic low is presented to the parallel input. Setting
D0–D6 to the ‘AUTO’ position presents as OPEN,
which is set for software programming of LatchedParallel and Serial mode. Table 8 depicts the
parallel programming truth table.
Latched-Parallel Programming Procedure
For automated latched-parallel programming,
connect the USB dongle board and cable that is
provided with the Evaluation Kit (EVK) from the
USB port of the PC to the J1 header of the
PE43704 EVB, and set the D0–D6 SP3T switches
to the ‘AUTO’ position. Position the Parallel/Serial
(P/S) select switch to the Parallel (or left) position.
The evaluation software is written to operate the
Document No. DOC-16514-6 |
www.psemi.com
DSA in Parallel Mode. Ensure that the software
GUI is set to Latched-Parallel mode. Use the
software GUI to enable the desired attenuation
state. The software GUI automatically programs
the DSA each time an attenuation state is
enabled.
Serial-Addressable Programming Procedure
For automated serial programming, connect the
USB dongle board and cable that is provided with
the Evaluation Kit (EVK) from the USB port of the
PC to the J1 header of the PE43704 EVB, and set
the D0–D6 SP3T switches to the ‘AUTO’ toggle
position. Position the Parallel/Serial (P/S) select
switch to the Serial (or right) position. Prior to
programming, the user must define an address
setting using the HDR4 header pin. Jump the
middle row of pins on the HDR4 header (A0–A2)
to the lower row of pins to set logic low, or jump
the middle row of pins to the upper row of pins to
set logic high. If the HDR4 pins are left open, then
000 becomes the default address. The software
GUI is written to operate the DSA in Serial mode.
Use the software GUI to enable each setting to
the desired attenuation state. The software GUI
automatically programs the DSA each time an
attenuation state is enabled.
©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 17 of 20
PE43704
Product Specification
Figure 32. Evaluation Board Schematic
J1
HEADER16
2
1 CO_25
4
3
C0_5
6
5
C1
8
7
C2
10
9
C4
12
11 C8CLK
14
13 C16/DATA
16
15 LE
P/S
VDD_DIG
C6
C4
100pF
100pF
100pF
C2
C3
4
C7
4
SI 25
8 GND
GND 17
16 GND
RF2 18
15 GND
GND 19
7 RF1
1
D3
C9
0.1µF
C11
HDR2
3
2
4
HEADER_4
1
D4
C10
100pF
VDD
1
2
3
4
100pF
3
Z=50 Ohm
2
J5
142-0761-881/891
4
1
D5
C8 27
C4 28
C2 29
C16 26
VSS
VDD_DIG
DSA_50OHM_5X5_MLPQ32 VSS 20
6 GND
9 GND
2
1
A2 21
2
4
2
5 GND
J4
Z=50 Ohm
142-0761-881/891
U1
4 A0
14 GND
C8
0.1µF
A1 22
13 GND
C12
100pF
3 PS
12 GND
VDD
LE 23
3
HEADER3X3
CLK 24
2 VDD
11 GND
0 OHM
C1 30
CP25 32
1 GND
10 GND
R2
CP5 31
2
DNI
1
D2
A2_1
A0_2
A0 VDD
A1_1
A1_2
A1 VDD
A0_1
A2_2
A2 VDD
2 2
DNI
2
VDD_DIG
HDR4
R1
1
3
100pF
100pF
1 1
2 2
2
D1
C5
100pF
1 1
1
D0
100pF
HDR1
HEADER 1X2
1
6
3
C1
HDR3
HEADER 1X2
4
5
3
1
2
4
DNI
R3
1
D6
2
3
1
2
4
De-embeding trac
e
J10
J11
Z=50 Ohm
142-0761-881/891
142-0761-881/891
1
2
2
1
R4
0 OHM
DOC-16527
NOTES:
1. USE PRT-13505-01 PCB.
2. CAUTION:
CONTAINS PARTS AND ASSE MBLIES SUSCEPTIBLE
TO DAMAGE BY ELECTROSTATIC DISCHARGE (ESD)
©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 18 of 20
Document No. DOC-16514-6 |
UltraCMOS® RFIC Solutions
PE43704
Product Specification
Figure 33. Package Drawing
32-lead 5x5 QFN
A
0.10 C
(2X)
5.00
3.30±0.05
B
17
0.50
24
16
5.00
25
3.30±0.05
8
1
3.50
Pin #1 Corner
DOC-01872
0.10
0.05
0.05 C
5.20
RECOMMENDED LAND PATTERN
0.90 MAX
0.10 C
5.20
3.35
DETAIL A
BOTTOM VIEW
TOP VIEW
3.35
32
9
0.24±0.05
(X32)
0.50
(X28)
0.575
(x32)
3.50
0.10 C
(2X)
0.290
(x32)
0.375±0.05
(X32)
C A B
C
ALL FEATURES
SEATING PLANE
SIDE VIEW
0.203
Ref.
C
0.05
Figure 34. Top Marking Specification
43704
YYWW
ZZZZZZ
= Pin 1 designator
YYWW = Date Code, last two digits of the year and work week
ZZZZZZ = Six digits of the lot number
17-0091
Document No. DOC-16514-6 |
www.psemi.com
©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 19 of 20
PE43704
Product Specification
Figure 35. Tape and Reel Drawing
Tape Feed Direction
Notes:
1. 10 sprocket hole pitch cumulative tolerance ±.02
2. Camber not to exceed 1 mm in 100 mm
3. Material: PS + C
4. Ao and Bo measured as indicated
5. Ko measured from a plane on the inside bottom of the pocket to the
top surface of the carrier
6. Pocket position relative to sprocket hole measured as true position
of pocket, not pocket hole
Ao = 5.25 mm
Bo = 5.25 mm
Ko = 1.1 mm
Pin 1
Top of
Device
Device Orientation in Tape
Table 14. Ordering Information
Order Code
Description
Package
Shipping Method
PE43704MLCA-Z
PE43704 Digital step attenuator
32-lead 5x5 mm QFN
3000 units / T&R
EK43704-11
PE43704 Evaluation kit
Evaluation kit
1 / Box
Sales Contact and Information
For sales and contact information please visit www.psemi.com.
Advance Information: The product is in a formative or design stage. The datasheet contains design target
specifications for product development. Specifications and features may change in any manner without notice.
Preliminary Specification: The datasheet contains preliminary data. Additional data may be added at a later
date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best
possible product. Product Specification: The datasheet contains final data. In the event Peregrine decides to
change the specifications, Peregrine will notify customers of the intended changes by issuing a CNF (Customer
Notification Form).
The information in this datasheet is believed to be reliable. However, Peregrine assumes no liability for the use
of this information. Use shall be entirely at the user’s own risk.
©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 20 of 20
No patent rights or licenses to any circuits described in this datasheet are implied or granted to any third party.
Peregrine’s products are not designed or intended for use in devices or systems intended for surgical implant,
or in other applications intended to support or sustain life, or in any application in which the failure of the
Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no
liability for damages, including consequential or incidental damages, arising out of the use of its products in
such applications.
The Peregrine name, logo, UltraCMOS and UTSi are registered trademarks and HaRP, MultiSwitch and DuNE
are trademarks of Peregrine Semiconductor Corp. Peregrine products are protected under one or more of
the following U.S. Patents: http://patents.psemi.com.
Document No. DOC-16514-6 |
UltraCMOS® RFIC Solutions