Preliminary PLL601-03 Low Phase Noise PLL Clock Multiplier FEATURES • • • • • • • • Full swing CMOS outputs with 25 mA drive capability at TTL levels. Reference 10-30MHz crystal or clock. Integrated crystal load capacitor: no external load capacitor required. Output clocks up to 198MHz at 3.3V. Low phase noise (-126dBc/Hz @ 1kHz). Output Enable function. Low jitter (RMS): 6.4ps (period), 9.4ps (accum.) Advanced low power sub-micron CMOS process. 3.3V operation. Available in 16-Pin SOIC or TSSOP. CLK 1 16 GND REFEN 2 15 GND VDD 3 14 GND VDD 4 13 REFOUT VDD 5 12 OE XOUT 6 11 S0 S1 7 10 S3 XIN 8 9 S2 PLL 601-03 • • PIN CONFIGURATION DESCRIPTIONS The PLL601-03 is a low cost, high performance and low phase noise clock synthesizer. It implements PhaseLink’s proprietary analog and digital Phase Locked Loop techniques to allow the user to select the desired multiplier value. The chip accepts crystal or clock inputs ranging from 10 to 30MHz, depening on selected multiplier, and produces outputs clocks up to 198MHz at 3.3V. MULTIPLIER SELECT TABLE S3 S2 S1 S0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 1 1 1 0 1 1 Multiplier Xtal range Reserved 11x 10–18MHz 5x 20-30MHz Frequency Pass through 6x 11-22MHz BLOCK DIAGRAM S3 S2 S1 S0 ROM Based Multipliers Phase Locked Loop XIN XOUT XTAL OSC OE CLK REFOUT REFEN 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 06/15/01 Page 1 Preliminary PLL601-03 Low Phase Noise PLL Clock Multiplier PIN DESCRIPTIONS Name Number Type Description CLK 1 O Clock output from VCO. Equals the input frequency times multiplier. REFEN 2 I Reference clock enable. When Low, it turns off REFOUT. VDD 3,4,5 P 3.3V Power Supply. XIN 8 I Crystal input to be connected to 10-30MHz fundamental parallel mode crystal (C L =15pF). On chip load capacitors: No external capacitor required. XOUT 6 O Crystal Connection. OE 12 I Output Enable. Tri-state CLK and REFOUT when low. Has internal pull-up. REFOUT 13 O Buffered crystal oscillator clock output. Controlled by REFEN. S0 11 I Multiplier Select Pin 0. Determines CLK output. Has internal pull-up. S1 7 I Multiplier Select Pin 1. Determines CLK output. Has internal pull-up. S2 9 I Multiplier Select Pin 1. Determines CLK output. Has internal pull-up. S3 10 I Multiplier Select Pin 3. Determines CLK output. Has internal pull-up. GND 14,15,16 P Ground. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 06/15/01 Page 2 Preliminary PLL601-03 Low Phase Noise PLL Clock Multiplier ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS SYMBOL MIN. MAX. UNITS V CC - 0.5 7 V Input Voltage Range VI - 0.5 V CC + 0.5 V Output Voltage Range VO - 0.5 V CC + 0.5 V 260 °C -65 150 °C 0 70 °C Supply Voltage Range Soldering Temperature Storage Temperature TS Ambient Operating Temperature Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. 2. AC Specification PARAMETERS CONDITIONS MIN. Input Frequency Depends on selected multiplier 10 Output Frequency MAX. UNITS 30 MHz At 3.3V 160 MHz Output Rise Time 0.8V to 2.0V with no load 1.5 ns Output Fall Time 2.0V to 0.8V with no load 1.5 ns Duty Cycle At VDD/2 55 % Period jitter RMS With capacitive decoupling between VDD and GND 6.4 ps Accumulated jitter RMS With capacitive decoupling between VDD and GND 9.4 ps Phase Noise, relative to carrier, 155Mhz(x8) 100Hz offset, 3.3V -103 dBc/Hz Phase Noise, relative to carrier, 155Mhz(x8) 1kHz offset, 3.3V -126 dBc/Hz Phase Noise, relative to carrier, 155Mhz(x8) 10kHz offset, 3.3V -133 dBc/Hz Phase Noise, relative to carrier, 155Mhz(x8) 100kHz offset, 3.3V -128 dBc/Hz 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 45 TYP. 50 Rev 06/15/01 Page 3 Preliminary PLL601-03 Low Phase Noise PLL Clock Multiplier 3. DC Specification PARAMETERS SYMBOL CONDITIONS MIN. TYP. Operating Voltage VDD 3.135 Input High Voltage V IH 2 Input Low Voltage V IL Input High Voltage V IH For XIN pin Input Low Voltage V IL For XIN pin Output High Voltage V OH I OH = -25mA Output Low Voltage V OL I OL = 25mA Output High Voltage At CMOS Level V OH I OH = -8mA Operating Supply Current I DD No Load Short-circuit Current IS Input Capacitance C IN MAX. UNITS 3.465 V V 0.8 (VDD/2) + 1 VDD/2 VDD/2 V V (VDD/2) − 1 2.4 V V 0.4 VDD-0.4 OE, Select Pins V V 35 mA ±120 mA 5 pF 4. Crystal Specifications PARAMETERS SYMBOL CONDITIONS MIN. Crystal Resonator Frequency F XIN Parallel Fundamental Mode 10 Crystal Loading Capacitance Rating C L (xtal) 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 TYP. 15 MAX. UNITS 30 MHz pF Rev 06/15/01 Page 4 Preliminary PLL601-03 Low Phase Noise PLL Clock Multiplier PACKAGE INFORMATION 16 PIN Narrow SOIC, TSSOP ( mm ) SOIC TSSOP Symbol Min. Max. Min. Max. A 1.35 1.75 - 1.20 A1 0.10 0.25 0.05 0.15 B 0.33 0.51 0.19 0.30 C 0.19 0.25 0.09 0.20 D 9.80 10.00 4.90 5.10 E 3.80 4.00 4.30 H 5.80 6.20 L 0.40 e E H D 4.50 6.40 BSC 1.27 0.45 1.27 BSC 0.75 A A1 C 0.65 BSC B L e ORDERING INFORMATION For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PLL601-03 X C PART NUMBER TEMPERATURATURE C=COMMERCIAL M=MILITARY I=INDUSTRAL PACKAGE TYPE S=SOIC, O=TSSOP PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 06/15/01 Page 5