PLL PLL520-38

PLL520-38/-39
PECL and LVDS Low Phase Noise VCXO (for 65-130MHz Fund Xtal)
FEATURES
N/C
XIN
2
15
N/C
XOUT
3
14
GND
N/C
4
13
CLKC
N/C
5
12
VDD
OE
6
11
CLKT
VCON
7
10
N/C
GND
8
9
N/C
XIN
XOUT
Amplifier
w/
integrated
varicaps
Q
Q
N/C
N/C
12
13
11
10
9
14
N/C
15
OE
16
P520-3x
1
2
3
4
GND
XOUT
OE
VCON Oscillator
VDD
XIN
GND
BLOCK DIAGRAM
16
GND
The PLL520-38/-39 is a family of VCXO IC’s
specifically designed to pull high frequency
fundamental crystals from 65MHz to 130MHz, with
selectable PECL or LVDS outputs.. They achieve
very low current into the crystal resulting in better
overall stability. Their internal varicaps allow an on
chip frequency pulling, controlled by the VCON
input. Their very low jitter makes them ideal for the
most demanding timing requirements.
1
VDD
DESCRIPTION
VDD
VCON
65MHz to 130MHz Fundamental Mode Crystal.
Output range: 65MHz – 130MHz (no PLL).
Low Injection Power for crystal 50uW.
PECL (PLL520-38) or LVDS output (PLL520-39).
Integrated variable capacitors.
Supports 2.5V or 3.3V-Power Supply.
Available in 16-Pin (TSSOP or 3x3 QFN).
PLL 520-3x
•
•
•
•
•
•
•
PIN CONFIGURATION
8
GND
7
CLKC
6
VDD
5
CLKT
OUTPUT ENABLE LOGICAL LEVELS
Part #
PLL520-38
PLL520-38/-39
PLL520-39
OE
0
(Default)
1
0
1
(Default)
State
Output enabled
Tri-state
Tri-state
Output enabled
OE input: Logical states defined by PECL levels for PLL520-38
Logical states defined by CMOS levels for PLL520-39
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 1
PLL520-38/-39
PECL and LVDS Low Phase Noise VCXO (for 65-130MHz Fund Xtal)
PIN DESCRIPTIONS
Name
Number
Type
XIN
XOUT
OE
VCON
GND
CLKT
CLKC
N/C
VDD
2
3
6
7
8, 14
11
13
4,5,9,10,15,16
1, 12
I
I
I
I
P
O
O
P
Description
Crystal input. See Crystal Specifications on page 2.
Crystal output. See Crystal Specifications on page 2.
Output enable. See Output Enable Logic table on page 1.
Voltage control input.
Ground.
True output PECL (PLL520-38) or LVDS (PLL520-39).
Complementary output PECL (PLL520-38) or LVDS (PLL520-39).
Not connected.
Power supply.
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
SYMBOL
Supply Voltage
Input Voltage, dc
Output Voltage, dc
Storage Temperature
Ambient Operating Temperature*
Junction Temperature
Lead Temperature (soldering, 10s)
ESD Protection, Human Body Model
V DD
VI
VO
TS
TA
TJ
MIN.
-0.5
-0.5
-65
-40
MAX.
UNITS
4.6
V DD +0.5
V DD +0.5
150
85
125
260
2
V
V
V
°C
°C
°C
°C
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
* Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. Crystal Specifications
PARAMETERS
Built-in Capacitance
Inter-electrode capacitance
C0/C1 ratio (gamma)
Oscillation Frequency
SYMBOL
CONDITIONS
CX+
CXC0
65MHz to 130MHz
(VDD=3.3V)
γ
OF
Fund.
MIN.
TYP.
MAX.
UNITS
2
2
pF
300
130
MHz
2.6
65
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 2
PLL520-38/-39
PECL and LVDS Low Phase Noise VCXO (for 65-130MHz Fund Xtal)
3. Voltage Control Crystal Oscillator (3.3V)
PARAMETERS
SYMBOL
VCXO Stabilization Time *
CONDITIONS
T VCXOSTB
From power valid
F XIN = 100 – 200MHz;
XTAL C 0 /C 1 < 250
0V ≤ VCON ≤ 3.3V
VCON=1.65V, ±1.65V
VCON = 0 to 3.3V
VCXO Tuning Range
CLK output pullability
On-chip Varicaps control range
Linearity
VCXO Tuning Characteristic
VCON input impedance
VCON modulation BW
MIN.
TYP.
MAX.
UNITS
10
ms
200*
ppm
±100*
4 – 18*
10*
65
60
0V ≤ VCON ≤ 3.3V, -3dB
ppm
pF
%
ppm/V
kΩ
kHz
25
Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits.
4. General Electrical Specifications
PARAMETERS
SYMBOL
Supply Current (Loaded
Outputs)
Operating Voltage
I DD
CONDITIONS
MIN.
PECL/LVDS
V DD
2.97
45
45
@ 1.25V (LVDS)
@ V DD – 1.3V (PECL)
Output Clock Duty Cycle
TYP.
50
50
±50
Short Circuit Current
MAX.
UNITS
100/80
mA
3.63
55
55
V
%
mA
5. Jitter Specifications
PARAMETERS
CONDITIONS
Period jitter RMS
Period jitter peak-to-peak
Integrated jitter RMS
MIN.
77.76MHz
77.76MHz
Integrated 12 kHz to 20 MHz at 77.76MHz
TYP.
MAX.
2.5
18.5
0.5
UNITS
ps
ps
ps
6. Phase Noise Specifications
PARAMETERS
Phase Noise relative
to carrier
FREQUENCY
@10Hz
@100Hz
@1kHz
@10kHz
@100kHz
UNITS
77.76MHz
-75
-95
-125
-145
-155
dBc/Hz
Note: Phase Noise measured at VCON = 0V
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 3
PLL520-38/-39
PECL and LVDS Low Phase Noise VCXO (for 65-130MHz Fund Xtal)
7. LVDS Electrical Characteristics
PARAMETERS
SYMBOL
Output Differential Voltage
V DD Magnitude Change
Output High Voltage
Output Low Voltage
Offset Voltage
Offset Magnitude Change
∆V OD
V OH
V OL
V OS
Power-off Leakage
I OXD
Output Short Circuit Current
I OSD
CONDITIONS
V OD
R L = 100 Ω
(see figure)
MIN.
TYP.
MAX.
UNITS
247
-50
355
454
50
1.6
0.9
1.125
0
∆V OS
V out = V DD or GND
V DD = 0V
1.4
1.1
1.2
3
1.375
25
mV
mV
V
V
V
mV
±1
±10
uA
-5.7
-8
mA
8. LVDS Switching Characteristics
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Differential Clock Rise Time
tr
0.2
0.7
1.0
ns
Differential Clock Fall Time
tf
R L = 100 Ω
C L = 10 pF
(see figure)
0.2
0.7
1.0
ns
LVDS Levels Test Circuit
LVDS Switching Test Circuit
OUT
OUT
CL = 10pF
50Ω
VOD
VDIFF
VOS
RL = 100Ω
50Ω
CL = 10pF
OUT
OUT
LVDS Transistion Time Waveform
OUT
0V (Differential)
OUT
80%
VDIFF
80%
0V
20%
20%
tR
tF
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 4
PLL520-38/-39
PECL and LVDS Low Phase Noise VCXO (for 65-130MHz Fund Xtal)
9. PECL Electrical Characteristics
PARAMETERS
SYMBOL
CONDITIONS
MIN.
V OH
V OL
R L = 50 Ω to (V DD – 2V)
(see figure)
V DD – 1.025
Output High Voltage
Output Low Voltage
MAX.
UNITS
V DD – 1.620
V
V
10. PECL Switching Characteristics
PARAMETERS
SYMBOL
Clock Rise Time
Clock Fall Time
tr
tf
CONDITIONS
MIN.
@20/80% - PECL
@80/20% - PECL
PECL Levels Test Circuit
OUT
MAX.
UNITS
0.6
0.5
1.5
1.5
ns
ns
PECL Output Skew
VDD
50Ω
TYP.
OUT
2.0V
50%
50Ω
OUT
tSKEW
OUT
PECL Transistion Time Waveform
DUTY CYCLE
45 - 55%
55 - 45%
OUT
80%
50%
20%
OUT
tR
tF
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 5
PLL520-38/-39
PECL and LVDS Low Phase Noise VCXO (for 65-130MHz Fund Xtal)
PACKAGE INFORMATION
16 PIN TSSOP ( m m )
Sym bol
A
A1
B
C
D
E
H
L
e
M in.
M ax.
1.20
0.05
0.15
0.19
0.30
0.09
0.20
4.90
5.10
4.30
4.50
6.40 BSC
0.45
0.75
0.65 BSC
E
H
D
A
A1
C
e
B
L
3x3mm QFN
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 6
PLL520-38/-39
PECL and LVDS Low Phase Noise VCXO (for 65-130MHz Fund Xtal)
ORDERING INFORMATION
For part ordering, please contact our Sales Department:
47745 Fremont Blvd., Fremont, CA 94538, USA
Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
The order number for this device is a combination of the following:
Device number, Package type and Operating temperature range
PLL520-3x O C
PART NUMBER
TEMPERATURE
C=COMMERCIAL
I=INDUSTRAL
PACKAGE TYPE
O=TSSOP Q=QFN
Order Number
Marking
Package Option
PLL520-38OC
PLL520-38OC-R
PLL520-38QC
PLL520-38QC-R
P520-38OC
P520-38OC
P520-38QC
P520-38QC
TSSOP - Tube
TSSOP - Tape & Reel
QFN - Tube
QFN - Tape & Reel
PLL520-39OC
PLL520-39OC-R
PLL520-39QC
PLL520-39QC-R
P520-39OC
P520-39OC
P520-39QC
P520-39QC
TSSOP - Tube
TSSOP - Tape & Reel
QFN - Tube
QFN - Tape & Reel
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information
furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the
express written approval of the President of PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 7