MPT57216 192-CHANNEL COLOR TFT COLUMN (SOURCE) DRIVER SGLS092 – MARCH 1997 192 OUT0 OUT3 OUT13 OUT181 OUT183 OUT189 D D D D Clock-Control Circuit Conserves Power Consumption Power Supply Voltage of 5 V ±10% High-Voltage CMOS SI Gate Technology 231-Pin TAB (Tape Automated Bonding) Functional Equivalent of MPT57206 OUT11 D Column (Source) Driver VEE of 14 V to 18 V for LCD Driving 192 Channel Outputs Data Bus With 3 x 3 (RGB) Bits 512 Colors (8 Gray Scale) 15-MHz Data Transfer Clock OUT191 D D D D D D 1 MPT57216 IC 224 231 V5 V6 V7 MODE CL LS EIO1 VSS1 220 R/L V EE V0 V1 210 V0 VSS2 EIO2 DSEL VDD C32 C31 C30 C22 C21 C20 C12 C11 C10 CLK V2 V1 200 TEST1 TEST2 V7 V6 193 NOTE A: Pin numbering is for reference only to the function table. The pin numbering in this figure does not correspond to the numbering on the custom tape. description The MPT57216 is a 192-channel color thin-film transistor (TFT) LCD driver based on an active matrix LCD (AMLCD). It has 3 bits for each RGB input. These 3 bits are decoded internally to select one of eight bias-voltage levels, V0 to V7 for output, in order to support 512 colors (R = 23 = 8; G = 23 = 8; B = 23 = 8; RGB = 29 = 512). Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1997, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 MPT57216 192-CHANNEL COLOR TFT COLUMN (SOURCE) DRIVER SGLS092 – MARCH 1997 functional block diagram CLK EIO1 EIO2 Clock Control Circuit LS R/L Data Bus 64-Bit Shift Register CL 64 3 3 64) 3 192 9-Bit Data Latch Data Memory (9 192) 3 192 Display Latch (3 C32 C31 C30 C22 C21 C20 C12 C11 C10 DSEL 192) 8 192 3 to 8 Decoder (8 TEST1 TEST2 See Note A 192 MODE V7 V6 V5 V4 V3 V2 V1 V0 VDD 8 Bits Level Shifter 8 192 VEE V7 V6 V5 V4 V3 V2 V1 V0 8-Level 192-Channel LCD Driver VSS1 NOTE A: These terminals are for factory testing only and should be left open. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 OUT191 OUT190 OUT189 OUT188 OUT187 OUT186 OUT185 OUT184 OUT8 OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1 OUT0 VSS2 MPT57216 192-CHANNEL COLOR TFT COLUMN (SOURCE) DRIVER SGLS092 – MARCH 1997 power supply circuit 5V Timing DSEL VDD VEE From Controller – + V0 – + V1 – + V2 – + V3 – + V4 – + V5 – + V6 – + V7 MPT57216 VSS1, 2 Frame Signal Logic GND (0 V) HV GND (0 V) NOTE A: Separation between high voltage GND line and logic GND line is recommended to avoid noise problems. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 MPT57216 192-CHANNEL COLOR TFT COLUMN (SOURCE) DRIVER SGLS092 – MARCH 1997 decoding for OUT0 – OUT191 P-Ch V0 N-Ch SEL0 P-Ch V1 N-Ch SEL1 Output Pin (OUT0 – OUT191) OUTn Terminal P-Ch V7 N-Ch SEL7 NOTE A. The C32 – C10 inputs are decoded internally to derive SEL0 – SEL7 from the output of a 3-to-8 decoder. Only one of the decoder outputs, SEL0 – SEL7, puts ≈VEE on the P-CH and ≈VSS on the N-CH of its corresponding transmission gate. This allows only one of eight bias voltages, V0 – V7, to pass onto OUTn. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MPT57216 192-CHANNEL COLOR TFT COLUMN (SOURCE) DRIVER SGLS092 – MARCH 1997 Terminal Functions NAME TERMINAL I/O C32 C31 C30 C22 C21 C20 C12 C11 C10 207 208 209 210 211 212 213 214 215 I FUNCTION CL 217 I Clear input. This active-low clear input resets the clock control circuit, shift register, data memory, and display latch. CL also sets output to the V0 level. CL must be asserted high for normal operation. CLK 216 I Clock input. CLK is the rising edge systems clock for the 64-bit shift register. Also, 9 bits of data are stored in the data memory by the falling edge of CLK. The clock control circuit stops the internal system clock to save power consumption after 64 clocks. DSEL 205 I Data select input. This input inverts the data on C10 to C32 input. RGB color data input. These nine inputs of 3-bit input data at each of 3 RGB ports selects up to 8-levels of grey scale on the LCD outputs. For Cmn: m = port number and n = weight selected. INPUT OUTPUT C32 C22 C12 C31 C21 C11 C30 C20 C10 DSEL = L (Noninverted) DESEL = H (Inverted) 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 V7 V6 V5 V4 V3 V2 V1 V0 V0 V1 V2 V3 V4 V5 V6 V7 INPUT DATA EIO1 EIO2 219 204 I/O DATA MEMORY C10 to C32 DSEL = L DSEL = H 0 0 1 1 1 0 Enable I/O. EIO1 and EIO2 are data enable input/output for cascade interface. R/L EIO1 EIO2 H (Left Shift) Cascade Input Cascade Output (OUT0 – OUT191) L (Right Shift) Cascade Output Cascade Input (OUT191 – OUT0) LS 218 I Latch Strobe Input. When LS is high, 9 x 64 bits of data memory is latched into the display latch (3 x 192) and passed through a 3-to-8 decoder. The decoder selects one of eight bias voltage V0 – V7 to be passed on to OUTn using a transmission gate. LS also clears the shift register and clock control circuit. MODE 231 I Mode input. MODE is used for factory testing only and should be left open. The internal pullup resistors connected to VDD force the inputs into a high state. OUT0 – OUT191 1 – 192 O 192-channel output for RGB color LCD display. C1x, C2x, and C3x select bias voltages, V0 – V7, on OUT(3n), OUT(3n+1), and OUT(3n+2), where n = 0 – 63, respectively. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 MPT57216 192-CHANNEL COLOR TFT COLUMN (SOURCE) DRIVER SGLS092 – MARCH 1997 Terminal Functions (continued) NAME TERMINAL I/O FUNCTION R/L 221 I Select right/left shift. R/L selects which direction the EIOn enable pulse advances through the 64-bit shift register. It also selects which direction the 3-bit × 3 RGB data from the data latch is loaded into three different but adjacent channels of data memory. This data is loaded as the channels are enabled three at a time by the enable pulse from the shift register. It advances from one output to the next when shifting through the shift register with each clock pulse. R/L H L Shift Direction Left Right EIO1 Input Output EIO2 Output Input CLK . . . . . 64 2, 5, 8, . . . . . 191 1, 4, 7, . . . . . 190 0, 3, 6, . . . . . 189 . . . . . 64 191, 188, 185, . . . . . 2 190, 187, 184, . . . . . 1 189, 186, 183, . . . . . 0 C32 – C30 C22 – C20 C12 – C10 6 1, 2, 3, 1, 2, 3, TEST1 TEST2 193 194 I Test input. TEST1 and TEST2 are used for factory testing only and should be left open. The internal pullup resistors connected to VDD force the inputs into a high state. V0 – V7 V0 – V7 202 – 195 223 – 230 I Eight-level input bias voltage for output buffer. After the three bits for each RGB color are decoded, the device outputs one voltage level from the eight possible bias voltages (V0 – V7). There is no priority on the V0 to V7 terminals. A pair of V0 to V7 bias voltage terminals are provided. Each pair of terminals is required to be connected together externally. VDD 206 5-V supply input for logic circuits VEE 222 Supply input for level shifter and output transmission gate. VSS1 VSS2 220 203 Ground terminals POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MPT57216 192-CHANNEL COLOR TFT COLUMN (SOURCE) DRIVER SGLS092 – MARCH 1997 1 2 64 128 65 129 320 1 2 320 CLK Driver1 EIO1 Driver1 EIO2 Driver2 EIO1 Driver2 EIO2 1st Frame Data Latch Driver 1 Driver 2 Drivers 3 – 5 Drivers 1 – 5 C10 R11 R12 R164 R11 R164 R11 R164 R11 R12 R164 C11 R21 R22 R264 R21 R264 R21 R264 R21 R22 R264 C12 R31 R32 R364 R31 R364 R31 R364 R31 R32 R364 C20 G11 G12 G164 G11 G164 G11 G164 G11 G12 G164 C32 B31 B32 B364 B31 B364 B31 B364 B31 B32 B364 LS OUT 0 – 191 1st Frame Data Output Figure 1. Timing Diagram (R/L = H) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 MPT57216 192-CHANNEL COLOR TFT COLUMN (SOURCE) DRIVER SGLS092 – MARCH 1997 absolute maximum ratings over operating free-air temperature range† Supply voltage range, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V Supply voltage range for LCD, VEE . – 0.3 V to 22 V Input voltage range, VI (CLK, LS, R/L, CL, C32 to C10, DSEL, EIO1, EIO2) . . . . . . – 0.3 V to VDD + 0.3 V Output voltage range, VO (E101, E102) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VDD + 0.3 V Output bias voltage range for LCD, Vx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to VDD + 0.6 V Input current, II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 10 mA Output current, IO: E101, E102 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA OUT0 to OUT191 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA Power dissipation, PD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 W Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55 to 125°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: Voltage values are with respect to VSS1 and VSS2 recommended operating conditions MIN NOM MAX 5 UNIT Supply voltage, VDD See Note 2 4.5 5.5 V Supply voltage, VEE See Note 2 14 18 V Output bias voltage for LCD driver V0, V1, V2, V3, V4, V5, V6, V7 See Note 2 0 VEE V High-level input voltage, VIH CLK, LS, DSEL, R/L, CL, EIO1, EIO2, C32 to C10 0.8 VDD V Low-level input voltage, VIL CLK, LS, DSEL, R/L, CL, EIO1, EIO2, C32 to C10 VSS VDD 0.2 VDD Clock frequency at CLK, f(CLK) CLK Clock frequency at LS, f(LS) LS Operating free-air temperature, TA – 55 NOTE 2: Turn-on and -off sequence of power must be as follows: Turn-on sequence: VDD → Logic Input → VEE → V7 to V0 Turn-off sequence: V7 to V0 → VEE → Input → VDD 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 V 15 MHZ 100 kHz 125 °C MPT57216 192-CHANNEL COLOR TFT COLUMN (SOURCE) DRIVER SGLS092 – MARCH 1997 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH VOL TEST CONDITIONS High-level output voltage E101, E102 IOH = – 0.3 mA IOH = 0.3 mA Low-level output voltage E101, E102 IIH High-level input current CLK, DSEL, LS, R/L, CL, EIO1, EIO2, C32 to C10 IIL Low-level input current Ilkg MIN MAX VDD – 0.4 UNIT V 0.4 V VIH = VDD 10 µA CLK, DSEL, LS, R/L, CL, EIO1, EIO2, C32 to C10 VIL = VSS 10 µA Input leakage current V7 to V0 VSS < Vx < VEE 100 µA ∆VIO Voltage difference between Vx to OUTn (voltage variance) Vx - OUTn II/O = ± 10 µA, 50 mV Ro(on) Output resistance OUT0 – OUT191 5 kΩ IDD Supply current VDD IO = ± 100 µA f(CLK) = 15 MHZ, f(LS) = 30 KHZ, VEE = 18V f(EIOxin) = 30 KHZ, VDD = 5.5 V, 4 mA IEE Supply current VEE f(EIOxin) = 30 KHZ, VDD = 5 V, 1 mA VDD f(CLK) = 15 MHZ, f(LS) = 30 KHZ, VEE = 17V VDD = 5 V, See Note 3 VEE = 17 V 300 µA VEE VDD = 5 V, See Note 3 VEE = 17 V 100 µA II( t db ) I(standby) Standby current – 100 VSS < Vx < VEE NOTE 3: Test conditions of standby current are added at R/L = VDD, and EIO1 = VSS. timing requirements, VDD = 5 V, TA = –55°C to 125°C PARAMETER tCLK Clock cycle time tW(L) Low-level pulse width tw(H) High-level pulse width tsu Data setup time th tw(EN) TEST CONDITIONS MIN MAX UNIT See Figures 2 and 4 66 ns See Figure 2 23 ns See Figure 2 18 ns Cxx – CLK See Figure 4 10 ns Data hold time CLK – Cxx See Figure 4 15 ns Enable high-level pulse width EIO1, EIO2 See Figure 2 1/fCLK CLK ns tsu(EN) Enable setup time EIOx – CLK See Figure 2 20 30 or 1/fCLK th(EN) Enable hold time CLK – EIOx See Figure 2 10 tCLK × 62 tw(LS) Latch strobe high-level pulse width See Figure 3 40 ns tsu(LS) LS setup time See Figure 3 66 ns th(LS) LS hold time See Figure 2 40 ns tsu(DSEL) DSEL setup time See Figure 2 66 ns LS EIOx – DSEL POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ns ns 9 MPT57216 192-CHANNEL COLOR TFT COLUMN (SOURCE) DRIVER SGLS092 – MARCH 1997 switching characteristics, VDD = 5 V, TA = –55°C to 125°C over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX UNIT tp(EN) Enable propagation delay time CLK – EIOx CL = 35 pF, See Note 4 and Figure 4 40 ns tp(OUT) Output propagation delay time LS – OUTn CL = 200 pF, See Note 4 and Figure 3 3.0 µs NOTE 4: CL includes probe and jig capacitance. PARAMETER MEASUREMENT INFORMATION tw(H) tf tCLK tr CLK (1st) tw(L) tsu(EN) th(EN) EIOx (IN) (1st EIOx) tr(EN) tf(EN) tw(EN) th(LS) LS tsu(DSEL) DSEL NOTES: A. Input pulse generators have the following characteristics: PRR ≤ 1 MHz, duty cycle ≤ 50%, tr ≤ 15 ns, tf ≤ 15 ns, zo = 50 Ω. B. VIH and VIL for all waveforms are at 0.8 VDD and 0.2 VDD respectively. C. All timing parameters and measurements are referenced at the 0.5 VDD point of each waveform. Figure 2. EIOx (IN), LS, and DSEL Timing Waveforms 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MPT57216 192-CHANNEL COLOR TFT COLUMN (SOURCE) DRIVER SGLS092 – MARCH 1997 PARAMETER MEASUREMENT INFORMATION Case of Clock(CLK) Restart (See Note A) CLK (1H Last) (See Note B) Case of Clock(CLK) Suspend tsu(LS) tw(LS) LS tr(LS) tf(LS) tp(OUT) OUTn V0 Level (See Notes C and D) Vx Level NOTES: A. Case of data input change: if data has changed after the last clock of 1H, then it is recommended to add a dummy clock of one pulse after the last 1H pulse of the clock. B. Case of suspending clock (CLK) after data transfer (1H) completion: it is recommended that the data input not be changed while the clock is suspended. C. All timing parameters and measurements are referenced at the 0.5 VDD point of each waveform except tp(OUT) on the OUTn waveform. The reference point on the OUTn waveform is V0 + 0.1 Vx for positive-going transitions and V0 – 0.1 Vx for negative-going transitions. D. OUTn waveform transitions are from V0 level to Vx level. Maximum V0 and Vx levels are 8.0 V due to tester limitations. E. Input pulse generators have the following characteristics: PRR ≤ 1 MHz, duty cycle ≤ 50%, tr ≤ 15 ns, tf ≤ 15 ns, zo = 50 Ω. F. VIH and VIL for all waveforms are at 0.8 VDD and 0.2 VDD respectively. Figure 3. LS and OUTn Timing Waveforms CLK 64 1 2 tCLK 3 th tsu 64th Data C32 – C10 Next 1st Data tp(EN) VOH EIOx (OUT) VOL NOTES: A. Input pulse generators have the following characteristics: PRR ≤ 1 MHz, duty cycle ≤ 50%, tr ≤ 15 ns, tf ≤ 15 ns, zo = 50 Ω. B. VIH and VIL for all waveforms are at 0.8 VDD and 0.2 VDD respectively. C. All timing parameters and measurements are referenced at the 0.5 VDD point of each waveform. Figure 4. Cxx and EIOx (OUT) Timing Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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