SILAN SC7312

SC7312
4-CH OUTPUT STEREO AUDIO PROCESSOR WITH 4 STEREO INPUTS AND
TONE/VOLUME CONTROL
DESCRIPTION
The SC7312 is a volume, tone (bass and treble), balance (left/ right)
and fader(front/rear) processor for quality audio applications in car radio
and Hi-Fi systems. Selectable input gain and external loudness function
are provided. Control is accomplished by serial I2C bus microprocessor
interface. The AC signal settings is obtained by resistor networks and
switches combined with operational amplifiers. Due to the Used CMOS
technology, low distortion, low noise and low DC stepping are obtained.
SOP-32-375-1.27
FEATURES
* Input multiplexer:
--4 stereo inputs
--Selectable input gain for optimal adaptation to different
sources
* Four speaker attenuators:
--4 independent speakers control in 1.25dB steps for
ORDERING INFORMATION
Device
SC7312S
Package
SOP-32-375-1.27
balance and fader facilities
--Independent mute function
* All functions programmable via serial I 2C Bus
* Loudness function
* Volume control in 1.25dB steps
* Treble and bass control
* Input and output for external
equalizer or noise reduction system
BLOCK DIAGRAM
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SC7312
ABSOLUTE MAXIMUM RATINGS
Characteristics
Symbol
Ratings
Unit
VS
10.2
V
Operating Temperature
Tamb
-40 ~ +85
°C
Storage Temperature
Tstg
-55 ~ +150
°C
Supply Voltages
QUICK REFERENCE DATA
Characteristics
Symbol
Min.
Typ.
Max.
Unit
Vs
6
9
10
V
Maximum Input Signal Handling
VCL
2
Total Harmonic Distortion ,V=1Vrms,
THD
0.01
Signal to Noise Ratio
S/N
106
dB
Channel Separation, f=1kHz
Sc
103
dB
Supply Voltage
Vrms
0.1
%
f=1kHz
Volume Control, 1.25dB step
-78.75
0
dB
Bass and Treble Control, 2dB step
-14
+14
dB
Fader and Balance Control, 1.25dB
-38.75
0
dB
0
11.25
dB
step
Input Gain, 3.75dB Step
Mute Attenuation
100
dB
ELECTRICAL CHARACTERISTICS (Refer to the test circuit)
(Tamb=25°C, VS=9.0V, RL=10kΩ, RG=600Ω, all controls flat(G=0), f=1kHz,Unless otherwise specified)
Characteristics
Symbol
Test conditions
Min.
Typ.
Max.
Unit
6
9
10.0
V
20.0
35.0
mA
SUPPLY VOLTAGE
Operating Supply Voltage
VS
Operating Supply Current
IS
Ripple Rejection of Supply Voltage
SVR
60
80
35
50
dB
INPUTS SELECTORS
Input Resistance
RII
Input 1, 2, 3, 4
Clipping Level
VCL
2
2.5
Vrms
Input Separation (note 2)
SIN
80
100
dB
Output Load Resistance
RL
Pin 8, 21
70
4
kΩ
Minimum Input Gain
GIN(MIN)
Maximum Input gain
GIN(MAX)
11.25
dB
Step Resolution
GSTEP
3.75
dB
G=11.25dB
2
µV
Adjacent gain steps
4
G=18.75 to MUTE
4
Input Noise
eIN
DC Steps
VDC
-1
kΩ
0
1
20
dB
mV
mV
(To be continued)
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SC7312
(Continued)
Characteristics
Symbol
Test conditions
Min.
Typ.
Max.
Unit
RIV
20
33
50
kΩ
Crange
70
75
80
dB
Minimum Attenuation
AV(min)
-1
0
1
dB
Maximum Attenuation
AV(max)
70
75
80
dB
ASTEP
0.5
1.25
1.75
dB
-1.25
0
1.25
VOLUME CONTROL
Input Resistance
Control Range
Step Resolution
Attenuation Set Error
EA
Tracking Error
ET
DC Steps
VDC
AV=0 to –20dB
AV=-20 to –60dB
-3
Adjacent attenuation steps
From 0dB to AV max
2
dB
2
dB
0
3
mV
0.5
7.5
mV
SPEAKER ATTENUATORS
Control Range
Crange
35
37.5
40
dB
Step Resolution
SSTEP
0.5
1.25
1.75
dB
1.5
dB
Attenuation Set Error
Output Mute Attenuation
DC Steps
EA
AMUTE
VDC
80
100
dB
Adjacent attenuation steps
0
3
mV
From 0dB to MUTE
1
10
mV
±12
±14
±16
dB
BASS CONTROL (note 1)
Control Range
GB
Step Resolution
BSTEP
1
2
3
dB
RB
34
44
58
kΩ
±13
±14
±15
dB
1
2
3
dB
2
2.5
Internal Feedback Resistance
Maximum boost/cut
TREBLE CONTROL (note 1)
Control Range
Gt
Step Resolution
TSTEP
Maximum boost/cut
AUDIO OUTPUTS
Clipping Level
VOCL
Output Load Resistance
RL
Output load Capacitance
CL
THD=0.3%
Vrms
4
kΩ
10
nF
Output Resistance
ROUT
30
75
120
Ω
DC Voltage Level
VOUT
4.2
4.5
4.8
V
GENERAL
BW=20 ~20kHz,flat
µV
2.5
output muted
Output Noise
eNO
BW=20 ~20kHz,flat
5
15
µV
All gains=0dB
A curve, all gains =0 dB
Signal to Noise Ratio
S/N
All gains=0dB; Vo=1Vrms
3
µV
106
dB
(To be continued)
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SC7312
(Continued)
Characteristics
Symbol
Distortion
d
Channel Separation Left/right
Test conditions
Min.
Typ.
Max.
Unit
Av=0,VIN=10mV
0.01
0.1
%
Av=-20dB, VIN=1Vrms
0.09
0.3
%
Av=-20dB,VIN=0.3Vrms
0.04
%
103
dB
Sc
Total Tracking Error
80
AV=0 to –20 dB
0
1
dB
AV=-20 to –60 dB
0
2
dB
1
V
+5
µA
0.4
V
BUS INPUTS
Input Low Voltage
VIL
Input High Voltage
VIH
3
Input Current
IIN
-5
Output Voltage SDA Acknowledge
Vo
V
IO=1.6mA
NOTES:
(1) Bass and treble response see Figure 16. The center frequency and quality of the response behavior can be
chosen by the external circuitry. A standard first order bass response can realized by a standard feedback
network.
(2) The selected input is grounded through the 2.2µF capacitor.
PIN CONFIGURATIONS
CREF
1
32 SCL
VDD
2
31 SDA
GND
3
30 DIG GND
CODE
4
29 OUT LF
L
5
28 OUT RF
R
6
27 OUT LR
IN(R)
7
26 OUT RR
OUT(R)
8
LOUD R
9
BUS
INPUTS
TREBLE
SC7312
R4 10
24 BIN(R)
BASS
23 BOUT(L)
R3 11
22 BIN(L)
R2 12
21 OUT(L)
R1 13
20 IN(L)
NC 14
19 L1
LOUD L 15
18 L2
RIGHT
INPUTS
LEFT INPUTS —
L4 16
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25 BOUT(R)
LEFT INPUTS
17 L3
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SC7312
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Loudness (dB)
THD & Noise (%)
Channel Separation (dB)
THD (%)
THD & Noise (%)
Noise ( V)
Noise ( V)
Loudness (dB)
Loudness (dB)
TYPICAL CHARACTERISTICS PERFORMANCE
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SC7312
TYPICAL CHARACTERISTICS PERFORMANCE (continued)
Fig.10 Input Separation
( L1,L2,L3,L4) vs. Frequency
Fig.11 Supply Voltage Rejection
vs. Frequency
100
VIN=1Vrms
AV=0dB
All controls Flat
90
80
Output Clipping Level (v)
100
Channel Separation (dB)
Channel Separation (dB)
110
Fig.12 Output Clipping Level vs.
Supply Voltage
90
80
70
Vsvr=0.5Vrms
All Input to GND
AV=0dB
All controls Flat
60
5.0
RL=10k
f=1kHz
THD=0.3%
4.0
3.0
2.0
70
1.0
2
10
3
10
4
10
1
10
2
10
3
10
4
10
4
6
8
10
12
Frequency (Hz)
Frequency (Hz)
Supply Voltage (V)
Fig.13 Quiescent current vs. Supply
Voltage
Fig.14 Supply current vs.
Temperature
Fig.15 Bass resistance vs.
Temperature
8.0
6.0
4.0
50
8.5
48
)
9.0
Bass Resistance (
Quiescent Current (mA)
Quiescent Current (mA)
1
10
8.0
Vs=9V
7.5
7.0
4
6
8
10
12
44
42
6.5
2.0
46
40
-60
-30
0
30
60
90
Temperature ( )
Supply Voltage (V)
-60
-30
0
30
Temperature (
60
90
)
Fig.16 Typical Tone Response
(with the Ext components indicated
the test circuit)
15
AV=0dB
Tone Response (dB)
10
5
0
-5
-10
-15
1
10
2
10
3
10
4
10
Frequency (Hz)
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SC7312
APPLICATION NOTES
1. I2C BUS INTERFACE
Data transmission from microprocessor to the SC7312 and viceversa takes place through the 2 wires I 2C BUS
interface, consisting of the two lines SDA and SCL(pull-up resistors to positive supply voltage must be
connected).
2. DATA VALIDITY
As shown in Figure 17, the data of the SDA line must be stable during the high period of the clock. The HIGH
and LOW state of the dtat line can only change when the clock signal on the SCL line is LOW.
Fig. 17 Data Validity on the I2C BUS
3. START AND STOP CONDITIONS
As shown in Figure 18, a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The
stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH.
Fig. 18 Timing diagram of I2C BUS
4. BYTE FORMAT
Every byte transferred on the SDA line must obtain 8 bits. Each byte must be followed by the an acknowledge
bit. The MSB is transferred first.
5. ACKNOWLEDGE
The master(microprocessor) puts a resistive HIGH level on the SDA line during the acknowledge clock
pulse(see Figure 19). The peripheral(audioprocessor) that acknowledges has to pull-down(LOW) the SDA line
during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse.
The audioprocessor which has been addressed has to generate an acknowledge after the reception of each
byte , otherwise the SDA line remain at the HIGH level during the ninth clock pulse time. In this case the master
transmitter can generate the STOP information in order to abort the transfer.
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SC7312
Fig. 19 Acknowledge on the I2C BUS
6. Transmission without acknowledge
Avoiding to detect the acknowledge of the audioprocessor, the microprocessor can use a simpler transmission:
simply it waits one clock without checking the slave acknowledgig, and sends the new data.
This approach of course is less protected from mis-working and decreases the noise immunity.
SOFTWARE SPECIFICATION
1. Interface protocol
The interface protocol comprises:
•
•
A start conditions
A chip address byte, containing the SC7312 address(the 8th bit of the bytes must be 0). The SC7312
must always acknowledge at the end of each transmitted byte.
•
•
A sequence of data(N-bytes + acknowledge)
A stop condition (P)
2. Chips address
1 (MSB)
0
0
0
1
0
0
0 (LSB)
3. Data bytes
MSB
LSB
Function
0
0
B2
B1
B0
A2
A1
A0
Volume Control
1
1
0
B1
B0
A2
A1
A0
Speaker ATT LR
1
1
1
B1
B0
A2
A1
A0
Speaker ATT RR
1
0
0
B1
B0
A2
A1
A0
Speaker ATT LF
1
0
1
B1
B0
A2
A1
A0
Speaker ATT RF
0
1
0
G1
G0
S2
S1
S0
Audio switch
0
1
1
0
C3
C2
C1
C0
Bass control
0
1
1
1
C3
C2
C1
C0
Treble control
Note: Ax=1.25dB steps;Bx=10dB steps;Cx=2dB steps;Gx=3.75dB steps
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SC7312
DETAILED DESCRIPTION OF DATA BYTES
1. Volume
MSB
0
0
0
0
B2
B1
B0
LSB
Function
A2
A1
A0
Volume 1.25dB steps
0
0
0
0
0
0
1
-1.25
0
1
0
-2.5
0
1
1
-3.75
1
0
0
-5
1
0
1
-6.25
1
1
0
-7.5
1
1
1
-8.75
A2
A1
A0
Volume 10dB steps
B2
B1
B0
0
0
0
0
0
0
1
-10
0
1
0
-20
0
1
1
-30
1
0
0
-40
1
0
1
-50
1
1
0
-60
1
1
1
-70
For example, a volume of –45dB is given by: 00100100
2. speaker attenuators
MSB
LSB
Function
1
0
0
B1
B0
A2
A1
A0
Speaker ATT LF
1
0
1
B1
B0
A2
A1
A0
Speaker ATT RF
1
1
0
B1
B0
A2
A1
A0
Speaker ATT LR
1
1
1
B1
B0
A2
A1
A0
Speaker ATT RR
0
0
0
0
0
0
1
-1.25
0
1
0
-2.5
0
1
1
-3.75
1
0
0
-5
1
0
1
-6.25
1
1
0
-7.5
1
1
1
-8.75
0
0
0
0
1
-10
1
0
-20
1
1
-30
1
1
1
1
1
MUTE
For example, attenuation of 25dB on speaker RF is given by: 10110100
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SC7312
3.Audio switch
MSB
0
1
0
G1
G0
S2
LSB
Function
S1
S0
Audio switch
0
0
Stereo 1
0
1
Stereo 2
1
0
Stereo 3
1
1
Stereo 4
0
Loudness ON
1
Loudness OFF
0
0
+11.25dB
0
1
+7.5dB
1
0
+3.75dB
1
1
0dB
For example, to select the stereo 2 input with a gain of +7.5dB Loudness ON the 8bit string is: 01001001
4.Bass and treble
MSB
LSB
Function
0
1
1
0
C3
C2
C1
C0
Bass
0
1
1
1
C3
C2
C1
C0
Terble
0
0
0
0
-14
0
0
0
1
-12
0
0
1
0
-10
0
0
1
1
-8
0
1
0
0
-6
0
1
0
1
-4
0
1
1
0
-2
0
1
1
1
0
1
1
1
1
0
1
1
1
0
2
1
1
0
1
4
1
1
0
0
6
1
0
1
1
8
1
0
1
0
10
1
0
0
1
12
1
0
0
0
14
C3=Sign
For Example, bass at –10dB is obtained by the following 8bit string is: 01100010.
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SC7312
TEST AND TYPICAL APPLICATION CIRCUIT
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SC7312
PACKAGE OUTLINE
SOP-32-375-1.27
UNIT: mm
20.98±0.10
2.54MAX
0.15±0.05
1.27
0.40
0.25±0.05
19.05
HANDLING MOS DEVICES:
Electrostatic charges can exist in many things. All of our MOS devices are internally protected against
electrostatic discharge but they can be damaged if the following precautions are not taken:
• Persons at a work bench should be earthed via a wrist strap.
• Equipment cases should be earthed.
• All tools used during assembly, including soldering tools and solder baths, must be earthed.
• MOS devices should be packed for dispatch in antistatic/conductive containers.
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