Sitronix ST7575 66 x 102 Dot Matrix LCD Controller/Driver 1. INTRODUCTION ST7575 is a driver & controller LSI for graphic dot-matrix liquid crystal display systems. It contains 102-segment and 65-common with 1-icon-common driver circuits. This chip is connected directly to a microprocessor which accepts 3-line or 4-line serial peripheral interface (SPI) or 8-bit parallel interface. Display data stores in an on-chip display data RAM (DDRAM) of 66 x 102 bits. It performs display data RAM read/write operation with no external operating clock to minimize power consumption. In addition, because it contains power supply circuits to drive liquid crystal, it is possible to make a display system with the fewest components. 2. FEATURES Single-chip LCD Controller & Driver Low Power Consumption Analog Circuit Driver Output Circuits - Voltage booster (X4, X5) 102-segment / 65-common+1-icon-common (1/66 duty) - Voltage regulator generates LCD operating voltage On-chip Display Data Ram - (Temperature Gradient: -0.11%/°C) Capacity: 66X102= 6,732 bits Microprocessor Interface - - 8-bit parallel bi-directional interface - Electronic contrast control (128 steps) - Voltage follower generates LCD bias voltages supports (1/4 ~ 1/11 bias) 6800-series or 8080-series MPU Wide supply voltage range 3-line & 4-line SPI (serial peripheral interface) are - VDD1 – VSS1 : 1.8 ~ 3.3V available (write only) - VDD2 – VSS2 : 2.4 ~ 3.3V External RESB (reset) pin Display supply voltage range Built-in oscillation circuit - Application Vop range : 8V ~ 9.5V - - Programmable voltage (Vop) : 10.56V (max) Oscillator requires no external component ° Temperature range: -30 to +85 C Support LCD Module Size up to 1.8” ST7575 6800 , 8080 , 4-Line , 3-Line interface Sitronix Technology Corp. reserves the right to change the contents in this document without prior notice. Ver 1.3 1/51 2007/09/12 ST7575 3-1. ST7575 Pad Arrangement Chip Size: 5570 um ×770 um Bump Height: 15 um Chip Thickness: 480 um Bump Pitch: (minimum) PAD Number Unit: um Pitch PAD Number Pitch 1~27, 130~156, 157~163, 243~250 37.20 212~213 46.65 28~129 33.00 213~216,218~221 33.30 27~28 62.90 216~217,217~218 38.80 129~130 60.69 221~222 46.30 163~164 329.57 228~229 66.40 164~207, 208~211,222~228,229~235,236~242 59.30 235~236 62.45 207~208 131.83 242~243 79.90 211~212 71.30 * Refer to “Pad Center Coordinates” section for ITO layout. Fig 1. Ver 1.3 2/51 2007/09/12 ST7575 3-2. Pad Center Coordinates 66 Duty (TMY=0) PAD NO. PIN Name X Y 1 COM[59] 2695.50 293.00 2 COM[58] 2658.30 293.00 3 COM[57] 2621.10 293.00 4 COM[56] 2583.90 293.00 5 COM[55] 2546.70 293.00 6 COM[54] 2509.50 293.00 7 COM[53] 2472.30 293.00 8 COM[52] 2435.10 293.00 9 COM[51] 2397.90 293.00 10 COM[50] 2360.70 293.00 11 COM[49] 2323.50 293.00 12 COM[48] 2286.30 293.00 13 COM[47] 2249.10 293.00 14 COM[46] 2211.90 293.00 15 COM[45] 2174.70 293.00 16 COM[44] 2137.50 293.00 17 COM[43] 2100.30 293.00 18 COM[42] 2063.10 293.00 19 COM[41] 2025.90 293.00 20 COM[40] 1988.70 293.00 21 COM[39] 1951.50 293.00 22 COM[38] 1914.30 293.00 23 COM[37] 1877.10 293.00 24 COM[36] 1839.90 293.00 25 COM[35] 1802.70 293.00 26 COM[34] 1765.50 293.00 27 COM[33] 1728.30 293.00 28 SEG[0] 1665.39 282.75 29 SEG[1] 1632.39 282.75 30 SEG[2] 1599.39 282.75 Fig 2. MX=0, MY=0 Ver 1.3 3/51 2007/09/12 ST7575 PAD NO. PIN Name X Y PAD NO. PIN Name X Y 31 SEG[3] 1566.39 282.75 61 SEG[33] 576.39 282.75 32 SEG[4] 1533.39 282.75 62 SEG[34] 543.39 282.75 33 SEG[5] 1500.39 282.75 63 SEG[35] 510.39 282.75 34 SEG[6] 1467.39 282.75 64 SEG[36] 477.39 282.75 35 SEG[7] 1434.39 282.75 65 SEG[37] 444.39 282.75 36 SEG[8] 1401.39 282.75 66 SEG[38] 411.39 282.75 37 SEG[9] 1368.39 282.75 67 SEG[39] 378.39 282.75 38 SEG[10] 1335.39 282.75 68 SEG[40] 345.39 282.75 39 SEG[11] 1302.39 282.75 69 SEG[41] 312.39 282.75 40 SEG[12] 1269.39 282.75 70 SEG[42] 279.39 282.75 41 SEG[13] 1236.39 282.75 71 SEG[43] 246.39 282.75 42 SEG[14] 1203.39 282.75 72 SEG[44] 213.39 282.75 43 SEG[15] 1170.39 282.75 73 SEG[45] 180.39 282.75 44 SEG[16] 1137.39 282.75 74 SEG[46] 147.39 282.75 45 SEG[17] 1104.39 282.75 75 SEG[47] 114.39 282.75 46 SEG[18] 1071.39 282.75 76 SEG[48] 81.39 282.75 47 SEG[19] 1038.39 282.75 77 SEG[49] 48.39 282.75 48 SEG[20] 1005.39 282.75 78 SEG[50] 15.39 282.75 49 SEG[21] 972.39 282.75 79 SEG[51] -17.60 282.75 50 SEG[22] 939.39 282.75 80 SEG[52] -50.60 282.75 51 SEG[23] 906.39 282.75 81 SEG[53] -83.60 282.75 52 SEG[24] 873.39 282.75 82 SEG[54] -116.60 282.75 53 SEG[25] 840.39 282.75 83 SEG[55] -149.60 282.75 54 SEG[26] 807.39 282.75 84 SEG[56] -182.60 282.75 55 SEG[27] 774.39 282.75 85 SEG[57] -215.60 282.75 56 SEG[28] 741.39 282.75 86 SEG[58] -248.60 282.75 57 SEG[29] 708.39 282.75 87 SEG[59] -281.60 282.75 58 SEG[30] 675.39 282.75 88 SEG[60] -314.60 282.75 59 SEG[31] 642.39 282.75 89 SEG[61] -347.60 282.75 60 SEG[32] 609.39 282.75 90 SEG[62] -380.60 282.75 Ver 1.3 4/51 2007/09/12 ST7575 PAD NO. PIN Name X Y PAD NO. PIN Name X Y 91 SEG[63] -413.60 282.75 121 SEG[93] -1403.60 282.75 92 SEG[64] -446.60 282.75 122 SEG[94] -1436.60 282.75 93 SEG[65] -479.60 282.75 123 SEG[95] -1469.60 282.75 94 SEG[66] -512.60 282.75 124 SEG[96] -1502.60 282.75 95 SEG[67] -545.60 282.75 125 SEG[97] -1535.60 282.75 96 SEG[68] -578.60 282.75 126 SEG[98] -1568.60 282.75 97 SEG[69] -611.60 282.75 127 SEG[99] -1601.60 282.75 98 SEG[70] -644.60 282.75 128 SEG[100] -1634.60 282.75 99 SEG[71] -677.60 282.75 129 SEG[101] -1667.60 282.75 100 SEG[72] -710.60 282.75 130 COMS1 -1728.30 293.00 101 SEG[73] -743.60 282.75 131 COM[0] -1765.50 293.00 102 SEG[74] -776.60 282.75 132 COM[1] -1802.70 293.00 103 SEG[75] -809.60 282.75 133 COM[2] -1839.90 293.00 104 SEG[76] -842.60 282.75 134 COM[3] -1877.10 293.00 105 SEG[77] -875.60 282.75 135 COM[4] -1914.30 293.00 106 SEG[78] -908.60 282.75 136 COM[5] -1951.50 293.00 107 SEG[79] -941.60 282.75 137 COM[6] -1988.70 293.00 108 SEG[80] -974.60 282.75 138 COM[7] -2025.90 293.00 109 SEG[81] -1007.60 282.75 139 COM[8] -2063.10 293.00 110 SEG[82] -1040.60 282.75 140 COM[9] -2100.30 293.00 111 SEG[83] -1073.60 282.75 141 COM[10] -2137.50 293.00 112 SEG[84] -1106.60 282.75 142 COM[11] -2174.70 293.00 113 SEG[85] -1139.60 282.75 143 COM[12] -2211.90 293.00 114 SEG[86] -1172.60 282.75 144 COM[13] -2249.10 293.00 115 SEG[87] -1205.60 282.75 145 COM[14] -2286.30 293.00 116 SEG[88] -1238.60 282.75 146 COM[15] -2323.50 293.00 117 SEG[89] -1271.60 282.75 147 COM[16] -2360.70 293.00 118 SEG[90] -1304.60 282.75 148 COM[17] -2397.90 293.00 119 SEG[91] -1337.60 282.75 149 COM[18] -2435.10 293.00 120 SEG[92] -1370.60 282.75 150 COM[19] -2472.30 293.00 Ver 1.3 5/51 2007/09/12 ST7575 PAD NO. PIN Name X Y PAD NO. PIN Name X Y 151 COM[20] -2509.50 293.00 181 VDD1 -1134.54 -311.50 152 COM[21] -2546.70 293.00 182 VDD1 -1075.23 -311.50 153 COM[22] -2583.90 293.00 183 VDD1 -1015.92 -311.50 154 COM[23] -2621.10 293.00 184 VDD1 -956.62 -311.50 155 COM[24] -2658.30 293.00 185 VDD2 -897.32 -311.50 156 COM[25] -2695.50 293.00 186 VDD2 -838.01 -311.50 157 COM[32] -2695.50 -293.00 187 VDD2 -778.70 -311.50 158 COM[31] -2658.30 -293.00 188 VDD2 -719.40 -311.50 159 COM[30] -2621.10 -293.00 189 RESB -660.09 -311.50 160 COM[29] -2583.90 -293.00 190 CSB -600.79 -311.50 161 COM[28] -2546.70 -293.00 191 RWR -541.48 -311.50 162 COM[27] -2509.50 -293.00 192 ERD -482.18 -311.50 163 COM[26] -2472.30 -293.00 193 A0 -422.88 -311.50 164 VDX2O -2142.72 -311.50 194 VDD1 -363.57 -311.50 165 VDX2O -2083.42 -311.50 195 D7 -304.27 -311.50 166 VDX2O -2024.11 -311.50 196 D6 -244.96 -311.50 167 VSS1 -1964.81 -311.50 197 D5 -185.66 -311.50 168 T11 -1905.50 -311.50 198 D4 -126.35 -311.50 169 T12 -1846.19 -311.50 199 D3 -67.05 -311.50 170 BR -1786.89 -311.50 200 D2 -7.74 -311.50 171 CP -1727.58 -311.50 201 D1 51.56 -311.50 172 TMX -1668.28 -311.50 202 D0 110.87 -311.50 173 TMY -1608.97 -311.50 203 OSC 170.17 -311.50 174 PS2 -1549.67 -311.50 204 VSS2 229.47 -311.50 175 PS1 -1490.36 -311.50 205 VSS2 288.78 -311.50 176 PS0 -1431.06 -311.50 206 VSS2 348.09 -311.50 177 VMO -1371.75 -311.50 207 VSS2 407.39 -311.50 178 VMO -1312.45 -311.50 208 VSS1 539.23 -311.50 179 VMO -1253.14 -311.50 209 VSS1 598.53 -311.50 180 VSS1 -1193.84 -311.50 210 VSS1 657.84 -311.50 Ver 1.3 6/51 2007/09/12 ST7575 PAD NO. PIN Name X Y PAD NO. PIN Name X Y 211 VSS1 717.15 -311.50 241 XV0I 2295.89 -311.50 212 VRS 786.52 -311.50 242 XV0S 2355.20 -311.50 213 T1 835.10 -307.75 243 COMS2 2435.10 -293.00 214 T2 868.40 -307.75 244 COM[60] 2472.30 -293.00 215 T3 901.70 -307.75 245 COM[61] 2509.50 -293.00 216 T4 935.00 -307.75 246 COM[62] 2546.70 -293.00 217 T0 973.80 -307.75 247 COM[63] 2583.90 -293.00 218 T5 1012.60 -307.75 248 COM[64] 2621.10 -293.00 219 T6 1045.90 -307.75 249 Reserved 2658.30 -293.00 220 T7 1079.20 -307.75 250 Reserved 2695.50 -293.00 221 T8 1112.50 -307.75 222 VGO 1158.81 -311.50 223 VGO 1218.11 -311.50 224 VGI 1277.42 -311.50 225 VGI 1336.72 -311.50 226 VGI 1396.03 -311.50 227 VGI 1455.33 -311.50 228 VGS 1514.64 -311.50 229 V0O 1581.08 -309.75 230 V0O 1640.38 -309.75 231 V0I 1699.69 -309.75 232 V0I 1759.00 -309.75 233 V0I 1818.30 -309.75 234 V0I 1877.60 -311.50 235 V0S 1936.91 -311.50 236 XV0O 1999.36 -311.50 237 XV0O 2058.67 -311.50 238 XV0I 2117.98 -311.50 239 XV0I 2177.28 -311.50 240 XV0I 2236.58 -311.50 Ver 1.3 7/51 2007/09/12 ST7575 66 Duty (TMY=1) PAD NO. PIN Name X Y PAD NO. PIN Name X Y 1 COM[5] 2695.50 293.00 31 SEG[3] 1566.39 282.75 2 COM[6] 2658.30 293.00 32 SEG[4] 1533.39 282.75 3 COM[7] 2621.10 293.00 33 SEG[5] 1500.39 282.75 4 COM[8] 2583.90 293.00 34 SEG[6] 1467.39 282.75 5 COM[9] 2546.70 293.00 35 SEG[7] 1434.39 282.75 6 COM[10] 2509.50 293.00 36 SEG[8] 1401.39 282.75 7 COM[11] 2472.30 293.00 37 SEG[9] 1368.39 282.75 8 COM[12] 2435.10 293.00 38 SEG[10] 1335.39 282.75 9 COM[13] 2397.90 293.00 39 SEG[11] 1302.39 282.75 10 COM[14] 2360.70 293.00 40 SEG[12] 1269.39 282.75 11 COM[15] 2323.50 293.00 41 SEG[13] 1236.39 282.75 12 COM[16] 2286.30 293.00 42 SEG[14] 1203.39 282.75 13 COM[17] 2249.10 293.00 43 SEG[15] 1170.39 282.75 14 COM[18] 2211.90 293.00 44 SEG[16] 1137.39 282.75 15 COM[19] 2174.70 293.00 45 SEG[17] 1104.39 282.75 16 COM[20] 2137.50 293.00 46 SEG[18] 1071.39 282.75 17 COM[21] 2100.30 293.00 47 SEG[19] 1038.39 282.75 18 COM[22] 2063.10 293.00 48 SEG[20] 1005.39 282.75 19 COM[23] 2025.90 293.00 49 SEG[21] 972.39 282.75 20 COM[24] 1988.70 293.00 50 SEG[22] 939.39 282.75 21 COM[25] 1951.50 293.00 51 SEG[23] 906.39 282.75 22 COM[26] 1914.30 293.00 52 SEG[24] 873.39 282.75 23 COM[27] 1877.10 293.00 53 SEG[25] 840.39 282.75 24 COM[28] 1839.90 293.00 54 SEG[26] 807.39 282.75 25 COM[29] 1802.70 293.00 55 SEG[27] 774.39 282.75 26 COM[30] 1765.50 293.00 56 SEG[28] 741.39 282.75 27 COM[31] 1728.30 293.00 57 SEG[29] 708.39 282.75 28 SEG[0] 1665.39 282.75 58 SEG[30] 675.39 282.75 29 SEG[1] 1632.39 282.75 59 SEG[31] 642.39 282.75 30 SEG[2] 1599.39 282.75 60 SEG[32] 609.39 282.75 Ver 1.3 8/51 2007/09/12 ST7575 PAD NO. PIN Name X Y PAD NO. PIN Name X Y 61 SEG[33] 576.39 282.75 91 SEG[63] -413.60 282.75 62 SEG[34] 543.39 282.75 92 SEG[64] -446.60 282.75 63 SEG[35] 510.39 282.75 93 SEG[65] -479.60 282.75 64 SEG[36] 477.39 282.75 94 SEG[66] -512.60 282.75 65 SEG[37] 444.39 282.75 95 SEG[67] -545.60 282.75 66 SEG[38] 411.39 282.75 96 SEG[68] -578.60 282.75 67 SEG[39] 378.39 282.75 97 SEG[69] -611.60 282.75 68 SEG[40] 345.39 282.75 98 SEG[70] -644.60 282.75 69 SEG[41] 312.39 282.75 99 SEG[71] -677.60 282.75 70 SEG[42] 279.39 282.75 100 SEG[72] -710.60 282.75 71 SEG[43] 246.39 282.75 101 SEG[73] -743.60 282.75 72 SEG[44] 213.39 282.75 102 SEG[74] -776.60 282.75 73 SEG[45] 180.39 282.75 103 SEG[75] -809.60 282.75 74 SEG[46] 147.39 282.75 104 SEG[76] -842.60 282.75 75 SEG[47] 114.39 282.75 105 SEG[77] -875.60 282.75 76 SEG[48] 81.39 282.75 106 SEG[78] -908.60 282.75 77 SEG[49] 48.39 282.75 107 SEG[79] -941.60 282.75 78 SEG[50] 15.39 282.75 108 SEG[80] -974.60 282.75 79 SEG[51] -17.60 282.75 109 SEG[81] -1007.60 282.75 80 SEG[52] -50.60 282.75 110 SEG[82] -1040.60 282.75 81 SEG[53] -83.60 282.75 111 SEG[83] -1073.60 282.75 82 SEG[54] -116.60 282.75 112 SEG[84] -1106.60 282.75 83 SEG[55] -149.60 282.75 113 SEG[85] -1139.60 282.75 84 SEG[56] -182.60 282.75 114 SEG[86] -1172.60 282.75 85 SEG[57] -215.60 282.75 115 SEG[87] -1205.60 282.75 86 SEG[58] -248.60 282.75 116 SEG[88] -1238.60 282.75 87 SEG[59] -281.60 282.75 117 SEG[89] -1271.60 282.75 88 SEG[60] -314.60 282.75 118 SEG[90] -1304.60 282.75 89 SEG[61] -347.60 282.75 119 SEG[91] -1337.60 282.75 90 SEG[62] -380.60 282.75 120 SEG[92] -1370.60 282.75 Ver 1.3 9/51 2007/09/12 ST7575 PAD NO. PIN Name X Y PAD NO. PIN Name X Y 121 SEG[93] -1403.60 282.75 151 COM[44] -2509.50 293.00 122 SEG[94] -1436.60 282.75 152 COM[43] -2546.70 293.00 123 SEG[95] -1469.60 282.75 153 COM[42] -2583.90 293.00 124 SEG[96] -1502.60 282.75 154 COM[41] -2621.10 293.00 125 SEG[97] -1535.60 282.75 155 COM[40] -2658.30 293.00 126 SEG[98] -1568.60 282.75 156 COM[39] -2695.50 293.00 127 SEG[99] -1601.60 282.75 157 COM[32] -2695.50 -293.00 128 SEG[100] -1634.60 282.75 158 COM[33] -2658.30 -293.00 129 SEG[101] -1667.60 282.75 159 COM[34] -2621.10 -293.00 130 COMS1 -1728.30 293.00 160 COM[35] -2583.90 -293.00 131 COM[64] -1765.50 293.00 161 COM[36] -2546.70 -293.00 132 COM[63] -1802.70 293.00 162 COM[37] -2509.50 -293.00 133 COM[62] -1839.90 293.00 163 COM[38] -2472.30 -293.00 134 COM[61] -1877.10 293.00 164 VDX2O -2142.72 -311.50 135 COM[660 -1914.30 293.00 165 VDX2O -2083.42 -311.50 136 COM[59] -1951.50 293.00 166 VDX2O -2024.11 -311.50 137 COM[58] -1988.70 293.00 167 VSS1 -1964.81 -311.50 138 COM[57] -2025.90 293.00 168 T11 -1905.50 -311.50 139 COM[56] -2063.10 293.00 169 T12 -1846.19 -311.50 140 COM[55] -2100.30 293.00 170 BR -1786.89 -311.50 141 COM[54] -2137.50 293.00 171 CP -1727.58 -311.50 142 COM[53] -2174.70 293.00 172 TMX -1668.28 -311.50 143 COM[52] -2211.90 293.00 173 TMY -1608.97 -311.50 144 COM[51] -2249.10 293.00 174 PS2 -1549.67 -311.50 145 COM[50] -2286.30 293.00 175 PS1 -1490.36 -311.50 146 COM[49] -2323.50 293.00 176 PS0 -1431.06 -311.50 147 COM[48] -2360.70 293.00 177 VMO -1371.75 -311.50 148 COM[47] -2397.90 293.00 178 VMO -1312.45 -311.50 149 COM[46] -2435.10 293.00 179 VMO -1253.14 -311.50 150 COM[45] -2472.30 293.00 180 VSS1 -1193.84 -311.50 Ver 1.3 10/51 2007/09/12 ST7575 PAD NO. PIN Name X Y PAD NO. PIN Name X Y 181 VDD1 -1134.54 -311.50 211 VSS1 717.15 -311.50 182 VDD1 -1075.23 -311.50 212 VRS 786.52 -311.50 183 VDD1 -1015.92 -311.50 213 T1 835.10 -307.75 184 VDD1 -956.62 -311.50 214 T2 868.40 -307.75 185 VDD2 -897.32 -311.50 215 T3 901.70 -307.75 186 VDD2 -838.01 -311.50 216 T4 935.00 -307.75 187 VDD2 -778.70 -311.50 217 T0 973.80 -307.75 188 VDD2 -719.40 -311.50 218 T5 1012.60 -307.75 189 RESB -660.09 -311.50 219 T6 1045.90 -307.75 190 CSB -600.79 -311.50 220 T7 1079.20 -307.75 191 RWR -541.48 -311.50 221 T8 1112.50 -307.75 192 ERD -482.18 -311.50 222 VGO 1158.81 -311.50 193 A0 -422.88 -311.50 223 VGO 1218.11 -311.50 194 VDD1 -363.57 -311.50 224 VGI 1277.42 -311.50 195 D7 -304.27 -311.50 225 VGI 1336.72 -311.50 196 D6 -244.96 -311.50 226 VGI 1396.03 -311.50 197 D5 -185.66 -311.50 227 VGI 1455.33 -311.50 198 D4 -126.35 -311.50 228 VGS 1514.64 -311.50 199 D3 -67.05 -311.50 229 V0O 1581.08 -309.75 200 D2 -7.74 -311.50 230 V0O 1640.38 -309.75 201 D1 51.56 -311.50 231 V0I 1699.69 -309.75 202 D0 110.87 -311.50 232 V0I 1759.00 -309.75 203 OSC 170.17 -311.50 233 V0I 1818.30 -309.75 204 VSS2 229.47 -311.50 234 V0I 1877.60 -311.50 205 VSS2 288.78 -311.50 235 V0S 1936.91 -311.50 206 VSS2 348.09 -311.50 236 XV0O 1999.36 -311.50 207 VSS2 407.39 -311.50 237 XV0O 2058.67 -311.50 208 VSS1 539.23 -311.50 238 XV0I 2117.98 -311.50 209 VSS1 598.53 -311.50 239 XV0I 2177.28 -311.50 210 VSS1 657.84 -311.50 240 XV0I 2236.58 -311.50 Ver 1.3 11/51 2007/09/12 ST7575 PAD NO. PIN Name X Y 241 XV0I 2295.89 -311.50 242 XV0S 2355.20 -311.50 243 COMS2 2435.10 -293.00 244 COM[4] 2472.30 -293.00 245 COM[3] 2509.50 -293.00 246 COM[2] 2546.70 -293.00 247 COM[1] 2583.90 -293.00 248 COM[0] 2621.10 -293.00 249 Reserved 2658.30 -293.00 250 Reserved 2695.50 -293.00 Ver 1.3 12/51 2007/09/12 ST7575 4. BLOCK DIAGRAM Fig 3. Ver 1.3 Block Diagram 13/51 2007/09/12 ST7575 5. PINNING DESCRIPTIONS LCD Driver Output Pins Pin Name Type Description No. of Pins LCD segment driver outputs. The display data and the frame control the output voltage. SEG0 to SEG101 Display data Frame H O Segment driver output voltage Normal display Reverse display + VG VSS H - VSS VG L + VSS VG L - VG VSS VSS VSS Display OFF, Power Save 102 LCD common driver outputs. The internal scanning signal and the frame control the output voltage. COM0 to COM64 Common driver output voltage Scan signal Frame H + XV0 H - V0 L + VM L - VM O Normal display Display OFF, Power Save COMS1,COMS2 (COMS) Reverse display 65 VSS LCD common driver outputs for icons. O The output signals of these two pins are the same. 2 When icon feature is not used, these pins should be left open. Microprocessor Interface Pins Pin Name Type Description No. of Pins Microprocessor interface select pins. PS[2:0] I PS2 PS1 PS0 Selected Interface “L” “L” “L” 4 Pin-SPI MPU interface “H” “L” “L” 3 Pin-SPI MPU interface “L” “H” “L” 8080-series parallel MPU interface “H” “H” “L” 6800-series parallel MPU interface 3 Chip select input pin. CSB I Interface access is enabled when CSB is “L”. When CSB is non-active (CSB=“H”), D[7:0] pins are high impedance. 1 CSB is not used in serial interfaces and should fix to “H” by VDD1. RESB I Reset input pin. When RESB is “L”, internal initialization is executed. 1 It determines whether the access is related to data or command. A0 I A0=“H” : Indicates that D[7:0] are display data. A0=“L” : Indicates that D[7:0] are control data. 1 A0 is not used in serial interfaces and should fix to “H” by VDD1. Ver 1.3 14/51 2007/09/12 ST7575 Pin Name Type Description No. of Pins Read/Write execution control pin. When PS[1:0]=(H,L), PS2 H RWR I L MPU Type 6800 series 8080 series RWR Description Read/Write control input pin. R/W R/W=“H”: read. R/W=“L”: write. 1 Write enable input pin. /WR Signals on D[7:0] will be latched at the rising edge of /WR signal. RWR is not used in serial interfaces and should fix to “H” by VDD1. Read/Write execution control pin. When PS[1:0]=(H,L), PS2 MPU Type ERD Description Read/Write control input pin. ERD I H 6800 series R/W=”H“: When E is “H”, D[7:0] are in an E output status. R/W=”L“: Signals on D[7:0] are latched at the 1 falling edge of E signal. L 8080 series /RD Read enable input pin. When /RD is “L”, D[7:0] are in output status. ERD is not used in serial interfaces and should fix to “H” by VDD1. When using 8-bit parallel interface: 6800 or 8080 mode I/O 8-bit bi-directional data bus. Connect to the data bus of 8-bit microprocessor. When CSB is non-active (CSB=“H”), D[7:0] pins are high impedance. When using serial interface: 4-LINE or 3-LINE D[7:0] 8 D7=SCLK : Serial clock input. I D6=SDA : Serial data input. D5=A0 : Command / Data selection (unused in 3-Line SPI; fix to H by VDD1). D4=CSB : Chip select pin. D[3:0] : Not used and should fix to “H” by VDD1. Note: 1. After VDD1 is turned ON, any MPU interface pins cannot be left floating. Clock System Input Pin Name Type Description No. of Pins OSC=“H” : On-chip oscillator is used. Connect to VDD1 to set OSC=“H”. OSC=External clock : Use external clock. Connect external clock to this pin. OSC=“L” : Stop system clock. The whole circuit is stopped except the logical OSC I and DDRAM circuits. It is not recommended to stop the system clock. When system clock is stopped, 1 the driver outputs (SEGx & COMx) will be hold at the last state (like DC output) and the liquid crystal maybe polarized. To avoid this, never stop system clock before entering Power Down Mode. Ver 1.3 15/51 2007/09/12 ST7575 Power System Pins Pin Name Type Description VSS1 Power VSS2 Power Analog ground. Connect to VSS1 externally. 6 VDX2O Power Power for test mode. Left this pin floating. 3 VDD1 Power VDD2 Power Digital ground. Connect to VSS2 externally. For pins that are set to be “L”, connect them to this power (use VSS1 for “L”). Digital power. If VDD1=VDD2, connect to VDD2 externally. For pins that are set to be “H”, connect them to this power (use VDD1 for “H”). Analog power. If VDD1=VDD2, connect to VDD1 externally. No. of Pins 4 5 4 LCD driving voltage for commons at negative frame. V0 (V0O, V0I, V0S) Power V0 ≥ VG > VM > VSS ≥ XV0 V0O, V0I & V0S should be separated in ITO layout. 7 V0O, V0I & V0S should be connected together in FPC layout. XV0 (XV0O, XV0I, LCD driving voltage for commons at positive frame. Power XV0S) XV0O, XV0I & XV0S should be separated in ITO layout. 7 XV0O, XV0I & XV0S should be connected together in FPC layout. LCD driving voltage for segments. VG (VGO, VGI, VGS) Power VGO, VGI & VGS should be separated in ITO layout. VGO, VGI & VGS should be connected together in FPC layout. 7 1.24 ≤ VG < VDD2. VMO Power VRS Power CP I VM output. LCD driving voltage for commons. 0.62V ≤ VM < VDD2. Test pin for monitoring voltage reference level. This pin must be left open (without any kinds of connection). Booster configuration pin for default setting : “L”=4X; “H”=5X. This pin set the default booster stage after reset. 4 1 1 Bias circuit configuration pin for default setting : “L”=1/7; “H”=1/9. BR I This pin set the default value of bias ratio after reset. 1 The bias ratio can be changed by software instruction. Configuration Pins Pin Name Type Description No. of Pins Select SEG output direction. TMX I TMX=“L” : Normal direction (SEG0 ~ SEG101). 1 TMX=“H” : Reverse direction (SEG101 ~ SEG0). Select COM output direction. TMY I TMY=“L” : Normal direction. TMY=“H” : Reverse direction. 1 Refer to “PAD Center Coordinates”. Ver 1.3 16/51 2007/09/12 ST7575 Test Pins Pin Name Type T0~T8 T T11 T T12 T Description No. of Pins Do NOT use. Reserved for testing. 9 Must be floating. Do NOT use. Reserved for testing. 1 Must be “L”. Connect to VSS1 for pull-low. Do NOT use. Reserved for testing. 1 Must be “L”. Connect to VSS1 for pull-low. Recommend ITO Resistance Pin Name ITO Resistance T[0:8], VRS, VDX2O Floating VDD1, VDD2, VSS1, VSS2 < 100Ω V0(V0I, V0O, V0S), VG(VGI, VGO, VGS), XV0(XV0I, XV0O, XV0S), VMO A0, RWR, ERD, CSB, D[7:0] *1 < 1KΩ *2 PS[2:0], OSC , CP, BR, TMX, TMY, T11, T12 RESB < 300Ω < 5KΩ *3 < 10KΩ Note: 1. If using 3-Line or 4-Line SPI interface with VDD1 less than 2.4V, the SDA signal resistance should be less than 500Ω. 2. If using internal clock, OSC is connect to VDD1 and the limitation of ITO resistance will be “No Limitation”. If using external clock, the ITO resistance of OSC should be kept lower than 300Ω to keep the clock signal quality. 3. To prevent the ESD pulse resetting the internal register, applications should increase the resistance of RESB signal (add a series resistor or increase ITO resistance). The value is different from modules. 4. The option setting to be “H” should connect to VDD1. 5. The option setting to be “L” should connect to VSS1. Ver 1.3 17/51 2007/09/12 ST7575 6. FUNCTIONS DESCRIPTION Microprocessor Interface Chip Select Input CSB pin is used for chip selection. ST7575 can interface with an MPU when CSB is "L". When CSB is “H”, the inputs of A0, ERD and RWR with any combination will be ignored and D[7:0] are high impedance. In 3-Line and 4-Line serial interface, the internal shift register and serial counter are reset when CSB is “H”. Parallel / Serial Interface ST7575 has types of interface for kinds of MPU. The MPU interface is selected by PS[2:0] pins as shown in table 1. Table 1. Parallel/Serial Interface Mode PS2 PS1 PS0 CSB A0 ERD RWR D[7:0] “L” “L” “L” --------Refer to serial interface. “H” “L” “L” “L” “H” “L” /RD /WR CSB A0 D[7:0] “H” “H” “L” E R/W * The un-used pins are marked as “---” and should be fixed to “H” by VDD1. MPU Interface 4-Line SPI interface 3-Line SPI interface 8080-series parallel interface 6800-series parallel interface Parallel Interface The 8-bit bi-directional data bus is used in parallel interface and the type of MPU is selected by PS2 (fix PS1=H, PS0=L) as shown in table 2. The data transfer type is determined by signals of A0, ERD and RWR as shown in table 3. Table 2. Microprocessor Selection for Parallel Interface PS2 “L” “H” PS1 “H” “H” PS0 “L” “L” CSB A0 CSB A0 ERD /RD E RWR /WR R/W D[7:0] D[7:0] MPU Interface 8080-series 6800-series Table 3. Parallel Data Transfer Common 6800-series 8080-series Description A0 E (ERD) R/W (RWR) /RD (ERD) /WR (RWR) “H” “H” “H” “L” “H” Display data read out “H” “H” “L” “H” “L” Display data write “L” “H” “H” “L” “H” Internal status read “L” “H” “L” “H” “L” Writes to internal register (instruction) NOTE: In 6800-series interface mode, fixing E (ERD) pin at high can use CSB as enable signal instead. In this case, interface data is latched at the rising edge of CSB and the type of data transfer is determined by signals at A0 and R/W (RWR) pins as defined in 6800-series mode. Setting Serial Interface Serial Mode PS[2:0] CSB A0 ERD RWR D[7:0] 4-Line SPI interface “L, L, L” SCLK, SDA, A0, CSB, ---, ---, ---, ----------3-Line SPI interface “H, L, L” SCLK, SDA, ---, CSB, ---, ---, ---, --* The un-used pins are marked as “---” and should be fixed to “H” by VDD1. Note: 1. The option setting to be “H” should connect to VDD1. 2. The option setting to be “L” should connect to VSS1. Ver 1.3 18/51 2007/09/12 ST7575 PS2= "L", PS1= "L", PS0= "L" : 4-line SPI interface When ST7575 is active (CSB=“L”), serial data (SDA) and serial clock (SCLK) inputs are enabled. When ST7575 is not active (CSB=“H”), the internal 8-bit shift register and 3-bit counter are reset. The display data/command indication is controlled by the register selection pin (A0). The signals transferred on data bus will be display data when A0 is high and will be instruction when A0 is low. The read feature is not supported in this mode. Serial data on SDA is latched at the rising th edge of serial clock on SCLK. After the 8 serial clock, the serial data will be processed as 8-bit parallel data. The DDRAM column address pointer will be increased by one automatically after each byte of DDRAM access. Fig 4. 4-Line SPI Access PS2= "L", PS1= "L", PS0= "H": 3-line SPI interface When ST7575 is active (CSB=“L”), serial data (SDA) and serial clock (SCLK) inputs are enabled. When ST7575 is not active (CSB=“H”), the internal 8-bit shift register and 3-bit counter are reset. The A0 pin is not available in this mode. Before issuing serial data, an A0 bit is required to indicate the following 8-bit signals are data or instruction. The read feature is not th supported in this mode. Serial data on SDA is latched at the rising edge of serial clock on SCLK. After the 9 serial clock, the serial data will be processed as 8-bit parallel data. The DDRAM column address pointer will be increased by one automatically after each byte of DDRAM access. Fig 5. Ver 1.3 3-Line SPI Access 19/51 2007/09/12 ST7575 Data Transfer ST7575 uses bus holder and internal data bus for data transfer with MPU. When writing data from the MPU to on-chip RAM, data is automatically transferred from the bus holder to the RAM as shown in Fig 6. And when reading data from on-chip RAM to the MPU, the data for the initial read cycle is stored in the bus holder (dummy read) and the MPU reads this stored data from bus holder for the next data read cycle as shown in Fig 7. This means that a dummy read cycle must be inserted between each pair of address sets when a sequence of address sets is executed. Therefore, the data of the specified address cannot be output with the read display data instruction right after the address sets, but can be output at the second read of data. MPU signal A0 /WR D0 to D7 N D(N) D(N+1) D(N+2) D(N+3) N D(N) D(N+1) D(N+2) D(N+3) N N+1 N+2 N+3 Internal signals /WR BUS HOLDER COLUMN ADDRESS Fig 6. Data Transfer : Write MPU signal A0 /WR /RD D0 to D7 Dummy N D(N) D(N+1) Internal signals /WR /RD BUS HOLDER N N COLUMN ADDRESS Fig 7. Ver 1.3 D(N) D(N+1) D(N+2) D(N) D(N+1) D(N+2) Data Transfer : Read 20/51 2007/09/12 ST7575 Display Data RAM (DDRAM) ST7575 contains a 66X102 bit static RAM that stores the display data. The display data RAM (DDRAM) store the dot data for the LCD. It is an addressable array with 102 columns by 66 rows (8-page with 8-bit, 1-page with 1-bit and 1-page with 1-bit). The X-address is directly related to the column output number. Each pixel can be selected when the page and column addresses are specified. The rows are divided into: 8 pages (page 0~7) each with 8 lines (for COM0~63), the 8 th th page with only 1 line (for COM64) and the 9 page with only 1 line (the 65th row, COMS, for icon). The display data (D7~D0) corresponds to the LCD common-line direction (D7 at top). Those pages with 8 lines can be accessed through D[7:0] directly. When accessing those pages with fewer than 8 lines, the valid bit(s) in D[7:0] should be checked. Refer to Fig 9 for detailed illustration. The microprocessor can write to and read from (only Parallel interfaces) DDRAM by the I/O buffer. Since the LCD controller operates independently, data can be written into DDRAM at the same time as data is being displayed without causing the LCD flicker or data-conflict. Page Address Circuit This circuit is for providing a Page Address to Display Data RAM. It incorporates 4-bit Page Address register changed by only the “Set Page” instruction. Page Address 9 is a special RAM area for the icons and display data is only 1-bit valid (D7). Line Address Circuit This circuit controls each line in DDRAM to transfer 102-bit line data to the display data latch circuit. Therefore, the content in DDRAM can be transferred to the segment outputs and the content can be displayed on the LCD module as shown in Fig 12. At the beginning of each LCD frame, the 102-bit RAM data of Line-0 are transferred to the display data latch circuit. At the next line period, the Line Address is increased by one and the 102-bit RAM data at the next line are transferred to the display data latch circuit. The 102-bit icon data are transferred at the last line period during each frame. Ver 1.3 21/51 2007/09/12 ST7575 Column Address Circuit Column Address Circuit has an 8-bit preset counter that provides Column Address to the DDRAM. The display data RAM column address is specified by the Column Address Set command. The specified column address is incremented (+1) with each display data read/write command. This allows the MPU display data to be accessed continuously. TMX and TMY make it possible to invert the relationship between the addresses (Line Address and Column Address) and the outputs (COM/SEG). It is necessary to rewrite the display data into built-in RAM after changing TMX setting. The relation between DDRAM and outputs with different TMX or TMY setting is shown below. 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Data D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 TMX=0 5D 5E 5F 60 61 62 63 64 65 D0 TMX=1 08 07 06 05 04 03 02 01 00 D1 B B B B B B B Page 0 B B B B B B B B B B B B B B Page 1 B B B B B B B B B B B B B B B B B B B B B B B B B B B B B Page 2 Page 3 B B B B B B B B B B B B B Page 4 B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B Page 6 B B B B B B B B Page 5 Page 7 B B B COM Output Map PAD No. 1/66 Duty TMY=0 TMY=1 (COM) COM0 COM64 131 COM1 COM63 132 COM2 COM62 133 COM3 COM61 134 COM4 COM60 135 COM5 COM59 136 COM6 COM58 137 COM7 COM57 138 COM8 COM56 139 COM9 COM55 140 COM10 COM54 141 COM11 COM53 142 COM12 COM52 143 COM13 COM51 144 COM14 COM50 145 COM15 COM49 146 COM16 COM48 147 COM17 COM47 148 COM18 COM46 149 COM19 COM45 150 COM20 COM44 151 COM21 COM43 152 COM22 COM42 153 COM23 COM41 154 COM24 COM40 155 COM25 COM39 156 COM26 COM38 163 COM27 COM37 162 COM28 COM36 161 COM29 COM35 160 COM30 COM34 159 COM31 COM33 158 COM32 COM32 157 COM33 COM31 27 COM34 COM30 26 COM35 COM29 25 COM36 COM28 24 COM37 COM27 23 COM38 COM26 22 COM39 COM25 21 COM40 COM24 20 COM41 COM23 19 COM42 COM22 18 COM43 COM21 17 COM44 COM20 16 COM45 COM19 15 COM46 COM18 14 COM47 COM17 13 COM48 COM16 12 COM49 COM15 11 COM50 COM14 10 COM51 COM13 9 COM52 COM12 8 COM53 COM11 7 COM54 COM10 6 COM55 COM9 5 COM56 COM8 4 COM57 COM7 3 COM58 COM6 2 COM59 COM5 1 COM60 COM4 244 COM61 COM3 245 COM62 COM2 246 COM63 COM1 247 0 0 D7 Page 8 40H COM64 0 0 1 D7 Page 9 41H ICON 130, 243 (COMS1, COMS2) 121 122 123 124 125 126 127 128 129 0 1 28 29 30 31 32 33 34 35 36 1 Fig 8. Ver 1.3 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH B B B B B Line Address (Hex) 0 D2 00 01 02 03 04 05 06 07 08 Page Address D3 65 64 63 62 61 60 5F 5E 5D Column Address (Hex) COM0 248 PAD No. (SEG) Relationship between DDRAM and Outputs (COM/SEG) 22/51 2007/09/12 ST7575 Addressing Data is downloaded in bytes into the Display Data RAM matrix of ST7575 as shown below. The Display Data RAM has a matrix of 66 by 102 bits. The address pointer addresses the columns. The address ranges are: X 0 to 101 (1100101), Y 0 to 9 (1001) .Addresses outside these ranges are not allowed. In horizontal addressing mode the X address increments after each byte (see Fig 11). After the last X address (X = 101), X wraps around to 0 and Y increments to address the next row. After the very last address (X = 101, Y = 8) the address pointers wrap around to address (X = 0, Y =0) Data Structure Fig 9. Fig 10. Ver 1.3 RAM format Addressing : Vertical Mode (V=1) Fig 11. 23/51 Addressing : Horizontal Mode (V=0) 2007/09/12 ST7575 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Data D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 5D 5E 5F 60 61 62 63 64 65 D0 TMX=1 B B B B B B Page 0 B B B B B B B B B B B B B B B B B Page 1 B B B B B B B B B B B Page 2 B B B B B B B B B B B B B B B B B B Page 3 B B B B B B B B B B B B B Page 4 B B B B B B B B B B B B B B B B B B B B B B Page 5 B B B B B B B B B B B B B Page 6 B B B B B B B B Page 7 B B B TMY=0 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 0 D7 Page 8 40H COM64 1 0 0 1 D7 Page 9 41H ICON (COMS) S0 S1 S2 S3 S4 S5 S6 S7 S8 121 122 123 124 125 126 127 128 129 0 PAD No. S93 S94 S95 S96 S97 S98 S99 S100 S101 0 28 29 30 31 32 33 34 35 36 1 Fig 12. Ver 1.3 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH B B B 65 Lines 0 0 D1 When the common output is normal Line Address (Hex) 0 D2 TMX=0 08 07 06 05 04 03 02 01 00 D3 00 01 02 03 04 05 06 07 08 Page Address 65 64 63 62 61 60 5F 5E 5D Column Address (Hex) SEG No. (TMX=0) Regardless of the display start line address. Always the last line. Display Data RAM Map (66 COM) 24/51 2007/09/12 ST7575 Liquid Crystal Driver Power Circuit The Power Supply circuits generate the voltage levels necessary to drive liquid crystal driver circuits with low power consumption and the fewest components. There are voltage converter circuits, voltage regulator circuits, and voltage follower circuits. They are controlled by power control instruction. External Power Components The recommended external power components need only 2 capacitors. The detailed values of these two capacitors are determined by the panel size and loading. Fig 13. Power Circuit The referential external component values are listed below (it is determined by the worse condition of 1.4” panel). C1=0.1uF~1uF (Non-Polar/6V, default 0.1uF) R1=47KΩ~100KΩ (default 47KΩ) C2=0.1uF~1uF (Non-Polar/16V, default 0.1uF) R2=500KΩ~1MΩ (default 500KΩ) Customer applications are not necessary the same as the values listed above. The value can be determined by customer’s LCD module (panel loading and ITO resistance) and application (VDD, V0, bias and etc.). Ver 1.3 25/51 2007/09/12 ST7575 7. RESET CIRCUIT Setting RESB to “L” or RESET instruction can initialize internal function. While RESB is “L”, no instruction except read status can be accepted. RESB pin must connect to the reset pin of MPU and initialization by RESB pin is essential before operating. When RESB becomes “L”, the following procedures will start. Power Down Mode: PD=1 (Analog Power OFF, Oscillator OFF & COM/SEG output at VSS) Page Address: Y[3:0]=0 Column Address: X[6:0]=0 COM Scan Direction: Depends on “TMY” setting SEG Select Direction: Depends on “TMX” setting Display Control: Display OFF: D=E=0 Basic Instruction Set: H=0 Booster setting: Depends on “CP” setting Initial V0 Setting: VOP[6:0]=0 Bias system: BS[2:0] Depends on “BR” setting After power-on, RAM data are undefined and the display status is “Display OFF”. It’s better to initialize whole DDRAM (ex: fill all 00h or write the display pattern) before turning the Display ON. Ver 1.3 26/51 2007/09/12 ST7575 8. INSTRUCTION TABLE H=0 or 1 (H-Flag Independent) INSTRUCTION NOP COMMAND BYTE A0 R/W (RWR) D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 No operation DESCRIPTION Function Set 0 0 0 0 1 0 0 PD V H Power down; entry mode; Select instruction table Write Data 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Write data to RAM H=0 (Basic Instruction) INSTRUCTION Display Control COMMAND BYTE A0 R/W (RWR) D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 1 D 0 E Sets display configuration DESCRIPTION Set Y Address of RAM 0 0 0 1 0 0 Y3 Y2 Y1 Y0 Sets Y address of RAM 0≤Y≤9 Set X Address of RAM 0 0 1 X6 X5 X4 X3 X2 X1 X0 Sets X address of RAM 0≤X≤101 D2 D1 D0 H=1 (Extended Instruction) INSTRUCTION A0 R/W (RWR) COMMAND BYTE D7 D6 D5 D4 D3 Reserved 0 0 0 0 0 0 0 0 X Bias System 0 0 0 0 0 1 0 BS2 BS1 Reserved 0 0 0 1 X X X X X Set V0 0 0 1 VOP6 VOP5 VOP4 VOP3 VOP2 VOP1 Ver 1.3 27/51 X DESCRIPTION Do not use BS0 Set bias system (BSx) X Do not use VOP0 Set VOP parameter to register 2007/09/12 ST7575 9. INSTRUCTION DESCRIPTION H=0 or 1 (H-Flag Independent) Function Set A0 R/W(RWR) D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 1 0 0 PD V H Flag Description PD PD=0: chip is active PD=1: chip is in power down mode All LCD outputs at VSS (display off), bias generator and V0 generator off, VOUT can be disconnected, oscillator off (external clock possible), RAM contents not cleared; RAM data can be written. V Select addressing mode: V=0 for Horizontal Addressing; V=1 for Vertical Addressing. H H=0: Basic Instruction set; H=1: Extended instruction set. Data access can be used in both instruction blocks. Refer to the instruction table. Read Data By specify the column address and page address, the display data in DDRAM can be read by MPU (parallel interface). D7 D6 D5 D4 D3 D2 D1 D0 A0 R/W(RWR) 1 1 Read Data Write Data 8-bit data of Display Data from the microprocessor can be written to the RAM location specified by the column address and page address. The column address is increased by 1 automatically so that the microprocessor can continuously write data to the addressed page. During auto-increment, the column address wraps to 0 after the last column is written. A0 R/W(RWR) D7 D6 D5 D4 D3 D2 D1 D0 1 H=0 0 Write Data (Basic Instruction) Display Control This bits D and E selects the display mode. A0 R/W(RWR) D7 D6 0 0 0 0 Flag D,E Ver 1.3 D5 D4 D3 D2 D1 D0 0 0 1 D 0 E Description D 0 E 0 The bits D and E select the display mode. Display OFF 0 1 1 0 All display segments on Normal mode 1 1 Inverse video mode 28/51 2007/09/12 ST7575 Set Y Address of RAM Y [3:0] defines the Y address vector address of the display RAM. A0 R/W(RWR) D7 D6 D5 D4 0 0 0 1 0 0 D3 D2 D1 D0 Y3 Y2 Y1 Y0 Y3 Y2 Y1 Y0 Content Allowed X-Range Valid Bit 0 0 0 0 Page0 (display RAM) 0 to 101 D7~ D0 0 0 0 0 0 1 1 0 Page1 (display RAM) Page2 (display RAM) 0 to 101 0 to 101 D7~ D0 D7~ D0 0 0 0 1 1 0 1 0 Page3 (display RAM) Page4 (display RAM) 0 to 101 0 to 101 D7~ D0 D7~ D0 0 0 1 1 0 1 1 0 Page5 (display RAM) Page6 (display RAM) 0 to 101 0 to 101 D7~ D0 D7~ D0 0 1 1 0 1 0 1 0 Page7 (display RAM) Page8 (display RAM) 0 to 101 0 to 101 D7~ D0 D7 1 0 0 1 Page9 (display RAM) 0 to 101 D7 Set X Address of RAM The X address points to the columns. The range of X is 0…101. D7 D6 D5 D4 A0 R/W(RWR) 0 0 1 X6 X5 X4 D3 D2 D1 D0 X3 X2 X1 X0 D3 D2 D1 D0 0 BS2 BS1 BS0 X6 X5 X4 X3 X2 X1 X0 Column address 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 1 2 3 : 1 : 1 : 0 : 0 : 0 : 1 : 1 : 99 1 1 1 1 0 0 0 0 1 1 0 0 0 1 100 101 H=1 (Extended Instruction) System Bias Select LCD bias ratio of the voltage required for driving the LCD. A0 R/W(RWR) D7 D6 D5 D4 0 0 0 0 0 1 Recommend LCD Bias Voltage BS2 BS1 BS0 Bias 0 0 0 11 Symbol 0 0 0 1 1 0 10 9 V0 V0 0 1 1 0 1 0 8 7 VG VM 2/9 x V0 1/9 x V0 VSS VSS 1 1 0 1 1 0 6 5 1 1 1 4 Ver 1.3 Voltage for 1/9 Bias * VG range: 1.24V ≤ VG < VDD2. * VM range: 0.62V ≤ VM < VDD2. 29/51 2007/09/12 ST7575 Set V0 A0 R/W(RWR) D7 D6 D5 0 0 1 VOP6 VOP5 The operation voltage V0 can be set by software. D4 D3 D2 D1 D0 VOP4 VOP3 VOP2 VOP1 VOP0 (1) V0=( a + VOPx X b ) The parameters are explained in table 4. The maximum voltage that can be generated is depending on the VDD2 voltage and the display load current. For the V0 programmable range, V0 starts from a (6.78V, VOP[6:0]=0x01) with each step equal to b (0.03V). Note that the internal booster is turned off if VOP[6:0]=0x00. Please don’t operate this IC with this setting (VOP[6:0]=0). * The Vop must be operated in the range of 8V to 9.5V for the normal or partial display mode application, so that customer have some range(<8V; >9.5V) to adjust contrast by themselves. Table 4 Typical values for parameter for the HV-Generator programming VALUE UNIT a 6.75 V b 0.03 V Booster OFF SYMBOL VOP[6:0] (programmed) {00 hex… 7F hex} Fig 14. Ver 1.3 Setting V0 Voltage 30/51 2007/09/12 ST7575 10. COMMAND SEQUENCE This section introduces some reference operation flows. Power ON flow and instruction sequence: Operating Flow Power ON Keep RESB=L Wait power stable, t>1ms (depends on system power) Set RESB=H Wait reset finished, t>5us Initial: Power Circuit [Function Set] PD=0,V=0,H=1 [Bias System] [Set V0] [Function Set] PD=0,V=0,H=0 [Set V0 Range] Delay 50ms Initial: DDRAM Write DDRAM [ Display ON ] Normal Operating Power Sequence 1. tV2ON: VDD2 power ON delay. => 0 ≤ tV2ON ≤ No Limitation. 2. tRSTL: Reset Low time after VDD1 is stable. *1 => 0 ≤ tRSTL ≤ 50 ms . 3. tRW: Reset low pulse width. Please refer to RESB timing specification. Note: 1. IC will NOT be damaged if either VDD1 or VDD2 is OFF while another is ON. The specification listed here is to prevent abnormal display on LCD module. 2. Be sure the power is stable and the internal reset is finished (refer to RESB timing specification). Ver 1.3 31/51 2007/09/12 ST7575 Power OFF Flow and Sequence By setting PD=”1”, ST7575 will go into power save mode. The LCD driving outputs are fixed to VSS, built-in power circuits are turned OFF and a discharge process starts. Instruction Flow After the built-in power circuits are turned OFF and completely discharged, the power (VDD1 and VDD2) can be removed. An alternate method is to use the RESB signal to set ST7575 into power save mode. After hardware reset, the PD flag is “1” and ST7575 is in power save mode (same as previous case). Operating Flow After the built-in power circuits are turned OFF and completely discharged, the power (VDD1 and VDD2) can be removed. Note: 1. tIPOFF: Internal Power discharge time. => 250ms (max). 2. tV2OFF: Period between VDD1 and VDD2 OFF time. => 0 ms (min). 3. It is NOT recommended to turn VDD1 OFF before VDD2. Without VDD1, the internal status cannot be guaranteed and internal discharge-process maybe stopped. The un-discharged power maybe flows into COM/SEG output(s) and the liquid crystal in panel maybe polarized. 4. IC will NOT be damaged if either VDD1 or VDD2 is OFF while another is ON. 5. The timing is dependent on panel loading and the external capacitor(s). 6. The timing in these figures is base on the condition that: LCD Panel Size = 1.4” with C1=1uF, C2=1uF. Ver 1.3 32/51 2007/09/12 ST7575 7. When turning VDD2 OFF, the falling time should follow the specification: 8. If the power OFF flow cannot meet this specification, it is recommended to use the discharge resistors (R1 & R2 in 300ms ≤ tPFall ≤ 1sec application circuits). Ver 1.3 33/51 2007/09/12 ST7575 Power-Save Flow and Sequence ENTERING THE POWER SAVE MODE The power save mode is achieved by setting PD bit to be “1”. No specified instruction flow required. EXITING THE POWER SAVE MODE INTERNAL SEQUENCE of EXIT POWER SAVE MODE After receiving “PD=0”, the internal circuits (Power) will starts the following procedure. Note: 1. The power stable time is determined by LCD panel loading. 2. The power stable time in this figure is base on: LCD Panel Size = 1.4” with C1=1uF, C2=1uF. Ver 1.3 34/51 2007/09/12 ST7575 11. LIMITING VALUES In accordance with the Absolute Maximum Rating System; please refer to notes 1 and 2. Parameter Symbol Conditions Unit Digital Power Supply Voltage VDD1 -0.3 ~ 3.6 V Analog Power supply voltage VDD2 -0.3 ~ 3.6 V LCD Power supply voltage V0-XV0 -0.3~15 V LCD Power driving voltage VG, VM -0.3 ~ VDD2 Operating temperature Storage temperature TOPR TSTR V –30 to +85 ° –65 to +150 ° C C Notes 1. Stresses above those listed under Limiting Values may cause permanent damage to the device. 2. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. 3. Insure the voltage levels of V0, VDD2, VG, VM, VSS and XV0 always match the correct relation: V0 ≥ VDD2 > VG > VM > VSS ≥ XV0 Ver 1.3 35/51 2007/09/12 ST7575 12. HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices. 13. DC CHARACTERISTICS ° ° VDD1=1.8V to 3.3V, VSS=0V; Tamb = -30 C to +85 C; unless otherwise specified. Item Symbol Condition Rating Min. Typ. Max. Unit Applicable Pin Operating Voltage (1) VDD1 1.7 — 3.4 V VDD1 Operating Voltage (2) VDD2 2.4 — 3.4 V VDD2 Input High-level Voltage VIHC 0.7 x VDD1 — VDD1 V Input Low-level Voltage VILC VSS — 0.3 x VDD1 V Output High-level Voltage VOHC IOUT=1mA, VDD1=1.8V 0.8 x VDD1 — VDD1 V D[7:0] Output Low-level Voltage VOLC IOUT=-1mA, VDD1=1.8V VSS — 0.2 x VDD1 V D[7:0] MPU Interface MPU Interface MPU Input Leakage Current ILI -1.0 — 1.0 μA Output Leakage Current ILO -3.0 — 3.0 μA Vop=9V, ΔV=0.9V — 0.7 — KΩ COMx VG=2V, ΔV=0.2V — 0.7 — KΩ SEGx 70 75 80 Hz Liquid Crystal Driver ON Resistance Frame Frequency RON FR ° Ta=25 C FR default (1,0,0), 1/66 Duty Ta = 25°C Interface MPU Interface Note: 1. Recommend application Vop range : 8V ~ 9.5V. 2. LCD module size : 1.8” (max). Current consumption: During Display, with internal power system, current consumed by whole IC (bare die). Test Pattern Symbol Condition Rating Unit Min. Typ. Max. — 110 150 μA — 1 10 μA Note VDD1=VDD2=3.0V, Display Pattern: SNOW (Static) ISS Booster X5 VOP = 9.0 V, Bias=1/9 ° Ta=25 C Power Down Ver 1.3 ISS VDD1=VDD2=3.0V, ° Ta=25 C 36/51 2007/09/12 ST7575 14. TIMING CHARACTERISTICS System Bus Read/Write Characteristics (For the 8080 Series MPU) ° (VDD = 3.3V , Ta =-30~85 C) Item Address setup time Address hold time Signal A0 System cycle time Write L pulse width /WR Write H pulse width Read L pulse width Read H pulse width /RD Data setup time (Write) Write Data hold time (Write) Data access time (Read) D[7:0] Output disable time (Read) Symbol Condition Min. Max. tAW8 80 — tAH8 10 — tCYC8 350 — tCCLW 70 — tCCHW 50 — tCCLR 120 — tCCHR 50 tDS8 60 — tDH8 10 — tACC8 CL = 16 pF — 70 tOH8 CL = 16 pF 10 50 Unit ns ° (VDD = 2.8V , Ta =-30~85 C) Item Address setup time Address hold time Signal A0 System cycle time Write L pulse width /WR Symbol Condition Min. Max. tAW8 120 — tAH8 15 — tCYC8 450 — tCCLW 120 — Write H pulse width tCCHW 100 — Read L pulse width tCCLR 120 — tCCHR 100 — tDS8 90 — tDH8 15 — Read H pulse width /RD Data setup time (Write) Write Data hold time (Write) Data access time (Read) Output disable time (Read) Ver 1.3 D[7:0] tACC8 CL = 16 pF — 140 tOH8 CL = 16 pF 10 100 37/51 Unit ns 2007/09/12 ST7575 ° (VDD = 1.8V , Ta =-30~85 C) Item Min. Max. tAW8 150 — tAH8 30 — tCYC8 550 — tCCLW 170 — tCCHW 150 — tCCLR 170 — tCCHR 150 Data setup time (Write) tDS8 120 — Write Data hold time (Write) tDH8 30 — Address setup time Address hold time Signal A0 System cycle time Write L pulse width /WR Write H pulse width Read L pulse width Read H pulse width Data access time (Read) Output disable time (Read) /RD D[7:0] Symbol Condition tACC8 CL = 16 pF — 240 tOH8 CL = 16 pF 10 200 Unit ns *1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast, (tr + tf) ≦ (tCYC8 – tCCLW – tCCHW) for (tr + tf) ≦ (tCYC8 – tCCLR – tCCHR) are specified. *2 All timing is specified using 20% and 80% of VDD1 as the reference. *3 tCCLW and tCCLR are specified as the overlap between CSB being “L” and WR and RD being at the “L” level. Ver 1.3 38/51 2007/09/12 ST7575 System Bus Read/Write Characteristics (For the 6800 Series MPU) ° (VDD = 3.3V , Ta =-30~85 C) Min. Max. tAW6 80 — tAH6 10 — System cycle time tCYC6 240 — Enable L pulse width (WRITE) tEWLW 70 — tEWHW 50 — Enable L pulse width (READ) tEWLR 70 — Enable H pulse width (READ) tEWHR 130 Write data setup time tDS6 60 — Write data hold time tDH6 10 — Item Address setup time Address hold time Enable H pulse width (WRITE) Read data access time Signal A0 E D[7:0] Read data output disable time Symbol Condition tACC6 CL = 16 pF — 70 tOH6 CL = 16 pF 10 50 Unit ns ° (VDD = 2.8V , Ta =-30~85 C) Min. Max. tAW6 100 — tAH6 15 — System cycle time tCYC6 340 — Enable L pulse width (WRITE) tEWLW 120 — tEWHW 100 — Enable L pulse width (READ) tEWLR 120 — Enable H pulse width (READ) tEWHR 100 — tDS6 120 — Item Address setup time Address hold time Enable H pulse width (WRITE) Signal A0 E Write data setup time Write data hold time Read data access time Read data output disable time Ver 1.3 D[7:0] Symbol Condition 15 — tACC6 tDH6 CL = 16 pF — 140 tOH6 CL = 16 pF 10 100 39/51 Unit ns 2007/09/12 ST7575 ° (VDD = 1.8V , Ta =-30~85 C) Item Min. Max. tAW6 150 — tAH6 30 — System cycle time tCYC6 440 — Enable L pulse width (WRITE) tEWLW 170 — tEWHW 150 — Enable L pulse width (READ) tEWLR 170 — Enable H pulse width (READ) tEWHR 150 — Write data setup time tDS6 180 — Write data hold time tDH6 30 — Address setup time Address hold time Enable H pulse width (WRITE) Read data access time Read data output disable time Signal A0 E D[7:0] Symbol Condition tACC6 CL = 16 pF — 240 tOH6 CL = 16 pF 10 200 Unit ns *1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast, (tr + tf) ≦ (tCYC6 – tEWLW – tEWHW) for (tr + tf) ≦ (tCYC6 – tEWLR – tEWHR) are specified. *2 All timing is specified using 20% and 80% of VDD1 as the reference. *3 tEWLW and tEWLR are specified as the overlap between CSB being “L” and E. Ver 1.3 40/51 2007/09/12 ST7575 SERIAL INTERFACE (4-Line Interface) First bit Last bit ° (VDD = 3.3V , Ta =-30~85 C) Item Signal Serial clock period SCLK “H” pulse width SCLK SCLK “L” pulse width Address setup time Address hold time Data setup time A0 SDA Data hold time CSB-SCLK time CSB-SCLK time CSB Symbol Condition Min. Max. tSCYC 120 — tSHW 60 — tSLW 60 — tSAS 20 — tSAH 90 — tSDS 20 — tSDH 10 — tCSS 20 — tCSH 120 — Unit ns ° (VDD = 2.8V , Ta =-30~85 C) Item Signal Serial clock period SCLK “H” pulse width SCLK SCLK “L” pulse width Address setup time Address hold time Data setup time Data hold time CSB-SCLK time CSB-SCLK time Ver 1.3 A0 SDA CSB Symbol Min. Max. tSCYC 200 — tSHW 100 — tSLW 100 — tSAS 30 — tSAH 120 — tSDS 30 — tSDH 20 — tCSS 30 — tCSH 150 — 41/51 Condition Unit ns 2007/09/12 ST7575 ° (VDD = 1.8V , Ta =-30~85 C) Item Signal Serial clock period SCLK “H” pulse width SCLK SCLK “L” pulse width Address setup time Address hold time Data setup time Data hold time CSB-SCLK time CSB-SCLK time A0 SDA CSB Symbol Min. Max. tSCYC Condition 280 — tSHW 140 — tSLW 140 — tSAS 50 — tSAH 150 — tSDS 50 — tSDH 50 — tCSS 40 — tCSH 180 — Unit ns *1 The input signal rise and fall time (tr, tf) are specified at 15 ns or less. *2 All timing is specified using 20% and 80% of VDD1 as the standard. Ver 1.3 42/51 2007/09/12 ST7575 SERIAL INTERFACE (3-Line Interface) First bit Last bit ° (VDD = 3.3V , Ta =-30~85 C) Item Signal Serial clock period SCLK “H” pulse width SCLK SCLK “L” pulse width Data setup time SDA Data hold time CSB-SCLK time CSB-SCLK time CSB Symbol Condition Min. Max. tSCYC 120 — tSHW 60 — tSLW 60 — tSDS 20 — tSDH 10 — tCSS 20 — tCSH 130 — Unit ns ° (VDD = 2.8V , Ta =-30~85 C) Item Signal Serial clock period SCLK “H” pulse width SCLK SCLK “L” pulse width Data setup time SDA Data hold time CSB-SCLK time CSB-SCLK time CSB Symbol Condition Min. Max. tSCYC 180 — tSHW 90 — tSLW 90 — tSDS 30 — tSDH 20 — tCSS 30 — tCSH 160 — Unit ns ° (VDD = 1.8V , Ta =-30~85 C) Item Signal Serial clock period SCLK “H” pulse width SCLK SCLK “L” pulse width Data setup time Data hold time CSB-SCLK time CSB-SCLK time SDA CSB Symbol Condition Min. Max. tSCYC 240 — tSHW 120 — tSLW 120 — tSDS 60 — tSDH 50 — tCSS 40 — tCSH 190 — Unit ns *1 The input signal rise and fall time (tr, tf) are specified at 15 ns or less. *2 All timing is specified using 20% and 80% of VDD1 as the standard. Ver 1.3 43/51 2007/09/12 ST7575 RESET TIMING tRW RESB tR Internal Status During Reset ... Reset Complete ° (VDD = 3.3V , Ta =-30~85 C) Item Reset time Reset “L” pulse width Symbol Min. Max. tR Condition — 1.5 tRW 1.5 — Unit us ° (VDD = 2.8V , Ta =-30~85 C) Item Reset time Reset “L” pulse width Symbol Condition Min. Max. tR — 2.0 tRW 2.0 Unit us ° (VDD = 1.8V , Ta =-30~85 C) Item Reset time Reset “L” pulse width Ver 1.3 Symbol Condition Min. Max. tR — 3.0 tRW 3.0 — 44/51 Unit us 2007/09/12 ST7575 APPLICATION NOTE Application Circuits The application circuits are for reference only and actual settings are dependent on LCD module characteristics. COM34 COM35 COM59 25 1 26 COM33 SEG0 27 28 SEG101 COM0 COMS 129 130 COM25 COM1 131 132 156 248 249 250 COM64 Reserved Reserved COMS COM60 XV0I XV0S 244 242 243 238-241 V0S XV0O V0I 235 236-237 231-234 219 220 T4 T0 T5 T6 T7 V0O 218 T3 VGS 217 T2 228 216 T1 229-230 215 T8 214 VRS VGI 213 VSS1 VGO 212 224-227 208-211 D0 VSS2 222-223 204-207 OSC 221 203 198 199 200 D7 D6 D5 D4 D3 D2 D1 202 197 201 196 A0 ERD VDD1 CSB RWR 195 192 194 191 193 190 VDD2 RESB VDD1 189 181-184 PS0 VSS1 185-188 180 VMO 174 CP TMY PS2 PS1 176 177-179 173 TMX 175 172 163 164-166 167 168 169 COM32 COM31 COM26 VDX2 VSS1 T11 T12 BR 171 156 170 157 1 6 5 4 3 2 14 13 12 11 10 9 8 7 15 16 17 18 VDD A0 E R/W CSB RESB D0 D1 D2 D3 D4 D5 D6 D7 VSS VG V0 XV0 2007/09/12 45/51 Ver 1.3 ST7575 COM34 COM35 COM59 25 1 26 COM33 SEG0 27 28 SEG101 COM0 COMS 129 130 COM25 COM1 131 132 156 248 249 250 COM64 Reserved Reserved COMS COM60 XV0I XV0S 244 242 243 238-241 V0S XV0O V0I 235 236-237 231-234 219 220 T4 T0 T5 T6 T7 V0O 218 T3 VGS 217 T2 228 216 T1 229-230 215 T8 214 VRS VGI 213 VSS1 VGO 212 224-227 208-211 D0 VSS2 222-223 204-207 OSC 221 203 198 199 200 D7 D6 D5 D4 D3 D2 D1 202 197 201 196 A0 ERD VDD1 CSB RWR 195 192 194 191 193 190 VDD2 RESB VDD1 189 181-184 PS0 VSS1 185-188 180 VMO 174 CP TMY PS2 PS1 176 177-179 173 TMX 175 172 163 164-166 167 168 169 COM32 COM31 COM26 VDX2 VSS1 T11 T12 BR 171 156 170 157 1 6 5 4 3 2 14 13 12 11 10 9 8 7 15 16 17 18 VDD A0 /RD /WR CSB RESB D0 D1 D2 D3 D4 D5 D6 D7 VSS VG V0 XV0 2007/09/12 46/51 Ver 1.3 ST7575 ST7575 Interface : 4-Line SPI OSC : VDD1 Resolution : 66(65COM+ICON)*102(SEG) T11 : VSS1 Internal analog circuit T12 : VSS1 Internal OSC PS0 : VSS1 Booster : X5 PS1 : VSS1 Bias ratio default : 1/9 PS2 : VSS1 (bias ratio can be changed by instruction) CP : VDD1 Vop=8.76V, C=0.1uF BR : VDD1 VDD1=VDD2=2.8V TMX=TMY=VSS1 COM34 COM35 COM59 25 1 26 COM33 SEG0 27 28 SEG101 COM0 COMS 129 130 COM25 COM1 131 132 156 248 249 250 COM64 Reserved Reserved COMS COM60 XV0I XV0S 244 242 243 238-241 V0S XV0O V0I 235 236-237 V0O 231-234 VGS T7 228 T6 229-230 T5 T8 220 T0 VGI 219 T4 VGO 218 T3 224-227 217 T2 222-223 216 T1 221 215 X (D0) 214 X (D1) 213 X (D2) VRS 202 X (D3) 212 201 CSB (D4) OSC 200 VSS1 199 VSS2 198 A0 (D5) 208-211 197 VDD1 SDA (D6) 204-207 196 SCLK (D7) 203 195 192 X (CSB) X (RWR) X (ERD) X (A0) 194 191 193 190 VDD2 RESB VDD1 189 181-184 PS0 VSS1 185-188 180 VMO 174 CP TMY PS2 PS1 176 177-179 173 TMX 175 172 163 164-166 167 168 169 COM32 COM31 COM26 VDX2 VSS1 T11 T12 BR 171 156 170 157 1 2 6 5 4 3 7 8 9 10 VDD RESB CSB A0 SDA SCLK VSS VG V0 XV0 2007/09/12 47/51 Ver 1.3 ST7575 COM34 COM35 COM59 25 1 26 COM33 SEG0 27 28 SEG101 COM0 COMS 129 130 COM25 COM1 131 132 156 248 249 250 COM64 Reserved Reserved COMS COM60 XV0I XV0S 244 242 243 238-241 V0S XV0O V0I 235 236-237 V0O 231-234 VGS T7 228 T6 229-230 T5 T8 220 T0 VGI 219 T4 VGO 218 T3 224-227 217 T2 222-223 216 T1 221 215 X (D0) 214 X (D1) 213 X (D2) VRS 202 X (D3) 212 201 CSB (D4) OSC 200 VSS1 199 VSS2 198 A0 (D5) 208-211 197 VDD1 SDA (D6) 204-207 196 SCLK (D7) 203 195 192 X (CSB) X (RWR) X (ERD) X (A0) 194 191 193 190 VDD2 RESB VDD1 189 181-184 PS0 VSS1 185-188 180 VMO 174 CP TMY PS2 PS1 176 177-179 173 TMX 175 172 163 164-166 167 168 169 COM32 COM31 COM26 VDX2 VSS1 T11 T12 BR 171 156 170 157 7 8 9 VSS VG V0 XV0 SDA SCLK 6 4 3 VDD RESB CSB 2 5 1 2007/09/12 48/51 Ver 1.3 ST7575 Selection of Application Voltage Power Range Summary l Positive Booster: (VDD2 x PCn x BE) ≥ V0 or (VDD2 x PCn x BE) ≥ Vop; l Negative Booster: [–VDD2 x (PCn – 1) x BE] ≤ XV0 or [VDD2 x (PCn – 1) x BE] ≥ (Vop – VG), where VG = Vop x 2 / N; l Vop requirement: [VDD2 x (PCn – 1) x BE] ≥ [Vop x (N – 2) / N] or [Vop ≤ VDD2 x (PCn – 1) x BE x N / (N – 2)]. l PCn is the booster stage and BE is the booster efficiency. Referential values are listed below: (assume VDD2=2.4V) Module Size ≤ 1.4”: BE=80% (min); Module Size = 1.4”~1.8”: BE=76% (min). Actual BE should be determined by module loading and ITO resistance value. l 1.24 ≤ VG < VDD2. Recommend VG is: VDD2-VG around 0.5~0.8V. l VM=VG/2 and 0.62V ≤ VM < VDD2. l The worse condition should be considered: Low temperature effect and display on with snow pattern on panel (max: 1.8”). Referential LCD Module Setting VDD1=VDD2=2.8V, Panel Size=1.4” Duty 1/66 Booster Vop Bias 5X, 8.49V ~ 9V, 1/9, CP=H PRS=1 BS[2:0]=0,1,1 Note: It is recommended to reserve some range for user adjustment and temperature effect. Ver 1.3 49/51 2007/09/12 ST7575 ITO Layout Reference FPC PIN FPC PIN FPC PIN FPC FPC FPC PIN PIN PIN Ver 1.3 FPC PIN FPC PIN FPC PIN FPC FPC FPC PIN PIN PIN 50/51 FPC FPC FPC PIN PIN PIN 2007/09/12 ST7575 Reversion History Version Date 1.0 2007/01/18 1.1 2007/3/18 1.2 1.2a 1.2b 2007/04/30 2007/05/08 2007/07/25 1.2c 2007/08/28 1.3 2007/09/12 Ver 1.3 Description Formal release. l Add detailed operating flows and power sequences. l Add application note for power selection. l Separate I C interface as ST7575i. l Add operating flows and power sequences. l Add application note for Vop selection and power setting. l Add Temperature Gradient of Regulator. l Update ITO Resistance suggestion: No Limitation => 5K. l Rearrange Microprocessor Interface section. l More detailed application circuits. l Fix typing mistake. l Fix Vop voltage range mistype. l Add an alternated power OFF operating flow. l Fix typing mistake (PAD167 & PAD180 are VSS1). l Fix typing mistake (PAD Coordinate of VRS). l Update PAD Size: PAD 213~221, 20um x 60um l Fix typing mistake of MPU interface (Page 18). l Fix typing mistake of 8080 timing (Page 37). l Add discharge on VG. 2 51/51 2007/09/12