SITRONIX ST7573

ST
Sitronix
ST7573
132 x 33 Dot Matrix LCD Controller/Driver
1. INTRODUCTION
ST7573 is a driver & controller LSI for graphic dot-matrix liquid crystal display systems. ST7573 contains 132 segment and
33 common driver circuits. This chip is connected directly to a microprocessor, accepts 3-line, 4-line serial peripheral
interface (SPI) or 8-bit parallel interface, display data can stores in an on-chip Display Data RAM (DDRAM) of 132 x 33 bits.
It performs Display Data RAM read/write operation with no external operating clock to minimize power consumption. In
addition, because it contains power supply circuits to drive liquid crystal, it is possible to make a display system with the
fewest components.
2. FEATURES
Single-chip LCD controller & driver
Voltage regulation temperature gradient -0.07%/°C
Driver Output Circuits
Programmable Booster stages: X3,X4.
132 segments / 32 commons + 1 ICON common
On-chip electronic contrast control function
132 segments / 16 commons + 1 ICON common
132 segments / 8 commons + 1 ICON common
Built-in Voltage Follower generates LCD bias
voltages (1/4 to 1/7).
On-chip Display Data RAM (DDRAM)
Built-in oscillator
Capacity: 132X33=4356 bits
Microprocessor Interface
Built-in oscillator requires no external components
(external clock input is also supported)
8-bit parallel bi-directional interface with 6800-series
External RESB (reset) pin
or 8080-series
Supply voltage range
4-line SPI (serial peripheral interface) available (only
VDD - VSS (Digital): 2.4 to 3.3V (typical);
write operation)
VDD2 - VSS (Analog): 2.4 to 3.3V (typical).
3-line SPI (serial peripheral interface) available
Display supply voltage range
On-chip Low Power Analog Circuit
Temperature range: -30 to +85 degree
Embedded Boosters with voltage regulation function
Programmable voltage (LCD Vop): 8.31V (max)
that generates high-accuracy voltage.
ST7573
Ver 1.0b
6800 , 8080 , 4-Line , 3-Line interface
1/46
2007/07/12
Reverse
Reverse
Reverse
Reverse
Reverse
Reverse
Reverse
Reverse
Reverse
Reverse
Reverse
Reverse
PS0
PS1
PS2
MLB
T11
PM
T10
VDD
VDD
VDD
VDD2
VDD2
VDD2
VM
VM
VM
VGI
VGI
VGI
VGI
VGS
VGO
VGO
VSS
VSS
VSS
V0O
V0O
V0S
V0I
V0I
V0I
V0I
XV0I
XV0I
XV0I
XV0I
XV0S
XV0O
XV0O
T1
T2
T3
T4
T0
T5
T6
T7
T8
12
Ver 1.0b
40
50
70.0
60.0
11~12
84.5
97~115
34.0
12~39
60.0
115~116
57.0
39~40
89.0
116~247
34.0
40~49
60.0
247~248
57.0
49~50
70.0
248~267
34.0
2/46
97
72~73
73~96
COM29
COM30
COM31
84.5
60.0
96
5~6
6~11
89
60.0
87
50~72
114
113
116
60.0
82
SEG4
SEG3
SEG2
SEG1
SEG0
Reserve
Reserve
COMS1
COM16
COM17
COM18
1~5
74
Pitch
68
PAD
64
Pitch
57
118
55
248
PAD
47
37
31
COM1
COM0
SEG131
SEG130
SEG129
SEG128
SEG127
265
264
267
Bump Height:
T9
D7
D6
D5
D4
D3
D2
D1
D0
ERD
RWR
A0
CSB
OSC
RESB
VRS
VDD
VDD
VDD
VDD
VDD2
VDD2
VDD2
VDD2
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
6
Reserve
Reserve
Reserve
COMS2
COM15
COM14
Chip Size:
24
VDD2
VDD2
VDD
VDD
VDD
1
ST7573
3. ST7573 Pad Arrangement (COG)
6074µm(X) x 720µm(Y)
Chip Thickness: 480µm
15µm
PAD Pitch:
Rough layout
For easy LCM design, the Power-1, Power-2 & Power-3 are identical (any one of them can be used).
Power-3 has VGI, VGS, V0O, V0I, V0S, XV0O, XV0I and XV0S which are not in Power-1 or Power-2.
2007/07/12
ST7573
4. Pad Center Coordinates
PAD No.
PAD Name
X
Y
PAD No.
PAD Name
X
Y
1
VDD2
-2899.00
-286.50
46
VGO
-121.00
-286.50
2
VDD2
-2839.00
-286.50
47
VSS
-61.00
-286.50
3
VDD
-2779.00
-286.50
48
VSS
-1.00
-286.50
4
VDD
-2719.00
-286.50
49
VSS
59.00
-286.50
5
VDD
-2659.00
-286.50
50
V0O
129.00
-286.50
6
DUMMY
-2574.50
-286.50
51
V0O
189.00
-286.50
7
DUMMY
-2514.50
-286.50
52
V0S
249.00
-286.50
8
DUMMY
-2454.50
-286.50
53
V0I
309.00
-286.50
9
DUMMY
-2394.50
-286.50
54
V0I
369.00
-286.50
10
DUMMY
-2334.50
-286.50
55
V0I
429.00
-286.50
11
DUMMY
-2274.50
-286.50
56
V0I
489.00
-286.50
12
Reserve
-2190.00
-286.50
57
XV0I
549.00
-286.50
13
Reserve
-2130.00
-286.50
58
XV0I
609.00
-286.50
14
Reserve
-2070.00
-286.50
59
XV0I
669.00
-286.50
15
Reserve
-2010.00
-286.50
60
XV0I
729.00
-286.50
16
Reserve
-1950.00
-286.50
61
XV0S
789.00
-286.50
17
Reserve
-1890.00
-286.50
62
XV0O
849.00
-286.50
18
Reserve
-1830.00
-286.50
63
XV0O
909.00
-286.50
19
Reserve
-1770.00
-286.50
64
T1
969.00
-286.50
20
Reserve
-1710.00
-286.50
65
T2
1029.00
-286.50
21
Reserve
-1650.00
-286.50
66
T3
1089.00
-286.50
22
Reserve
-1590.00
-286.50
67
T4
1149.00
-286.50
23
Reserve
-1530.00
-286.50
68
T0
1209.00
-286.50
24
PS0
-1470.00
-286.50
69
T5
1269.00
-286.50
25
PS1
-1410.00
-286.50
70
T6
1329.00
-286.50
26
PS2
-1350.00
-286.50
71
T7
1389.00
-286.50
27
MLB
-1290.00
-286.50
72
T8
1449.00
-286.50
28
T11
-1230.00
-286.50
73
T9
1519.00
-286.50
29
PM
-1170.00
-286.50
74
D7
1579.00
-286.50
30
T10
-1110.00
-286.50
75
D6
1639.00
-286.50
31
VDD
-1050.00
-286.50
76
D5
1699.00
-286.50
32
VDD
-990.00
-286.50
77
D4
1759.00
-286.50
33
VDD
-930.00
-286.50
78
D3
1819.00
-286.50
34
VDD2
-870.00
-286.50
79
D2
1879.00
-286.50
35
VDD2
-810.00
-286.50
80
D1
1939.00
-286.50
36
VDD2
-750.00
-286.50
81
D0
1999.00
-286.50
37
VM
-690.00
-286.50
82
ERD
2059.00
-286.50
38
VM
-630.00
-286.50
83
RWR
2119.00
-286.50
39
VM
-570.00
-286.50
84
A0
2179.00
-286.50
40
VGI
-481.00
-286.50
85
CSB
2239.00
-286.50
41
VGI
-421.00
-286.50
86
OSC
2299.00
-286.50
42
VGI
-361.00
-286.50
87
RESB
2359.00
-286.50
43
VGI
-301.00
-286.50
88
VRS
2419.00
-286.50
44
VGS
-241.00
-286.50
89
VDD
2479.00
-286.50
45
VGO
-181.00
-286.50
90
VDD
2539.00
-286.50
Ver 1.0b
3/46
2007/07/12
ST7573
PAD No.
PAD Name
X
Y
PAD No.
PAD Name
X
Y
91
VDD
2599.00
-286.50
136
SEG[20]
1564.00
255.00
92
VDD
2659.00
-286.50
137
SEG[21]
1530.00
255.00
93
VDD2
2719.00
-286.50
138
SEG[22]
1496.00
255.00
94
VDD2
2779.00
-286.50
139
SEG[23]
1462.00
255.00
95
VDD2
2839.00
-286.50
140
SEG[24]
1428.00
255.00
96
VDD2
2899.00
-286.50
141
SEG[25]
1394.00
255.00
97
COM[31]
2913.00
255.00
142
SEG[26]
1360.00
255.00
98
COM[30]
2879.00
255.00
143
SEG[27]
1326.00
255.00
99
COM[29]
2845.00
255.00
144
SEG[28]
1292.00
255.00
100
COM[28]
2811.00
255.00
145
SEG[29]
1258.00
255.00
101
COM[27]
2777.00
255.00
146
SEG[30]
1224.00
255.00
102
COM[26]
2743.00
255.00
147
SEG[31]
1190.00
255.00
103
COM[25]
2709.00
255.00
148
SEG[32]
1156.00
255.00
104
COM[24]
2675.00
255.00
149
SEG[33]
1122.00
255.00
105
COM[23]
2641.00
255.00
150
SEG[34]
1088.00
255.00
106
COM[22]
2607.00
255.00
151
SEG[35]
1054.00
255.00
107
COM[21]
2573.00
255.00
152
SEG[36]
1020.00
255.00
108
COM[20]
2539.00
255.00
153
SEG[37]
986.00
255.00
109
COM[19]
2505.00
255.00
154
SEG[38]
952.00
255.00
110
COM[18]
2471.00
255.00
155
SEG[39]
918.00
255.00
111
COM[17]
2437.00
255.00
156
SEG[40]
884.00
255.00
112
COM[16]
2403.00
255.00
157
SEG[41]
850.00
255.00
113
COMS1
2369.00
255.00
158
SEG[42]
816.00
255.00
114
Reserve
2335.00
255.00
159
SEG[43]
782.00
255.00
115
Reserve
2301.00
255.00
160
SEG[44]
748.00
255.00
116
SEG[0]
2244.00
255.00
161
SEG[45]
714.00
255.00
117
SEG[1]
2210.00
255.00
162
SEG[46]
680.00
255.00
118
SEG[2]
2176.00
255.00
163
SEG[47]
646.00
255.00
119
SEG[3]
2142.00
255.00
164
SEG[48]
612.00
255.00
120
SEG[4]
2108.00
255.00
165
SEG[49]
578.00
255.00
121
SEG[5]
2074.00
255.00
166
SEG[50]
544.00
255.00
122
SEG[6]
2040.00
255.00
167
SEG[51]
510.00
255.00
123
SEG[7]
2006.00
255.00
168
SEG[52]
476.00
255.00
124
SEG[8]
1972.00
255.00
169
SEG[53]
442.00
255.00
125
SEG[9]
1938.00
255.00
170
SEG[54]
408.00
255.00
126
SEG[10]
1904.00
255.00
171
SEG[55]
374.00
255.00
127
SEG[11]
1870.00
255.00
172
SEG[56]
340.00
255.00
128
SEG[12]
1836.00
255.00
173
SEG[57]
306.00
255.00
129
SEG[13]
1802.00
255.00
174
SEG[58]
272.00
255.00
130
SEG[14]
1768.00
255.00
175
SEG[59]
238.00
255.00
131
SEG[15]
1734.00
255.00
176
SEG[60]
204.00
255.00
132
SEG[16]
1700.00
255.00
177
SEG[61]
170.00
255.00
133
SEG[17]
1666.00
255.00
178
SEG[62]
136.00
255.00
134
SEG[18]
1632.00
255.00
179
SEG[63]
102.00
255.00
135
SEG[19]
1598.00
255.00
180
SEG[64]
68.00
255.00
Ver 1.0b
4/46
2007/07/12
ST7573
PAD No.
PAD Name
X
Y
PAD No.
PAD Name
X
Y
181
SEG[65]
34.00
255.00
226
SEG[110]
-1496.00
255.00
182
SEG[66]
0.00
255.00
227
SEG[111]
-1530.00
255.00
183
SEG[67]
-34.00
255.00
228
SEG[112]
-1564.00
255.00
184
SEG[68]
-68.00
255.00
229
SEG[113]
-1598.00
255.00
185
SEG[69]
-102.00
255.00
230
SEG[114]
-1632.00
255.00
186
SEG[70]
-136.00
255.00
231
SEG[115]
-1666.00
255.00
187
SEG[71]
-170.00
255.00
232
SEG[116]
-1700.00
255.00
188
SEG[72]
-204.00
255.00
233
SEG[117]
-1734.00
255.00
189
SEG[73]
-238.00
255.00
234
SEG[118]
-1768.00
255.00
190
SEG[74]
-272.00
255.00
235
SEG[119]
-1802.00
255.00
191
SEG[75]
-306.00
255.00
236
SEG[120]
-1836.00
255.00
192
SEG[76]
-340.00
255.00
237
SEG[121]
-1870.00
255.00
193
SEG[77]
-374.00
255.00
238
SEG[122]
-1904.00
255.00
194
SEG[78]
-408.00
255.00
239
SEG[123]
-1938.00
255.00
195
SEG[79]
-442.00
255.00
240
SEG[124]
-1972.00
255.00
196
SEG[80]
-476.00
255.00
241
SEG[125]
-2006.00
255.00
197
SEG[81]
-510.00
255.00
242
SEG[126]
-2040.00
255.00
198
SEG[82]
-544.00
255.00
243
SEG[127]
-2074.00
255.00
199
SEG[83]
-578.00
255.00
244
SEG[128]
-2108.00
255.00
200
SEG[84]
-612.00
255.00
245
SEG[129]
-2142.00
255.00
201
SEG[85]
-646.00
255.00
246
SEG[130]
-2176.00
255.00
202
SEG[86]
-680.00
255.00
247
SEG[131]
-2210.00
255.00
203
SEG[87]
-714.00
255.00
248
COM[0]
-2267.00
255.00
204
SEG[88]
-748.00
255.00
249
COM[1]
-2301.00
255.00
205
SEG[89]
-782.00
255.00
250
COM[2]
-2335.00
255.00
206
SEG[90]
-816.00
255.00
251
COM[3]
-2369.00
255.00
207
SEG[91]
-850.00
255.00
252
COM[4]
-2403.00
255.00
208
SEG[92]
-884.00
255.00
253
COM[5]
-2437.00
255.00
209
SEG[93]
-918.00
255.00
254
COM[6]
-2471.00
255.00
210
SEG[94]
-952.00
255.00
255
COM[7]
-2505.00
255.00
211
SEG[95]
-986.00
255.00
256
COM[8]
-2539.00
255.00
212
SEG[96]
-1020.00
255.00
257
COM[9]
-2573.00
255.00
213
SEG[97]
-1054.00
255.00
258
COM[10]
-2607.00
255.00
214
SEG[98]
-1088.00
255.00
259
COM[11]
-2641.00
255.00
215
SEG[99]
-1122.00
255.00
260
COM[12]
-2675.00
255.00
216
SEG[100]
-1156.00
255.00
261
COM[13]
-2709.00
255.00
217
SEG[101]
-1190.00
255.00
262
COM[14]
-2743.00
255.00
218
SEG[102]
-1224.00
255.00
263
COM[15]
-2777.00
255.00
219
SEG[103]
-1258.00
255.00
264
COMS2
-2811.00
255.00
220
SEG[104]
-1292.00
255.00
265
Reserve
-2845.00
255.00
221
SEG[105]
-1326.00
255.00
266
Reserve
-2879.00
255.00
222
SEG[106]
-1360.00
255.00
267
Reserve
-2913.00
255.00
223
SEG[107]
-1394.00
255.00
224
SEG[108]
-1428.00
255.00
225
SEG[109]
-1462.00
255.00
* Unit: µm
Ver 1.0b
5/46
2007/07/12
ST7573
5. BLOCK DIAGRAM
VGI
VGO
VGS
VG
Generator
XV0I
XV0O
XV0S
XV0
Generator
V0I
V0O
V0S
V0
Generator
PM
Power
System
SEGMENT
Drivers
Display Data Latchs
COMMON
Drivers
COMS
Voltage
Follower
COMS
COM31
COM0
SEG131
SEG0
VM
COMMON
Output
Controller
DTY
Display Data RAM
(DDRAM)
132X33
Timing
Generator
Oscillator
OSC
VDD2
Data
Register
VDD
VSS
Address
Counter
Control
Registers
Command Decoder
Reset
Circuit
MPU INTERFACE ( Parallel / Serial )
Ver 1.0b
PS2
PS1
PS0
D7
D6
D5
D4
D3
D2
D1
D0
/RD (E)
/WR (R/W)
A0
CSB
MLB
RESB
Figure 1
Block Diagram
6/46
2007/07/12
ST7573
6. PIN DESCRIPTION
Pin Name
I/O
Pin
Description
Count
LCD DRIVER OUTPUTS
LCD segment driver outputs.
This display data and the M signal control the output voltage of segment
driver.
SEG0…SEG131
Segment driver output voltage
Display data
Frame
Normal display
Reverse display
H
+
VG
VSS
H
-
VSS
VG
L
+
VSS
VG
L
-
VG
VSS
VSS
VSS
O
Power save mode
132
LCD column driver outputs.
This internal scanning data and M signal control the output voltage of
common driver.
COM0…COM31
Common driver output voltage
Display data
Frame
H
+
XV0
H
-
V0
L
+
VM
L
-
VM
O
Normal display
Reverse display
Power save mode
COMS1…COMS2
O
32
VSS
Common output for the icon. The output signals of two pins are the same.
When not used, this pin should be floating.
2
MICROPROCESSOR INTERFACE
Microprocessor interface select input pin.
PS2
PS0…PS2
I
PS1
PS0
State
“L”
“L”
“L”
4 Pin-SPI MPU interface
“H”
“L”
“L”
3 Pin-SPI MPU interface
“L”
“H”
“L”
8080-series parallel MPU interface
“H”
“H”
“L”
6800-series parallel MPU interface
3
Chip select input pins.
CSB
I
Data/instruction I/O is enabled only when CSB is “L”. When chip select is
1
non-active, D0 to D7 is high impedance.
RESB
I
Reset input pin.
When RESB is “L”, initialization is executed.
1
It determines whether the data bits are data or a command.
A0
I
A0=“H”: Indicates that D0 to D7 are display data.
A0=“L”: Indicates that D0 to D7 are control data.
1
When in 3-line SPI interface, left it connected to VDD.
Ver 1.0b
7/46
2007/07/12
ST7573
Read/Write execution control pin (PS[0:1]=[L:H]).
PS2
MPU type
RWR
H
6800-series
R/W
Description
Read/Write control input pin
RWR
R/W=“H”: read;
R/W=“L”: write.
I
1
Write enable clock input pin
L
8080-series
/WR
The data on D0 to D7 are latched at
the rising edge of the /WR signal.
When in the serial interface, left it connected to VDD.
Read/Write execution control pin (PS[0:1]=[L:H]).
PS2
MPU Type
/RD(E)
Description
Read/Write control input pin
R/W=“H”: When E is “H”, D0 to D7
H
ERD
6800-series
E
I
are in an output status;
R/W=“L”: The data on D0 to D7 are
latched at the falling edge of the E
1
signal.
Read enable clock input pin.
L
8080-series
/RD
When /RD is “L”, D0 to D7 are in an
output status.
When in the serial interface, left it connected to VDD.
When using 8-bit parallel interface: 6800, 8080
8-bit bi-directional data bus that is connected to the standard 8-bit
microprocessor data bus.
When chip select is not active, D0 to D7 is high impedance.
When using serial interface: 4-LINE
D0: serial input clock (SCLK);
D7…D0
I/O
D1, D2, D3: serial input data (SDA), must be connected together;
D4~D7 must be connected to VDD (not used).
8
When chip select is not active, D0 to D7 is high impedance.
When using serial interface: 3-LINE
D0: serial input clock (SCLK).
D1, D2, D3: serial input data (SDA), must be connected together;
D4~D7 must be connected to VDD (not used).
When chip select is not active, D0 to D7 is high impedance.
Ver 1.0b
8/46
2007/07/12
ST7573
LCD DRIVER CLOCK SUPPLY
When the on-chip oscillator is used, this input must be connected to
VDD. An external clock signal, if used, is connected to this pin. The
OSC
I
oscillator and external clock are both inhibited by connecting the OSC pin
to VSS and the display is not clocked and may be left in a DC state. To
1
avoid this, the chip should always be put into Power Down Mode before
stopping the clock.
POWER SUPPLY PIN
VSS
Power
Ground.
3
Digital Supply voltage.
VDD
Power
The 2 supply rails, VDD and VDD2 , could be connected together (for single
power).
10
If a Digital Option pin is high, must be this level.
Analog Supply voltage.
VDD2
Power
The 2 supply rails, VDD and VDD2 , could be connected together (for single
VRS
Power
Reference voltage. Must be left open.
9
power).
1
Positive LCD driving voltage for commons.
V0I is the V0 power source for the LCD driver. If using external V0, apply
V0I, V0O, V0S
Power
the external power source on these pads.
V0O is the internal V0 regulator output pad.
7
V0S is the feedback for the internal V0 voltage compensation circuit.
They should be separate in ITO and be connected together by FPC.
Negative LCD driving voltage for commons.
XV0I is the XV0 power source for the LCD driver. If using external XV0,
XV0I, XV0O,XV0S
Power
apply the external power source on these pads.
XV0O is the internal XV0 regulator output pad.
7
XV0S is the feedback for the internal XV0 voltage compensation circuit.
They should be separate in ITO and be connected together by FPC.
Ver 1.0b
9/46
2007/07/12
ST7573
LCD driving voltage for segments.
VGI is the VG power source for the LCD driver. If using external VG, apply
VGI, VGO, VGS
Power
external power source on these pads.
7
VGO is the internal VG regulator output pad.
VGS is the feedback for the internal VG voltage compensation circuit.
They should be separate in ITO and be connected together by FPC.
VM
Power
LCD driving voltage for commons.
3
CONFIGURATION PIN
Data format (MSB on top or LSB on top).
MLB
I
MLB=”H”, MSB on top (D7 on top);
1
MLB=”L”, LSB on top (D0 on top).
Set power mode. This pin will change the V0 (Vop) formula parameter.
PM
I
V0=( a + VOP[6:0] x b )
1
PM=”L”, a=3.0V, b=0.03V;
PM=”H”, a=4.5V, b=0.03V.
TEST PIN
T0~T8: left them open.
T0…T11
Test
12
T9 must connect to VSS.
T10 and T11 must connect to VDD.
The unused pins should be left floating.
The Microprocessor Interface pins should not be left floating under any operation mode.
Recommend I/O pins ITO Resistance Limitation
Pin Name
ITO Resistance
VRS, T[8:0]
Floating
VSS
<100Ω
Ω
VDD
<100Ω
Ω
VDD2
<100Ω
Ω
V0 (V0I + V0O + V0S), XV0 (XV0I + XV0O + XV0S), VG (VGI + VGO + VGS), VM
<500Ω
Ω
CSB, A0, /RD, /WR, D[7:0]
<1KΩ
Ω
*1
PS[2:0], OSC , MLB, T[11:9]
<5KΩ
Ω
RESB
<10KΩ
Ω
Notes:
1.
If using internal clock, OSC is connect to VDD and the limitation of ITO resistance will be “No Limitation”.
If using external clock, the ITO resistance of OSC should be kept lower than 500Ω to keep the clock signal quality.
Ver 1.0b
10/46
2007/07/12
ST7573
7. FUNCTIONS DESCRIPTION
MICROPROCESSOR INTERFACE
Chip Select Input
The CSB pin is used for chip selection. ST7573 can interface with an MPU when CSB is "L". When CSB is “H”, the control
pins (A0, /RD and /WR) are disabled and D0 to D7 are set to be high impedance. If using serial interface, the internal shift
register and the counter are reset when CSB=”H”.
Parallel / Serial Interface
ST7573 has five types of interface to communicate with an MPU, which are three serial and two parallel interfaces. The
parallel or serial interface is determined by PS[2:0] pin as shown below.
Table 1
Parallel/Serial Interface Selection
PS2
PS1
PS0
CSB
A0
State
“L”
“L”
“L”
CSB
A0
4 Pin-SPI MPU interface
“H”
“L”
“L”
CSB
"H"
3 Pin-SPI MPU interface
“L”
“H”
“L”
CSB
A0
8080-series parallel MPU interface
“H”
“H”
“L”
CSB
A0
6800-series parallel MPU interface
Parallel Interface
The 8-bit bi-directional data bus is used in parallel interface and the type of MPU is selected by PS[2:0] as shown in Table 2.
The type of data transfer is determined by A0, ERD and RWR as shown in Table 3.
Table 2
Microprocessor Selection for Parallel Interface
PS2
PS1
PS0
CSB
A0
ERD
RWR
DB0 to DB7
MPU bus
H
H
L
CSB
L
H
L
CSB
A0
E
R/W
DB0 to DB7
6800-series
A0
/RD
/WR
DB0 to DB7
8080-series
Table 3
Common
A0
6800-series
Parallel Data Transfer
8080-series
E
R/W
/RD
/WR
Description
(/RD)
(/WR)
(E)
(R/W)
H
H
H
L
H
H
H
L
H
L
Display data write
L
H
H
L
H
Register status read
L
H
L
H
L
Writes to internal register (instruction)
Display data read out
NOTE: When ERD pin is always pulled high in 6800-series interface, the CSB can be used as enable signal. In this case,
interface data is latched at the rising edge of CSB and the access type is determined by A0, RWR as 6800-series mode.
Serial Interface
ST7573 supports 3 kinds of serial interface and the type is selected by PS2~PS0 as shown below.
Ver 1.0b
Serial Mode
PS2
PS1
PS0
CSB
A0
4-line SPI interface
L
L
L
CSB
A0
3-line SPI interface
H
L
L
CSB
11/46
Not Used
Fix to “H”
2007/07/12
ST7573
PS2=“L”, PS1=“L”, PS0=“L”: 4-line SPI interface
When ST7573 is set into 4-line SPI interface mode, setting CSB to be “L” will active this chip. If CSB is “H”, the internal 8-bit
shift register and a 3-bit counter are reset. When CSB is “L”, the serial data (SDA) and the serial clock (SCLK) are set into
input mode. The input signal on SDA will be latched into the shift register from D7 to D0 at the rising edge of the serial clock.
The display data/instruction indication is controlled via the register select pin: A0. If A0=”L”, the input signal on SDA will be
treated as instruction; if A0=”H”, the input signal on SDA will be treated as data. After 8-bit data are written into the Data
Display RAM, the DDRAM column address pointer will be increased by one automatically.
Figure 2
4-line SPI Timing
PS2=“H”, PS1=“L”, PS0=“L”: 3-line SPI interface
Because 3-line SPI interface mode does not have a register selection pin “A0”, this mode latches the A0 bit first and then
latches 8-bit input (please refer to the following figure).
Figure 3
Ver 1.0b
3-line SPI Timing
12/46
2007/07/12
ST7573
Data Transfer
ST7573 uses bus holder and internal data bus for data transfer with the MPU. When writing data from the MPU to on-chip
RAM, data is automatically transferred from the bus holder to the RAM as shown in Figure 4. And when reading data from
on-chip RAM to the MPU, the data for the initial read cycle is stored in the bus holder (dummy read) and the MPU reads this
stored data from bus holder for the next data read cycle as shown in Figure 5. This means that a dummy read cycle must be
inserted between each pair of address sets when a sequence of address sets is executed. Therefore, the data of the
specified address cannot be output with the read display data instruction right after the address sets, but can be output at
the second read of data.
Figure 4
Write Timing
MPU signal
A0
/WR
D0 to D7
N
D(N)
D(N+1) D(N+2)
D(N+3)
N
D(N)
D(N+1)
D(N+2)
D(N+3)
N
N+1
N+2
N+3
Internal signals
/WR
BUS HOLDER
COLUMN ADDRESS
Figure 5
Read Timing
MPU signal
A0
/W R
/RD
D0 to D7
N
Dum m y
D(N)
D(N+1)
Internal signals
/W R
/RD
BUS HOLDER
COLUMN ADDRESS
Ver 1.0b
N
N
13/46
D(N)
D(N+1)
D(N+2)
D(N)
D(N+1)
D(N+2)
2007/07/12
ST7573
DISPLAY DATA RAM (DDRAM)
ST7573 contains a 132X33 bit static RAM that stores the display data. The Display Data RAM stores the dot data for the
LCD display. It is 132-column by 33-row addressable array: 132X33 (4-page X 8-bit + 1-page X 1-bit). Each pixel can be
selected when the page and column addresses are specified. The 33 rows are divided into 4 pages (with 8 lines, COM 0~31)
and the 4th page (with 1 lines, COMS). Data is read from or written to each page directly through D7 to D0. The display data
(D7~D0) corresponds to the LCD common-line direction (default: top to down). The microprocessor can write to and read
(only Parallel interfaces) from DDRAM by the I/O buffer. Since the LCD controller operates independently, data can be
written into RAM at the same time as data is being displayed without causing the LCD flicker or data-conflict.
DDRAM ORGANIZATION
Data is written in bytes into the RAM matrix of ST7573 as shown in Figure 6~Figure 9. The Display Data RAM is a matrix of
132 by 33 bits. The address pointer keeps the X and Y address. The valid address ranges are: X=0~131, Y=0~4.
The default data orientation of DDRAM is controlled by the hardware pin “MLB”.
When MLB=”L”, the data write into DDRAM is from D0~D7 (LSB on top). Please refer to Figure 6.
When MLB=”H”, the data write into DDRAM is from D7~D0 (MSB on top). Please refer to Figure 7.
Figure 6
DDRAM Format, If MLB=0
Figure 7
DDRAM Format, If MLB=1
COLUMN ADDRESS CIRCUIT
Column Address Circuit has an 8-bit preset counter that points to each column of DDRAM as shown in Figure 6. The valid
range is from 0 to 131. The DDRAM column address can be specified by the Set X address instruction.
PAGE ADDRESS CIRCUIT
This circuit is for providing a page address to Display Data RAM. It incorporates 3-bit Y address register and can be
programmed by the “Set Y address of RAM” instruction. Page Address 4 is a special RAM area for icon (please refer to
Figure 6 & Figure 7).
Ver 1.0b
14/46
2007/07/12
ST7573
START LINE ADDRESS CIRCUIT
This circuit assigns DDRAM a line address that is scanned first at the beginning of each frame. By setting Start Line
Address repeatedly, the display pattern looks like scrolling vertically in the screen without changing the contents of DDRAM
(refer to Figure 11). When setting the Start Line Address (with “Set Start Line” instruction), the data of the same specified
line address in DDRAM are transferred to the Display Data Latch Circuit at the beginning of each frame. If icon is used, icon
RAM will not be scrolled with DDRAM.
ADDRESSING
ST7573 will automatically increases the address when sequential access. This feature allows MPU to access the display
data in DDRAM continuously without setting the address before each access.
In horizontal addressing mode, the X address is automatically increased by 1 after each byte access (refer to Figure 8).
After the last X address (X=131), X address wraps around to 0 and Y address increases to the next page. After the very last
address (X=131, Y=4), the address pointers wrap around to the original address (X=0, Y=0).
In vertical addressing mode, the Y address is automatically increased by 1 after each byte access (refer to Figure 9). After
the last Y address (Y=4), Y address wraps around to 0 and X address increases to the next column. After the very last
address (X=131, Y=4), the address pointers wrap around to the original address (X=0, Y=0).
Figure 8
Ver 1.0b
Addressing Mode: Horizontal (V=0)
Figure 9
15/46
Addressing Mode: Vertical (V=1)
2007/07/12
ST7573
LCD DRIVER DISPLAY DIRECTION
Register bits XD (horizontal direction) and MY (vertical mirror) control the horizontal and vertical display direction. XD
controls the X-address write direction in DDRAM while MY controls the common output direction. Therefore, it is necessary
to rewrite the display data to DDRAM after changing XD-bit setting. Refer to the following figure.
COM
Y Address
Y2
Y1
Y0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
Data Format
MLB=0
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
MLB=1
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
1/33 Duty
B B B
B
B
B
B B B
B
B
B
Page 0
B B B
B B B
B
B
B
B
B
B B B
B B B B B
B
B
B
B
B
B
B B B B
B
B
B
B
B B B B
B
B
B
B
B
B
Page 1
Page 2
Page 3
Page 4
1/9 Duty
1/17 Duty
MY=0
MY=1
MY=0
MY=1
MY=0
MY=1
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COMS
COM31
COM30
COM29
COM28
COM27
COM26
COM25
COM24
COM23
COM22
COM21
COM20
COM19
COM18
COM17
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
COMS
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
COMS
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
COMS
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
COMS
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
COMS
PAD
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
113, 264
XD=1
XD=0
Figure 10 LCD Driver Display Direction
Ver 1.0b
16/46
2007/07/12
ST7573
DDRAM MAP vs. START LINE
Figure 11 Display Data RAM Map (33 COM)
Ver 1.0b
17/46
2007/07/12
ST7573
LCD DRIVER CIRCUIT
ST7573 built-in LCD driver circuit has 132-channel segment drivers and 33-channel common drivers. The LCD panel
driving voltage depends on the combination of display data and M signal (frame indicator).
Figure 12 External Power Parts
IC Internal
IC External
V0
Generator
V0
C2
VG
Grnerator
VG
C1
VDD2
VSS
XV0
Generator
Ver 1.0b
R1
18/46
VSS
C1: 0.1uF~1.0uF
(Non-Polar/6V)
XV0
C2: 0.1uF~1.0uF
(Non-Polar/16V)
R1: Reserve
(Default NC.)
2007/07/12
ST7573
PARTIAL DISPLAY (SOFTWARE)
The Partial Display function is controlled by software instruction. This feature is available under 1/9 duty mode and 1/17
duty mode. If duty mode is 1/33, the function of Partial Display is ineffective. The start common of Partial Display function is
selected by “Display Part” command. Through combining the commands of “Display Duty” and “Display Part”, there are 6
options for Partial Display operation (Figure 13~ Figure 14 referred to explain 3 kinds of Partial Display operation).
Figure 15 Partial Display OFF
Figure 16 Partial Display: 1/17 Duty, (DP[1:0]=0,0)
Ver 1.0b
19/46
2007/07/12
ST7573
Figure 17 Partial Display: 1/17 Duty, (DP[1:0]=0,1)
Figure 18 Partial Display: 1/9 Duty, (DP[1:0]=1,0)
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
Ver 1.0b
20/46
2007/07/12
ST7573
8. RESET CIRCUIT
Setting RESB to “L” can initialize internal function. While RESB is “L”, no instruction except read status can be accepted.
The initialization by RESB is essential before using.
When RESB becomes “L”, the following procedures will start.
Fix COM/SEG outputs at VSS.
Page address: Y[2:0]=0
Column address: X[7:0]=0
COM Scan Direction MY=0
SEG Select Direction XD=1
Data Format: MLB=MLB pin setting
Power down mode: PD=1
Initial V0 setting: VOP[6:0]=0
Display control: Display Blank: D=E=0
Normal instruction set: H=0
Frame Rate = 73Hz. FR[2:0]=011b
Display Duty = 33 Duty
Display Part = COM0
Booster setting: BE=0, PC[1:0]=01b (Booster Efficiency Level 2, Booster X3)
Bias system: BS[1:0]=[0,0] (1/7 Bias)
After power-on, RAM data are undefined and the Display status is “Blank”. It’s better to initialize whole DDRAM (fill all 00h
or write the display pattern) before turning the Display ON.
Ver 1.0b
21/46
2007/07/12
ST7573
9. INSTRUCTION TABLE
INSTRUCTION
A0
R/W
(/WR)
COMMAND BYTE
D7
D6
D5
D4
D3
D2
D1
D0
DESCRIPTION
H=0 or 1 (Independent of H)
NOP
0
0
0
0
0
0
0
0
0
0
No Operation.
Reset
0
0
0
0
0
0
0
0
0
1
Software Reset
Scan direction (COM/SEG);
Function Set
0
0
0
0
1
MY
XD
PD
V
H
Power mode (ON/OFF);
Addressing mode;
Instruction table selection.
Read Status
0
1
PD
0
D
E
XD
MY
V
MLB
Read Data
1
1
D7
D6
D5
D4
D3
D2
D1
D0
Read DDRAM data.
Write Data
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Write data into DDRAM.
INSTRUCTION
A0
R/W
Read status (setting).
COMMAND BYTE
DESCRIPTION
(/WR)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
1
X
Do NOT use.
0
0
0
0
0
0
0
1
1
0
End Read-Modify-Write
0
0
0
0
0
0
0
1
1
1
Enable Read-Modify-Write
Display Control
0
0
0
0
0
0
1
D
0
E
Set display configuration.
Frame Rate
0
0
0
0
0
1
0
FR2
FR1
FR0
0
0
0
1
0
0
0
Y2
Y1
Y0
0
0
1
0
0
0
X3
X2
X1
X0
0
0
1
0
0
1
X7
X6
X5
X4
Reserved
0
0
0
0
0
0
0
0
1
X
Display Duty
0
0
0
0
0
0
0
1
PS
WS
Booster Control
0
0
0
0
0
0
1
BE
PC1
PC0
Display Part
0
0
0
0
0
1
0
0
DP1
DP0
BIAS System
0
0
0
0
0
1
0
1
BS1
BS0
Set BIAS system.
Set V0
0
0
1
VOP6
VOP5
VOP4
VOP3
VOP2
VOP1
VOP0
Set V0 voltage to register.
0
0
0
1
0
S4
S3
S2
S1
S0
H=0
Reserved
End
read-modify-write
Enable
read-modify-write
Set Y address of
DDRAM
Set X address of
DDRAM (Low)
Set X address of
DDRAM (High)
Frame Rate control
Set DDRAM Y address
(0≤Y≤4)
Set DDRAM X address
Set the high-nibble first and
then low-nibble.
(0≤X≤131)
H=1
Set Start Line
(Vertical-Scroll)
Ver 1.0b
22/46
Do NOT use.
Set display duty
Control booster stages and
booster efficiency.
Set display part for partial
mode
Specify the first scan line in
the DDRAM.
2007/07/12
ST7573
10. INSTRUCTION DESCRIPTION
Function Set
A0
R/W(/WR)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
1
MY
XD
PD
V
H
Flag
Description
Set COM scan direction:
MY
MY=0: Normal direction (COM0->COM31, duty is determined by the “Display Duty” setting);
MY=1: Reverse direction (COM31->COM0, duty is determined by the “Display Duty” setting).
Set DDRAM write direction.
XD
XD=1: Write from X=0 to X=131 (Normal direction);
XD=0: Write from X=131 to X=0 (Reverse direction).
Set the power mode:
PD=0: Chip is active;
PD
PD=1: Chip is in power save mode.
In power save mode, all LCD outputs at VSS, built-in power circuits (Booster, Regulator and Follower) are
turned OFF, Oscillator OFF (external clock is possible), RAM contents is not cleared; RAM data can be
written.
Select Vertical or Horizontal addressing mode.
V
V=0: Horizontal addressing mode;
V=1: Vertical addressing mode.
H
H is used to select the extended instruction set.
Please refer to the instruction table.
Read Status
A0
R/W(/WR)
D7
D6
D5
D4
D3
D2
D1
D0
0
1
PD
0
D
E
XD
MY
V
MLB
Flag
PD
D, E
XD, MY
Description
PD=0: Chip is active;
PD=1: Chip is in power down mode.
D
E
0
0
Display Blank (DDRAM Data is masked out)
Display Mode
0
1
All Segments ON
1
0
Normal mode
1
1
Inverse Display mode
XD
MY
0
0
Only horizontal direction is mirrored.
0
1
Both horizontal and vertical direction is mirrored.
1
0
Normal direction.
1
1
Only vertical direction is mirrored.
Display Mode
Select Vertical or Horizontal addressing mode.
V
V=0: Horizontal addressing mode;
V=1: Vertical addressing mode.
MLB
Ver 1.0b
Data Format. MLB=0: LSB on top; MLB=1: MSB on top.
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ST7573
Read Data
Read the specified 8-bit data in DDRAM to the microprocessor. The location is specified by the X-address and Y-address.
A0
R/W(/WR)
1
1
D7
D6
D5
D4
D3
D2
D1
D0
Read Data
Write Data
8-bit data of Display Data from the microprocessor can be written to the RAM location specified by the column address and
page address. The column address is increased by 1 automatically so that the microprocessor can continuously write data
to the addressed page. During auto-increment, the column address wraps to 0 after the last column is written.
A0
R/W(/WR)
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Read Data
NOP
No operation.
A0
R/W(/WR)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
0
0
Reset
This is the Software RESET instruction. This is same as hardware reset.
A0
R/W(/WR)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
0
1
Ver 1.0b
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ST7573
[ H=0 ]
When Function Set instruction sets H=0, the selected instruction descriptions are as below.
End Read-Modify-Write
This command releases the Read-Modify-Write mode, and returns the column and row address to the address it was at
when the mode was entered.
A0
R/W(/WR)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
1
1
0
Enable Read-Modify-Write
This command is used paired with the ”End Read-Modify-Write” instruction. Once this command has been input, the display
data read command does not change the column and row address, but only the display data write command increments (+1)
the address depend on V register setting. This mode is maintained until the END command is input. When the END
command is input, the address returns to the address it was at when the read/modify/write command was entered. This
function makes it possible to reduce the load on the MPU when there are repeating data changes in a specified display
region, such as when there is a blanking cursor.
A0
R/W(/WR)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
1
1
1
* Even in read/modify/write mode, other commands aside from display data read/write commands can also be used.
Read-Modify-Write
Page Address Set
Column Address Set
Read-Modify-Write Cycle
Dummy Read
Data Read
No
Modify Data
Data Write (at same Address)
Finished?
Yes
Done
Display Control
The bits D and E configure the display mode.
A0
R/W(/WR)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
1
D
0
E
Flag
D, E
Ver 1.0b
Description
D
E
0
0
Display Blank (Segments will always output non-selected waveform)
Display Mode
0
1
All Segments ON
1
0
Normal mode
1
1
Inverse Display mode
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ST7573
Frame Rate
This command is used to select the frame rate.
A0
R/W(/WR)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
1
0
FR2
FR1
FR0
The optional Frame Rates are: (no matter 1/33, 1/17 or 1/9 duty mode, the frame rate will be controlled in the specified
range)
FR2
FR1
FR0
Frame Rate
0
0
0
60 Hz
0
0
1
65 Hz
0
1
0
70 Hz
0
1
1
73 Hz (Default)
1
0
0
76 Hz
1
0
1
80 Hz
1
1
0
85 Hz
1
1
1
90 Hz
Set Y address of DDRAM
Y[2:0] specifies the Y address of the Display Data RAM (DDRAM).
A0
R/W(/WR)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
1
0
0
0
Y2
Y1
Y0
Y2
Y1
Y0
Addressed Page
Allowed X address
0
0
0
Page0
0 ~ 131
D7~D0
0
0
1
Page1
0 ~ 131
D7~D0
0
1
0
Page2
0 ~ 131
D7~D0
0
1
1
Page3
0 ~ 131
D7~D0
1
0
0
Page4
0 ~ 131
D7
Valid bit (MLB= “H”)
Set X address of DDRAM
Specify the X address to point the columns of the Display Data RAM (DDRAM). The valid range is 0~131.
Set X address of DDRAM (Low)
A0
R/W(/WR)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
0
0
0
X3
X2
X1
X0
Set X address of DDRAM (High)
A0
R/W(/WR)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
0
0
1
X7
X6
X5
X4
X7
X6
X5
X4
X3
X2
X1
X0
Column Address
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
0
2
:
:
:
:
:
:
:
:
:
1
0
0
0
0
0
0
1
129
1
0
0
0
0
0
1
0
130
1
0
0
0
0
0
1
1
131
Ver 1.0b
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ST7573
[ H=1 ]
When Function Set instruction sets H=1, the selected instruction descriptions are as below.
Display Duty
This instruction configures the display duty.
A0
R/W(/WR)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
1
PS
WS
Flag
Description
Use PS and WS to select the duty.
PS, WS
PS
WS
0
X
1:33 (32 commons + 1 ICON common)
Display Duty
1
0
1:9 (8 commons + 1 ICON common)
1
1
1:17 (16 commons + 1 ICON common)
Booster Control
This instruction configures the built-in voltage booster.
A0
R/W(/WR)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
1
BE
PC1
PC0
Flag
Description
ST7573 supports software configurable Booster Efficiency. Customers can change the BE and PC[1:0]
according to the LCD panel loading and their power consumption requirement. The higher level provides
higher driving ability while the power consumption is also higher.
BE
BE
Booster Efficiency Level
0
Booster Efficiency Level 2 (Default)
1
Booster Efficiency Level 1
ST7573 supports software selectable Booster Stage. Customers can change the BE[1:0] and PC[1:0]
according to the LCD panel loading and their power consumption requirement. The higher stage generates
higher driving ability while the power consumption is also higher.
PC[1:0]
Ver 1.0b
PC1
PC0
0
1
Booster Stage
Booster X3
1
X
Booster X4
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ST7573
Display Part
This instruction configures the partial display part.
A0
R/W(/WR)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
1
0
0
DP1
DP0
Flag
Description
Use DP[1:0] to select the start common for partial display.
DP[1:0]
DP1
DP0
Start common
Start page
0
0
COM0
Page 0
0
1
COM8
Page 1
1
0
COM16
Page 2
1
1
N/A
*The range of display common depends on the instruction of “Display Partial”. For Example, if Duty=1/17 and DP[1:0]=01,
then display common is COM8 to COM23 and CONS is at page 5.
*The function of partial display is ineffective when Duty=1/33.
BIAS System
ST7573 is built-in a BIAS-voltage generation system for driving the LCD. The bias can be specified by this instruction.
A0
R/W(/WR)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
1
0
1
BS1
BS0
The referential settings of Bias, Duty and V0 are listed below:
LCD voltage
BS1
BS0
BIAS
Recommend Duty
Symbol
Voltage for 1/5 BIAS
0
0
7
1/33
V0
V0
0
1
6
1/33, 1/17
VG
2/5 of V0
1
0
5
1/17, 1/9
VM
1/5 of V0
1
1
4
1/9
VSS
VSS
* Be sure the VG is in operable range:
(1.28V ≤ VG ≤ VDD2-0.2V) in any operation condition.
Ver 1.0b
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ST7573
Set V0
Set V0 voltage level into this register and the built-in voltage regulator will generate the V0.
A0
R/W(/WR)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
VOP6
VOP5
VOP4
VOP3
VOP2
VOP1
VOP0
The V0 voltage can be calculated by this formula:
V0=( a + VOP[6:0] x b ) …………………………………………………………(1)
Figure 19 V0 voltage vs. VOP[6:0] value
The parameters in this formula are controlled by the hardware pin “PM” (Ta=25°C).
H/W Setting
a
b
Unit
PM=”L”
3.0
0.03
V
PM=”H”
4.5
0.03
V
Set Start Line (Vertical-Scroll)
Sets the line address of display RAM to determine the initial display line instruction. The RAM display data is displayed at
the top of row (COM0) of LCD panel.
A0
R/W(/WR)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
1
0
S4
S3
S2
S1
S0
S4
S3
S2
S1
S0
Column address
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
2
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
1
1
1
1
0
30
1
1
1
1
1
31
Ver 1.0b
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ST7573
11. Instruction Sequence
This section introduces some reference instruction flows.
Power ON flow with built-in power circuits:
Figure 20 Initial flow with built-in Power Supply Circuits
POWER SEQUENCE
1.
tV2ON:
Power Sequence
Period between VDD and VDD2 turned ON.
=> 0 ms (min). No maximum value specified.
2.
tRW
RESB
tRSTL
tV2ON
tRSTL:
Reset Low time after VDD is stable.
VDD2
=> 0 ms (min). No maximum value specified.
3.
VDD
tRW:
Reset low pulse width.
Please
refer to RESB
timing specification
(Page30).
Ver 1.0b
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ST7573
Power Saving flow with built-in power circuits
ENTERING THE POWER SAVE MODE
The power save mode is achieved by setting PD bit to be “1”. No specified instruction flow required.
EXITING THE POWER SAVE MODE
Figure 21 Exiting Power Save Mode
INTERNAL SEQUENCE of EXIT POWER SAVE MODE
After receiving the “PD” is “L”, the internal circuits (Power and COM/SEG) will starts the following procedure.
PD=“L”
Data
/WR
Booster
Max: 100ms
tBON
Regulator
Max: 100ms
tRON
Follower
Max: 100ms
tFON
COM,
SEG
Vss
tDON
Min: 160ms
Max: 240ms
Note:
1.
The power stable time is determined by LCD panel loading.
2.
The power stable time in this figure is base on: LCD Panel Size = 1.5” with C1=1uF, C2=1uF.
Ver 1.0b
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Power OFF flow with built-in power circuits
USING PD BIT
By setting PD=”H”, ST7573 will go into power save mode. The LCD driving outputs are all fixed to VSS and the built-in power
circuits are turned OFF. After the built-in power circuits are turned OFF, the power (VDD and VDD2) can be removed.
Instruction Flow
Note:
1.
tIPOFF: Internal Power discharge time. => 250ms (max).
2.
tV2OFF: Period between VDD and VDD2 OFF time. => 50 ms (max).
3.
It is NOT recommended to turn VDD OFF before VDD2. Without VDD, the internal status cannot be guaranteed and
internal discharge-process maybe stopped. The un-discharged power maybe polarizes the liquid crystal in panel.
4.
IC will NOT be damaged if either VDD or VDD2 is OFF while another is ON.
5.
The timing is dependent on panel loading and the external capacitor(s).
6.
The timing in these figures is base on the condition that: LCD Panel Size = 1.5” with C1=1uF, C2=1uF.
7.
Reset Low time after VDD2 is stable.
8.
When turning VDD2 OFF, the falling time should follow the specification:
300ms ≤ tPFall ≤ 1sec
Ver 1.0b
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ST7573
12 Absolutely Maximum Rating
In accordance with the Absolute Maximum Rating values; see notes 1 and 2.
Parameter
Symbol
Conditions
Unit
Digital Power Supply Voltage
VDD
-0.3 ~ 3.6
V
Analog Power supply voltage
VDD2
-0.3 ~ 3.6
V
V0-XV0
-0.3 ~ 9.5
V
VG, VM
-0.3 ~ VDD2+0.3
V
VIN
-0.3 ~ VDD+0.3
V
LCD Driver Power supply voltage
Input voltage
Operating temperature
TOPR
-30 to +85
°C
Storage temperature
TSTR
-65 to +150
°C
Figure 22 Voltage Range
Notes
1.
2.
Stresses over the Absolutely Maximum Rating may cause permanent damage to the device.
Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS
unless otherwise specified.
3.
Make sure the voltage of the following pins follows the relation list below:
V0 ≥ VDD2 ≥ VG ≥ VM ≥ VSS ≥ XV0
Ver 1.0b
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13. HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling MOS devices (see “Handling MOS devices”).
14. DC CHARACTERISTICS
Unless otherwise specified, VSS = 0V; Tamb = -30°C to +85°C.
Power
Item
Symbol
Condition
Rating
Min.
Typ.
Max.
Unit
Operation Voltage (1)
VDD
2.4
—
3.6
V
Operating Voltage (2)
VDD2
2.4
—
3.6
V
V0-XV0
Vop
3.0
—
9.0
V
Internal VG Output
VGO
1.28
VIHC
0.7 x VDD
High-level Input Voltage
VDD2
VDD
V
VILC
VSS
—
0.3 x VDD
V
High-level Output Voltage
VOHC
IOUT=-1mA; VDD=2.4V
0.8 x VDD
—
VDD
V
Low-level Output Voltage
VOLC
IOUT=1mA; VDD=2.4V
VSS
—
0.2 x VDD
V
Input leakage current
ILI
-1.0
—
1.0
µA
Output leakage current
ILO
-3.0
—
3.0
µA
—
0.8
—
Resistance
Frame Rate
Ver 1.0b
RON
FR
Ta = 25°C
V0 = 6.0 V
∆V=10%
VG = 2.4 V
—
0.8
—
FR[2:0]=011b, Ta = 25°C
69
73
77
34/46
Pin
V0, XV0
VGO
—
Low-level Input Voltage
Liquid Crystal Driver ON
Applicable
KΩ
COMn
SEGn
Hz
2007/07/12
ST7573
Dynamic Current Consumption: During Display, with Internal Power Supply ON, current consumed by whole chip (bare die)
Test pattern
Display Pattern
SNOW
Power Down
Symbol
ISS
Condition
Rating
Typ.
Max.
—
85
—
µA
—
0.5
10
µA
VDD = VDD2 = 2.8V, Frame Rate = 73 Hz;
Booster X4; V0 = 6.9 V; Bias=1/7; 1/33 Duty
ISS
Units
Min.
VDD = VDD2 = 2.8V, Ta = 25°C
Notes
Notes to the DC characteristics
1.
The maximum V0 voltage may be generated will be limited by VDD2 , temperature and panel loading.
2.
Power Down: During power down mode, all static currents are switched off.
Ver 1.0b
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ST7573
15. TIMING CHARACTERISTICS
System Bus Read/Write Characteristics (For the 8080 Series MPU)
Figure 23
VDD = 2.4~3.3V
Item
Address setup time
Signal
Symbol
Condition
Rating
Min.
tAW8
15
tAH8
10
System cycle time
tCYC8
150
/WR low pulse width
tCCLW
80
tCCHW
70
tCCLR
243
tCCHR
70
Address hold time
/WR high pulse width
/RD low pulse width
/RD high pulse width
A0
/WR
/RD
WRITE Data setup time
tDS8
30
WRITE Data hold time
tDH8
35
tACC8
30
READ access time
READ output disable time
D0 ~ D7
Typ.
tOH8
Max.
Units
ns
243
70
*1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast,
(tr + tf) ≦ (tCYC8 – tCCLW – tCCHW) for (tr + tf) ≦ (tCYC8 – tCCLR – tCCHR) are specified.
*2 All timing is specified using 20% and 80% of VDD as the reference.
*3 tCCLW and tCCLR are specified as the overlap between CSB being “L” and WR and RD being at the “L” level.
Ver 1.0b
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ST7573
System Bus Read/Write Characteristics (For the 6800 Series MPU)
VDD = 2.4~3.3V
Item
Address setup time
Address hold time
Signal
A0
System cycle time
Enable L pulse width (WRITE)
Enable H pulse width (WRITE)
Enable L pulse width (READ)
Enable H pulse width (READ)
E/RD
E/RD
WRITE Data setup time
WRITE Data hold time
READ access time
READ output disable time
D0 ~ D7
Symbol
Condition
Rating
Min.
tAW6
45
tAH6
10
tCYC6
130
tEWLW
50
tEWHW
80
tEWLR
245
tEWHR
40
tDS6
45
tDH6
45
tACC6
15
Typ.
tOH6
Max.
Units
ns
245
45
*1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast,
(tr + tf) ≦ (tCYC6 – tEWLW – tEWHW) for (tr + tf) ≦ (tCYC6 – tEWLR – tEWHR) are specified.
*2 All timing is specified using 20% and 80% of VDD as the reference.
*3 tEWLW and tEWLR are specified as the overlap between CSB being “L” and E.
Ver 1.0b
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ST7573
Serial Interface (4-Line Interface)
VDD = 2.4~3.3V
Item
Signal
Serial Clock Period
SCL “H” pulse width
SCL
SCL “L” pulse width
Address setup time
Address hold time
Data setup time
Data hold time
CS-SCL time
CS-SCL time
A0
SI
CSB
Symbol
Condition
Rating
Min.
tSCYC
330
tSHW
165
tSLW
165
tSAS
10
tSAH
60
tSDS
10
tSDH
40
tCSS
10
tCSH
110
Typ.
Max.
Units
ns
*1 The input signal rise and fall time (tr, tf) are specified at 15 ns or less.
*2 All timing is specified using 20% and 80% of VDD as the standard.
Ver 1.0b
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ST7573
Serial Interface (3-Line Interface)
VDD = 2.4~3.3V
Item
Signal
Serial Clock Period
SCL “H” pulse width
Data hold time
CS-SCL time
CS-SCL time
Condition
tSCYC
SCL
SCL “L” pulse width
Data setup time
Symbol
SI
CSB
Rating
Min.
Typ.
Max.
Units
330
tSHW
165
tSLW
165
tSDS
20
tSDH
30
tCSS
10
tCSH
120
ns
*1 The input signal rise and fall time (tr, tf) are specified at 15 ns or less.
*2 All timing is specified using 20% and 80% of VDD as the standard.
Ver 1.0b
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ST7573
Reset Timing
VDD = 2.4~3.3V
Item
Signal
Reset time
Reset “L” pulse width
Ver 1.0b
Symbol
Condition
Rating
Min.
tR
RESB
Typ.
Max.
2.0
tRW
2.0
40/46
Units
µs
µs
2007/07/12
ST7573
16. APPLICATION NOTE
Selection of Application Voltage
Power Range Summary
Positive Booster: (VDD2 x PCn x BE) ≥ V0 or (VDD2 x PCn x BE) ≥ Vop;
Negative Booster: [-VDD2 x (PCn - 1) x BE] ≤ XV0 or [VDD2 x (PCn -1) x BE] ≥ (Vop-VG),
Vop requirement: [VDD2 x (PCn - 1) x BE] ≥ [Vop x (N-2) / N] or Vop ≤ VDD2 x (PCn -1) x BE x N / (N-2).
where VG = Vop x 2 / N;
PCn is the booster stage and BE is the booster efficiency. Referential values are listed below: (assume VDD2=2.8V)
Module Size ≤ 1.5”: BE=76% (min when Booster X4);
Actual BE should be determined by module loading and ITO resistance value.
1.28 ≤ VG ≤ VDD2-0.2V. Recommend VG is: VDD2-VG around 0.5~0.8V.
VM=VG/2 and 0.64V ≤ VM < VDD2.
The worse condition should be considered:
Low temperature effect and display on with snow pattern on panel (max: 1.8”).
According to the Duty Size, the Recommend BIAS, Vop Range and Booster are listed below:
VDD2=2.8V
Duty
33
17
9
Recommend BIAS
Recommend Vop Range
Recommend Booster
1/6
5.5 ~ 6.5
X4
1/7
6.5 ~ 7.5
X4
1/5
4.5 ~ 5.5
X3, X4
1/6
5.5 ~ 6.5
X4
1/4
3.5 ~ 4.5
X3, X4
The V0 range Tables are base on: LCD Panel Size = 1.5” with C1=1uF, C2=1uF.
The actual V0 range depends on the Panel Size, Temperature Effect and Display Pattern.
Ver 1.0b
41/46
2007/07/12
ST7573
ITO Layout Reference (for Power)
V0O
VDD
FPC
PIN
FPC
PIN
V0S
V0I
VDD2
Digital / Analog Power ITO Layout (Using Single Power)
Power Circuit Input, Output and Sensor ITO Layout
(for V0, XV0 and VG ITO layout)
IC Side
ITO
FPC
CAP
Note:
1.
Total resistance value of VSS should be smaller than
RO
“VDD//VDD2”.
V0O
2.
RI
V0S
The relationship among input, output and sensor ITO
(for V0, XV0 and VG) resistance value is RS > RO > RI .
3.
RS
V0I
XV0
Recommend ITO resistance value:
RI ≤ 150 Ohm; RO ≤ 200 Ohm; RS ≤ 250 Ohm.
Equivalent Circuit
Ver 1.0b
42/46
2007/07/12
ST7573
MPU Interface
Intel 8080 series MPU Interface (8-bit):
32
COM0 ~ COM31
P1.7 to P1.0
8
P3.0
P3.1
P3.2
P3.3
A0
/RW
/RD
CSB
Intel 8051 Serial
D7 to D0
COMS
SEG0 ~
SEG131
1
132
ST7573
Motorola 6800 series MPU Interface (8-bit):
32
COM0 ~ COM31
P1.0 to P1.7
P3.0
P3.1
P3.2
P3.3
Intel 8051 Serial
8
DB0 to DB7 COMS
A0
R/W
E
CSB
SEG0 ~
SEG131
1
132
ST7573
Serial 4-Line SPI Mode:
32
COM0 ~ COM31
P1.6
SDA
P1.7
SCL
P3.0
P3.3
RS
CSB
COMS
SEG0 ~ SEG131
Intel 8051 Serial
1
132
ST7573
Serial 3-Line SPI Mode:
COM0 ~ COM31
P1.6
SDA
P1.7
SCL
P3.0
P3.3
RS
CSB
COMS
SEG0 ~ SEG131
Intel 8051 Serial
32
1
132
ST7573
Note:
The Microprocessor Interface pins should not be left floating under any operation mode.
Ver 1.0b
43/46
2007/07/12
D1
D0
E
R/W
A0
2007/07/12
CSB
RESB
D7
SEG4
SEG3
SEG2
SEG1
SEG0
Reserve
Reserve
COMS1
COM16
COM17
COM18
D6
D5
D4
D3
D2
D1
D0
/RD
/WR
A0
CSB
RESB
COM29
COM30
COM31
V0O
V0O
V0S
V0I
V0I
V0I
V0I
XV0I
XV0I
XV0I
XV0I
XV0S
XV0O
XV0O
T1
T2
T3
T4
T0
T5
T6
T7
T8
T9
D7
D6
D5
D4
D3
D2
D1
D0
ERD
RWR
A0
CSB
OSC
RESB
VRS
VDD
VDD
VDD
VDD
VDD2
VDD2
VDD2
VDD2
SEG4
SEG3
SEG2
SEG1
SEG0
Reserve
Reserve
COMS1
COM16
COM17
COM18
COM29
COM30
COM31
ST7573
D2
VG
VSS
TP2
D3
VDD2
C2
D4
T9
D7
D6
D5
D4
D3
D2
D1
D0
ERD
RWR
A0
CSB
OSC
RESB
VRS
VDD
VDD
VDD
VDD
VDD2
VDD2
VDD2
VDD2
VDD
TP1
TP2
D5
V0O
V0O
V0S
V0I
V0I
V0I
V0I
XV0I
XV0I
XV0I
XV0I
XV0S
XV0O
XV0O
T1
T2
T3
T4
T0
T5
T6
T7
T8
Reserve
(Default NC)
C2
Reserve
(Default NC)
D6
VGI
VGI
VGI
VGI
VGS
VGO
VGO
VSS
VSS
VSS
C1
TP1
D7
COM1
COM0
SEG131
SEG130
SEG129
SEG128
SEG127
8080 Interface
C1
VG
VSS
Reserve
Reserve
Reserve
COMS2
COM15
COM14
Application Circuits
COM1
COM0
SEG131
SEG130
SEG129
SEG128
SEG127
Clock: Internal
Data Format: MSB Upper
V0 Range: Higher range
Reverse
Reverse
Reverse
Reverse
Reverse
Reverse
Reverse
Reverse
Reverse
Reverse
Reverse
Reverse
PS0
PS1
PS2
MLB
T11
PM
T10
VDD
VDD
VDD
VDD2
VDD2
VDD2
VM
VM
VM
OSC=“H
MLB=“H
PM=“H
T0~T8=Open
T9=”L
T10=”H
T11=”H
44/46
VDD
VDD2
VDD2
VDD
VDD
VDD
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
VGI
VGI
VGI
VGI
VGS
VGO
VGO
VSS
VSS
VSS
VDD2
ITO
8080 Interface
FPC
PS2=“L
PS1=“H
PS0=“L
C1=0.1~1uF
C2=0.1~1uF
System
Clock: Internal
Data Format: LSB Upper
V0 Range: Lower range
Reverse
Reverse
Reverse
Reverse
Reverse
Reverse
Reverse
Reverse
Reverse
Reverse
Reverse
Reverse
PS0
PS1
PS2
MLB
T11
PM
T10
VDD
VDD
VDD
VDD2
VDD2
VDD2
VM
VM
VM
OSC=“H
MLB=“L
PM=“L
T0~T8=Open
T9=”L
T10=”H
T11=”H
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
Reserve
Reserve
Reserve
COMS2
COM15
COM14
6800 Interface
VDD2
VDD2
VDD
VDD
VDD
6800 Interface
ITO
PS2=“H
PS1=“H
PS0=“L
C1=0.1~1uF
C2=0.1~1uF
System
Ver 1.0b
FPC
V0O
V0O
V0S
V0I
V0I
V0I
V0I
XV0I
XV0I
XV0I
XV0I
XV0S
XV0O
XV0O
T1
T2
T3
T4
T0
T5
T6
T7
T8
VG
VSS
C2
TP2
SEG4
SEG3
SEG2
SEG1
SEG0
Reserve
Reserve
COMS1
COM16
COM17
COM18
Reserve
(Default NC)
TP2
T9
D7
D6
D5
D4
D3
D2
D1
D0
ERD
RWR
A0
CSB
OSC
RESB
VRS
VDD
VDD
VDD
VDD
VDD2
VDD2
VDD2
VDD2
VDD
VDD2
SDA
SCLK
A0
CSB
RESB
COM29
COM30
COM31
T9
D7
D6
D5
D4
D3
D2
D1
D0
ERD
RWR
A0
CSB
OSC
RESB
VRS
VDD
VDD
VDD
VDD
VDD2
VDD2
VDD2
VDD2
COM1
COM0
SEG131
SEG130
SEG129
SEG128
SEG127
SEG4
SEG3
SEG2
SEG1
SEG0
Reserve
Reserve
COMS1
COM16
COM17
COM18
COM29
COM30
COM31
ST7573
V0O
V0O
V0S
V0I
V0I
V0I
V0I
XV0I
XV0I
XV0I
XV0I
XV0S
XV0O
XV0O
T1
T2
T3
T4
T0
T5
T6
T7
T8
Reserve
Reserve
Reserve
COMS2
COM15
COM14
Serial 4-Line SPI
VGI
VGI
VGI
VGI
VGS
VGO
VGO
VSS
VSS
VSS
Clock: Internal
Data Format: MSB Upper
V0 Range: Lower range
VGI
VGI
VGI
VGI
VGS
VGO
VGO
VSS
VSS
VSS
OSC=“H
MLB=“H
PM=“L
T0~T8=Open
T9=”L
T10=”H
T11=”H
COM1
COM0
SEG131
SEG130
SEG129
SEG128
SEG127
Serial SPI-4
VDD2
VDD2
VDD
VDD
VDD
Reverse
Reverse
Reverse
Reverse
Reverse
Reverse
Reverse
Reverse
Reverse
Reverse
Reverse
Reverse
PS0
PS1
PS2
MLB
T11
PM
T10
VDD
VDD
VDD
VDD2
VDD2
VDD2
VM
VM
VM
TP1
C2
2007/07/12
CSB
RESB
ITO
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
C1
TP1
Reserve
(Default NC)
SDA
SCLK
FPC
PS2=“L
PS1=“L
PS0=“L
C1=0.1~1uF
C2=0.1~1uF
C1
VG
VSS
System
VDD
VDD2
Clock: Internal
Data Format: LSB Upper
V0 Range: Higher range
Reverse
Reverse
Reverse
Reverse
Reverse
Reverse
Reverse
Reverse
Reverse
Reverse
Reverse
Reverse
PS0
PS1
PS2
MLB
T11
PM
T10
VDD
VDD
VDD
VDD2
VDD2
VDD2
VM
VM
VM
OSC=“H
MLB=“L
PM=“H
T0~T8=Open
T9=”L
T10=”H
T11=”H
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
Reserve
Reserve
Reserve
COMS2
COM15
COM14
Serial 3-Line SPI
VDD2
VDD2
VDD
VDD
VDD
Serial SPI-3
ITO
PS2=“H
PS1=“L
PS0=“L
C1=0.1~1uF
C2=0.1~1uF
System
Recommend short noisy nets by FPC (refer to Page 41, ITO Layout).
45/46
The Microprocessor Interface pins should not be left floating under any operation mode.
Notes for all applications:
Ver 1.0b
FPC
ST7573
Reversion History
Version
0.0
0.1
0.1a
0.1b
1.0
1.0a
Description
Initial version
Modify Chip Thickness, PAD arrangement and PAD number (Page2)
Modify Pin count and Pin description of Test Pin (Page9~Page10)
Modify the I/O pin resistance limitation of T[0:11] (Page10)
Modify the Application circuit (Page49~Page51)
Modify Fig24 and Fig25 (Page32)
Modify Driver Output Circuits (Page 1)
Modify Chip Size (Page 2)
Modify description of PD (Page 25)
Modify description of Frame Rate (Page28)
Modify instruction of Display Part (Page 30)
Modify Fig24 and Fig25 (Page 32)
Modify test condition (Page 36)
Modify pin description (Page 8)
Modify application circuit. (Page 50~Page 51)
Modify Voltage regulation temperature gradient (Page 1)
Reserve X2 Booster function
Reserve I2C Interface
Modify DC field
Update reference timing.
Modify Fig2 and Fig 3
Modify the recommend BIAS, Vop rang and booster according to different duty size.
Define the relationship among Power Circuit Output, Input and Sensor ITO resistance
Date
2006/08/04
2006/08/15
2006/12/27
2007/02/01
2007/0312
2007/05/02
value.
1.0b
Ver 1.0b
Modify timing specification.
Modify Fig 12
Modify application circuit.
2007/07/12
46/46
2007/07/12