SSM2312GN N-channel Enhancement-mode Power MOSFET Low gate-charge D Simple drive requirement Fast switching G Pb-free; RoHS compliant. BV DSS 20V R DS(ON) 50mΩ ID 4.3A S DESCRIPTION D The SSM2312GN is in a SOT-23-3 package, which is widely used for lower power commercial and industrial surface mount applications. This device is suitable for low-voltage applications such as DC/DC converters and and general switching applications. S SOT-23-3 G ABSOLUTE MAXIMUM RATINGS Parameter Symbol VDS Drain-Source Voltage VGS Gate-Source Voltage ID @ TA=25°C ID @ TA=70°C Rating Units 20 V ± 12 V Continuous Drain Current 3 4.3 A Continuous Drain Current 3 3.4 A 1,2 IDM Pulsed Drain Current 10 A PD @ TA=25°C Total Power Dissipation 1.38 W Linear Derating Factor 0.01 W/°C TSTG Storage Temperature Range -55 to 150 °C TJ Operating Junction Temperature Range -55 to 150 °C THERMAL DATA Symbol RΘJA 4/16/2005 Rev.2.1 Parameter Maximum Thermal Resistance, Junction-ambient 3 www.SiliconStandard.com Value Unit 90 °C/W 1 of 5 SSM2312GN ELECTRICAL CHARACTERISTICS (at Tj = 25°C unless otherwise specified) Symbol Parameter Test Conditions Min. Typ. Max. Units 20 - - V BVDSS Drain-Source Breakdown Voltage ∆ BV DSS/∆Tj Breakdown Voltage Temperature Coefficient Reference to 25°C, ID=1mA - 0.02 - V/°C RDS(ON) Static Drain-Source On-Resistance VGS=10V, ID=5A - - 36 mΩ VGS=4.5V, ID=4A - - 50 mΩ VGS=2.5V, ID=3A - - 75 mΩ 0.5 - 1.2 V VGS(th) Gate Threshold Voltage gfs Forward Transconductance IDSS VDS=VGS, ID=250uA VDS=5V, ID=4A - 16 - S o VDS=20V, VGS=0V - - 1 uA o Drain-Source Leakage Current (Tj=70 C) VDS=16V ,VGS=0V - - 10 uA Gate-Source Leakage VGS=±12V - - ±100 nA ID=4A - 5 8 nC Drain-Source Leakage Current (Tj=25 C) IGSS VGS=0V, ID=250uA 2 Qg Total Gate Charge Qgs Gate-Source Charge VDS=16V - 1 - nC Qgd Gate-Drain ("Miller") Charge VGS=4.5V - 2.3 - nC VDS=15V - 8 - ns 2 td(on) Turn-on Delay Time tr Rise Time ID=1A - 9 - ns td(off) Turn-off Delay Time RG=3.3Ω , VGS=5V - 11 - ns tf Fall Time RD=15Ω - 2 - ns Ciss Input Capacitance VGS=0V - 360 580 pF Coss Output Capacitance VDS=20V - 75 - pF Crss Reverse Transfer Capacitance f=1.0MHz - 60 - pF Rg Gate Resistance f=1.0MHz - 1.5 - Ω Min. Typ. Source-Drain Diode Symbol Parameter 2 Test Conditions Max. Units VSD Forward On Voltage IS=1.2A, VGS=0V - - 1.2 V trr Reverse Recovery Time IS=4A, VGS=0V, - 16 - ns Qrr Reverse Recovery Charge dI/dt=100A/µs - 8 - nC Notes: 1.Pulse width limited by maximum junction temperature. 2.Pulse width <300us, duty cycle <2%. 3.Surface-mounted on 1 in2 copper pad on FR4 board , t <10sec ; 270°C/W when mounted on minimum copper pad. 4/16/2005 Rev.2.1 www.SiliconStandard.com 2 of 5 SSM2312GN 12 12 8 ID , Drain Current (A) T A =25 o C ID , Drain Current (A) T A = 150 o C 5.0V 4.5V 3.5V 2.5V 4 5.0V 4.5V 3.5V 2.5V 8 4 V G =2.5V V G =2.5V 0 0 0 1 2 0 3 2 3 V DS , Drain-to-Source Voltage (V) V DS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 70 1.6 I D =3A ID=4A V G =5V 1.4 o Normalized R DS(ON) T A =25 C 60 RDS(ON) (mΩ ) 1 50 1.2 1.0 40 0.8 0.6 30 0 2 4 6 8 -50 10 50 100 150 Fig 4. Normalized On-Resistance vs. Junction Temperature 4.0 1.8 3.0 1.4 Normalized VGS(th) (V) IS(A) Fig 3. On-Resistance vs. Gate Voltage T j =150 o C 0 T j , Junction Temperature ( o C) V GS , Gate-to-Source Voltage (V) T j =25 o C 2.0 1.0 1.0 0.6 0.0 0.2 0 0.2 0.4 0.6 0.8 1 1.2 -50 0 50 100 150 o V SD , Source-to-Drain Voltage (V) Fig 5. Forward Characteristic of Reverse Diode 4/16/2005 Rev.2.1 T j , Junction Temperature ( C) Fig 6. Gate Threshold Voltage vs. Junction Temperature www.SiliconStandard.com 3 of 5 SSM2312GN f=1.0MHz 1000 12 VGS , Gate to Source Voltage (V) I D =4A 10 C iss 8 C (pF) V DS =10V V DS =12V V DS =16V 6 100 C oss C rss 4 2 0 10 0 2 4 6 8 10 1 5 9 13 17 21 25 V DS , Drain-to-Source Voltage (V) Q G , Total Gate Charge (nC) Fig 7. Gate Charge Characteristics Fig 8. Typical Capacitance Characteristics 100 1 ID (A) 10 Normalized Thermal Response (Rthja) Duty factor=0.5 100us 1ms 1 10ms 100ms T A =25 o C Single Pulse 0.1 1s DC 0.01 0.2 0.1 0.1 0.05 PDM t 0.01 T 0.01 Single Pulse Duty factor = t/T Peak Tj = PDM x Rthja + Ta Rthja = 270°C/W 0.001 0.1 1 10 100 0.0001 0.001 0.01 Fig 9. Maximum Safe Operating Area 0.1 1 10 100 1000 t , Pulse Width (s) V DS , Drain-to-Source Voltage (V) Fig 10. Effective Transient Thermal Impedance VG VDS 90% QG 4.5V QGS QGD 10% VGS td(on) tr td(off) tf Fig 11. Switching Time Circuit 4/16/2005 Rev.2.1 Charge Q Fig 12. Gate Charge Circuit www.SiliconStandard.com 4 of 5 SSM2312GN Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. 4/16/2005 Rev.2.1 www.SiliconStandard.com 5 of 5