SSM4226M/GM
DUAL N-CHANNEL ENHANCEMENT-MODE POWER MOSFET
Low on-resistance
Simple drive requirement
D2
D2
D1
D1
High VGS rating
S1
30V
R DS(ON)
18mΩ
8.2A
ID
G2
S2
SO-8
BVDSS
G1
Description
D2
D1
Advanced Power MOSFETs from Silicon Standard provide the
designer with the best combination of fast switching,
ruggedized device design, ultra low on-resistance and
cost-effectiveness.
G2
G1
S2
S1
This device is available with Pb-free lead finish (second-level interconnect) as SSM4226GM.
Absolute Maximum Ratings
Symbol
Parameter
VDS
Drain-Source Voltage
VGS
Gate-Source Voltage
ID @ TA=25°C
ID @ TA=70°C
Rating
Units
30
V
± 20
V
Continuous Drain Current
3
8.2
A
Continuous Drain Current
3
6.7
A
30
A
1
IDM
Pulsed Drain Current
PD @ TA=25°C
Total Power Dissipation
2
W
Linear Derating Factor
0.016
W/°C
TSTG
Storage Temperature Range
-55 to 150
°C
TJ
Operating Junction Temperature Range
-55 to 150
°C
Thermal Data
Symbol
Rthj-a
8/06/2004 Rev.1.02
Parameter
Thermal Resistance Junction-ambient
3
Max.
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Value
Unit
62.5
°C/W
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SSM4226M/GM
Electrical Characteristics @ Tj=25oC (unless otherwise specified)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max. Units
30
-
-
V
BVDSS
Drain-Source Breakdown Voltage
∆ B VDSS/∆ Tj
Breakdown Voltage Temperature Coefficient Reference to 25°C, ID=1mA
-
0.03
-
V/°C
RDS(ON)
Static Drain-Source On-Resistance 2
VGS=10V, ID=6A
-
-
18
mΩ
VGS=4.5V, ID=4A
-
-
28
mΩ
VDS=VGS, ID=250uA
1
-
3
V
VGS(th)
Gate Threshold Voltage
gfs
Forward Transconductance
IDSS
VDS=10V, ID=6A
-
15
-
S
o
VDS=30V, VGS=0V
-
-
1
uA
o
Drain-Source Leakage Current (Tj=70 C)
VDS=24V ,VGS=0V
-
-
25
uA
Gate-Source Leakage
VGS= ± 20V
-
-
±100
nA
ID=8A
-
20
30
nC
Drain-Source Leakage Current (Tj=25 C)
IGSS
VGS=0V, ID=250uA
2
Qg
Total Gate Charge
Qgs
Gate-Source Charge
VDS=24V
-
5
-
nC
Qgd
Gate-Drain ("Miller") Charge
VGS=4.5V
-
12
-
nC
VDS=15V
-
12
-
ns
-
8
-
ns
2
td(on)
Turn-on Delay Time
tr
Rise Time
ID=1A
td(off)
Turn-off Delay Time
RG=3.3Ω ,VGS=10V
-
31
tf
Fall Time
RD=15Ω
-
12
Ciss
Input Capacitance
VGS=0V
-
1450 2320
pF
Coss
Output Capacitance
VDS=25V
-
320
-
pF
Crss
Reverse Transfer Capacitance
f=1.0MHz
-
230
-
pF
Min.
Typ.
IS=1.7A, VGS=0V
-
-
1.2
V
-
ns
ns
Source-Drain Diode
Symbol
Parameter
2
Test Conditions
Max. Units
VSD
Forward On Voltage
trr
Reverse Recovery Time
IS=8A, VGS=0V,
-
27
-
ns
Qrr
Reverse Recovery Charge
dI/dt=100A/µs
-
18
-
nC
Notes:
1.Pulse width limited by Max. junction temperature.
2.Pulse width <300us , duty cycle <2%.
3.Surface mounted on 1 in2 copper pad of FR4 board ; 135°C/Wwhen mounted on Min. copper pad.
8/06/2004 Rev.1.02
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SSM4226M/GM
35
35
10V
T A =25 o C
5.0V
5.0V
28
ID , Drain Current (A)
ID , Drain Current (A)
28
10V
T A =150 o C
4.0V
21
14
4.0V
21
14
V G =3.0V
7
7
V G =3.0V
0
0
0
1
1
2
2
0
3
1
V DS , Drain-to-Source Voltage (V)
1
2
2
3
V DS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
80
1.8
I D =6.0A
T A =25°C
I D =6A
V GS =10V
1.6
Normalized RDS(ON)
RDS(ON) (mΩ )
60
40
1.4
1.2
1
20
0.8
0
0.6
2
4
6
8
10
12
-50
0
50
100
150
V GS , Gate-to-Source Voltage (V)
T j , Junction Temperature ( o C)
Fig 3. On-Resistance vs. Gate Voltage
Fig 4. Normalized On-Resistance
vs. Junction Temperature
2.50
10
2.25
T j =25 o C
T j =150 o C
1
VGS(th) (V)
IS(A)
2.00
1.75
1.50
1.25
0.1
1.00
0
0.4
0.8
1.2
1.6
-50
0
V SD ,Source-to-Drain Voltage (V)
Fig 5. Forward Characteristic of
100
T j , Junction Temperature (
150
o
C)
Fig 6. Gate Threshold Voltage
Reverse Diode
8/06/2004 Rev.1.02
50
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vs. Junction Temperature
3 of 4
SSM4226M/GM
f=1.0MHz
10000
16
V DS =15V
V DS =20V
V DS =24V
12
Ciss
1000
C (pF)
VGS , Gate to Source Voltage (V)
I D =8A
8
Coss
Crss
100
4
0
10
0
10
20
30
40
50
1
5
9
13
17
21
25
29
V DS , Drain-to-Source Voltage (V)
Q G , Total Gate Charge (nC)
Fig 7. Gate Charge Characteristics
Fig 8. Typical Capacitance Characteristics
100
1
Normalized Thermal Response (R thja)
Duty factor=0.5
100us
10
ID (A)
1ms
10ms
1
100ms
1s
0.1
T c =25 o C
Single Pulse
DC
0.01
0.2
0.1
0.1
0.05
0.02
PDM
0.01
t
0.01
T
Single Pulse
Duty factor = t/T
Peak Tj = PDM x Rthja + Ta
Rthja = 135℃
℃ /W
0.001
0.1
1
10
100
0.0001
0.001
0.01
V DS (V)
0.1
1
10
100
1000
t , Pulse Width (s)
Fig 9. Maximum Safe Operating Area
Fig 10. Effective Transient Thermal Impedance
VG
VDS
90%
QG
4.5V
QGS
QGD
10%
VGS
td(on) tr
td(off) tf
Charge
Fig 11. Switching Time Waveform
Q
Fig 12. Gate Charge Waveform
Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no
guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no
responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its
use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including
without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to
the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of
Silicon Standard Corporation or any third parties.
8/06/2004 Rev.1.02
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