TRIQUINT AGR18125EF

Product Brief
AGR18125E
125 W, 1.805 GHz—1.880 GHz, LDMOS RF Power Transistor
Introduction
Table 1. Thermal Characteristics
The AGR18125E is a 125 W, 26 V, N-channel goldmetallized, laterally diffused metal oxide semiconductor (LDMOS) RF power field effect transistor
(FET) suitable for global system for mobile communication (GSM), enhanced data for global evolution
(EDGE), and multicarrier class AB power amplifier
applications. This device is manufactured using
advanced LDMOS technology offering state-of-theart performance and reliability. It is packaged in an
industry-standard package and is capable of delivering a minimum output power of 125 W which makes
it ideally suited for today’s RF power amplifier applications.
)
5B 03 STYLE 1
AGR18125EU (unflanged)
AGR18125EF (flanged)
Figure 1. Available Packages
Features
Typical performance ratings for GSM EDGE
(f = 1.840 GHz, POUT = 50 W)
— Modulation spectrum:
@ ± 400 kHz = –60 dBc.
@ ± 600 kHz = –72 dBc.
Typical performance over entire digital communication system (DCS) band:
— P1dB: 125 W typical (typ).
— Power gain: @ P1dB = 13.5 dB.
— Efficiency: @ P1dB = 50% typ.
— Return loss: –10 dB.
High-reliability, gold-metallization process.
Low hot carrier injection (HCI) induced bias drift
over 20 years.
Internally matched.
High gain, efficiency, and linearity.
Integrated ESD protection.
125 W minimum output power.
Device can withstand 10:1 voltage standing wave
ratio (VSWR) at 28 Vdc, 1.840 GHz, 125 W continuous wave (CW) output power.
Large signal impedance parameters available.
Parameter
Thermal Resistance,
Junction to Case:
AGR18125EU
AGR18125EF
Sym
Value
Unit
Rı JC
Rı JC
0.5
0.5
°C/W
°C/W
Table 2. Absolute Maximum Ratings*
Parameter
Drain-source Voltage
Gate-source Voltage
Total Dissipation at TC = 25 °C:
AGR18125EU
AGR18125EF
Derate Above 25 °C:
AGR18125EU
AGR18125EF
Operating Junction Temperature
Storage Temperature Range
Sym Value Unit
VDSS
65
Vdc
VGS –0.5, 15 Vdc
PD
PD
350
350
W
W
—
—
TJ
2.0
2.0
200
W/°C
W/°C
°C
TSTG –65, 150
°C
* Stresses in excess of the absolute maximum ratings can cause
permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at
these or any other conditions in excess of those given in the
operational sections of the data sheet. Exposure to absolute
maximum ratings for extended periods can adversely affect
device reliability.
Table 3. ESD Rating*
AGR18125E
HBM
MM
CDM
Minimum (V)
500
50
1500
Class
1B
A
4
* Although electrostatic discharge (ESD) protection circuitry has
been designed into this device, proper precautions must be
taken to avoid exposure to ESD and electrical overstress (EOS)
during all handling, assembly, and test operations. PEAK
Agere Devices
employs a human-body model (HBM), a machine model (MM),
and a charged-device model (CDM) qualification requirement in
order to determine ESD-susceptibility limits and protection
design evaluation. ESD voltage thresholds are dependent on the
circuit parameters used in each of the models, as defined by
JEDEC's JESD22-A114B (HBM), JESD22-A115A (MM), and
JESD22-C101A (CDM) standards.
Caution: MOS devices are susceptible to damage from electrostatic charge. Reasonable precautions in handling and packaging MOS devices should be
observed.
Agere Systems - Proprietary
AGR18125E
125 W, 1.805 GHz—1.880 GHz, LDMOS RF Power Transistor
Product Brief
Electrical Characteristics
Recommended operating conditions apply unless otherwise specified: TC = 30 °C.
Table 4. dc Characteristics
Parameter
Symbol
Min
Typ
Max
Off Characteristics
200 µA)
Drain-source Breakdown Voltage (VGS = 0, ID = 400
V(BR)DSS
65
—
—
Zero Gate Voltage Drain Leakage Current (VDS = 26 V, VGS = 0 V)
IDSS
—
Gate-source Leakage Current (VGS = 5 V, VDS = 0 V)
IGSS
—
Unit
Vdc
—
—
4
200
12
µAdc
9
—
S
µAdc
On Characteristics
Forward Transconductance (VDS = 10 V, ID = 1 A)
GFS
—
VGS(Q)
—
Gate Threshold Voltage (VDS = 10 V, ID = 400 µA)
VGS(TH)
Drain-source On-voltage (VGS = 10 V, ID = 1 A)
VDS(ON)
Gate Quiescent Voltage (VDS = 26 V, ID = 1200 mA)
—
—
4.8
Vdc
—
0.08
—
Vdc
Min
Typ
Max
Unit
CRSS
—
3.0
—
pF
COSS
—
48
—
pF
3.8
—
Vdc
Table 5. RF Characteristics
Parameter
Symbol
Dynamic Characteristics
Drain-to-gate Capacitance
(VDS = 26 V, VGS = 0 V, f = 1 MHz)
Drain-to-source Capacitance
(VDS = 26 V, VGS = 0 V, f = 1 MHz)
Test Fixture)
Functional Tests* (in Supplied
Agere Systems
Supplied Test Fixture)
Power Gain
(VDS = 26 V, POUT = 125 W, IDQ = 1200 mA)
Drain Efficiency
(VDS = 26 V, POUT = 125 W, IDQ = 1200 mA)
GL
—
13.5
—
dB
η
—
50
—
%
—
–60
—
dBc
—
125
—
W
EDGE Linearity Characterization
(POUT = 50 W, f = 1.840 GHz, VDS = 26 V, IDQ = 1200 mA)
Modulation spectrum @ ± 400 kHz
Modulation spectrum @ ± 600 kHz
Output Power
(VDS = 26 V, 1 dB gain compression, IDQ = 1200 mA)
Input VSWR
Ruggedness
(VDS = 26 V, POUT = 30 W, IDQ = 1200 mA,
VSWR = 10:1 [all angles])
* Across full DCS band, 1.805 GHz—1.880 GHz.
P1dB
VSWRI
ψ
—
—
–72
—
—
2:1
No degradation in output
power.
dBc
Product Brief
AGR18125E
125 W, 1.805 GHz—1.880 GHz, LDMOS RF Power Transistor
Test Circuit Illustrations for AGR18125E
+
C19 C20 C21
+
C26
Z1
FB1
R3
VGG
Z2
RF INPUT
C14
R2
Z4
C13
Z5
C27
C28
Z24
+
Z3
C1
C12
Z6
C11
Z7
C10
Z8
C9
Z9
C8
Z13
Z22
Z20
R1
Z10
Z21
Z19
C3
C2
Z12
2
1
3
C4
Z14
DUT
C5
C23
C18
C24
C25
Z23
C17
RF OUTPUT
Z18
Z17
C16
R4
Z11
C22
VDD
Z16
C15
Z15
PINS:
1. DRAIN
2. GATE
3. SOURCE
A. Schematic
Parts List:
®
■ Murata chip
capacitor:
C12, C24: 0.01 µF
GRM40X7R103K100AL.
■ 0603 chip
capacitor:
C10, C22: 220 pF.
®
■ Sprague tantalum
chip capacitor:
C14, C15, C26:
22 µF, 35 V.
®
■ Kreger
ferrite bead:
FB1 2743D19447.
®
■ Kemet chip capacitor:
C13, C25 0.10 µF
C1206C104KRAC7800.
®
■ Vitramon chip
capacitor:
C11, C23: 2200 pF,
VJ1206Y222KXA.
®
■ Taconic ORCER RF35: board material, 1 oz.
copper, 30 mil thickness,
εr = 3.5.
■
■
■
Microstrip line: Z1 0.243 in. x 0.066 in.; Z2 0.050 in. x 0.066 in.; Z3 0.321 in. x 0.050 in.; Z4 0.047 in. x 0.066 in.; Z5 0.067 in. x 0.066 in.;
Z6 0.123 in. x 0.066 in.; Z7 0.050 in. x 0.066 in.; Z8 0.381 in. x 0.066 in.; Z9 0.896 in. x 0.150 in.; Z10 0.050 in. x 0.600 in.;
Z11 0.540 in. x 0.600 in.; Z12 0.050 in. x 0.600 in.; Z13 1.024 in. x 0.050 in.; Z14 0.093 in. x 0.500 in.; Z15 0.050 in. x 0.500 in.;
Z16 0.242 in. x 0.500 in.; Z17 0.050 in. x 0.500 in.; Z18 0.198 in. x 0.500 in.; Z19 0.446 x 0.100; Z20 0.095 in. x 0.066 in.;
Z21 0.050 in. x 0.066 in.; Z22 0.419 in. x 0.066 in.; Z23 0.745 in. x 0.066 in.; Z24 2.048 in. x 0.050 in.
ATC® chip capacitor: C5: 4.7 pF 100B4R7BW; C4, C18 3.9 pF 100B3R9BW; C6, C7: 12 pF 100B120JW; C16, C17: 9.1 pF 100B9R1BW;
C9, C21: 10 pF 100B100JW; C2: 47 pF 100A470JW; C3, C8, C19, C20: 47 pF 100B470JW; C1: 8.2 pF 100A8R2BW.
1206 size, 0.25 W, fixed film, chip resistors: R1 50 Ω, RM73B2B500J; R2 47 kΩ RM73B2B473J; R3 1 kΩ RM73B2B103J;
R4 10 Ω RM73B2B100J.
B. Component Layout
Figure 2. AGR18125E Test Circuit
AGR18125E
125 W, 1.805 GHz—1.880 GHz, LDMOS RF Power Transistor
Product Brief
U CT
8
0.6
90
IN D
0.
10
0.1
0.4
20
50
20
10
5.0
4.0
3.0
2.0
1.8
1.6
1.4
1.2
50
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.2
)
/ Yo
(-jB
CE
1.
0
AN
PT
CE
US
ES
0
1.
0
1.2
1.0
0
-4
5
-4
0.15
0.14
-80
0.35
0.9
-70
0.36
-110
0
6
4
0.11
-100
-90
0.13
0
-12
0.1
IN
-70
40
-1
Z
X/
,O
o)
R
-75
06
(-j
5
0.
07
30
-1
43
0.
8
0.0
2
0.4
9
0.0
1
0.4
0.4
0.39
0.38
F
0.37
0.12
CE
CO
M
T
0.
2.
1.8
1.6
1.4
0.7
0.1
0.3
-5
35
0.8
3
-60
5
7
VE
-5
0.1
0.3
CA P
AC
I TI
-60
-30
32
RE
AC
TA
N
0.6
18
0.
0.2
EN
-65
0
-5
-25
0.
PO
N
0.
0.4
31
0.
19
0.
4
0
4
0.
0.6
0
3.
-20
DU
IV
CT
0.8
5
4.0
0.0
-15
5
0.4
8
0.4
2
0.2
0.2
0.3
f1
ZS
0.2
f3
-4
4
0.
0.2
9
0.3
1
-30
4
0.0
0
-15 -80
8
0.
5.0
0.2
-10
-85
0.6
0.2
6
10
0.48
0.4
ZL
-20
D L OA D <
OW A R
7
HST
0.4
N GT
-170
EL E
V
WA
<Ð
-90
-160
f3
0.1
0.2
f1
20
Ð
RESISTANCE COMPONENT (R/Zo), OR CONDUCTANCE COMPONENT (G/Yo)
50
0.49
0.25
0.2
6
0.24
0.27
0.23
0.25
0.24
0.26
0.23
0.27
REFL ECTI ON COEFFI CI EN T I N D EG
REES
L E OF
ANG
I SSI ON COEFFI CI EN T I N
TRA N SM
D EGR
EES
L E OF
ANG
Z0 = 6 Ω
0.0 Ð > W A V EL E
N GTH
S TOW
A RD
0.0
0.49
0.48
± 180
170
Typical Performance Characteristics
MHz (f)
865 (f1)
880 (f2)
895 (f3)
ZL Ω
ZS Ω
(Complex Source Impedance) (Complex Optimum Load Impedance)
0.980 – j2.93
2.54 + j0.868
0.865 – j2.90
2.58 + j0.819
0.710 – j2.81
2.60 + j0.765
GATE (2)
ZS
DRAIN (1)
ZL
SOURCE (3)
INPUT MATCH
DUT
OUTPUT MATCH
Figure 3. Series Equivalent Input and Output Impedances
Product Brief
AGR18125E
125 W, 1.805 GHz—1.880 GHz, LDMOS RF Power Transistor
Typical Performance Characteristics (continued)
Figure 4. Power Gain vs. POUT
Figure 5. Modulation Spectrum vs. POUT
Figure 6. Efficiency vs. POUT
Figure 7. Modulation Spectrum, Gain, and Efficiency vs. Frequency
Figure 8. Power Gain and Return Loss vs. Frequency
Figure 9. POUT and Efficiency vs. PIN
AGR18125E
125 W, 1.805 GHz—1.880 GHz, LDMOS RF Power Transistor
Product Brief
Package Dimensions
All dimensions are in inches. Tolerances are ±0.005 in. unless specified.
AGR18125EU
PINS:
1. DRAIN
2. GATE
3. SOURCE
1
A
M-AGR21125U
YYWWUR
ZZZZZZZ
PEAK DEVICES
AGR18125XU
YYWWLL XXXXX
ZZZZZZZ
1
3
3
2
2
AGR18125EF
1
PEAK DEVICES
AGR18125XF
YYWWLL XXXXX
ZZZZZZZ
M-AGR21125F
YYWWUR
ZZZZZZZ
PINS:
1. DRAIN
2. GATE
3. SOURCE
1
3
2
3
2
Label Notes:
■ M before the part number denotes model program. X before the part number denotes engineering prototype.
■
■
■
■
The last two letters of the part number denote wafer technology and package type.
YYWWLL is the date code including place of manufacture: year year work week (YYWW), LL = location (AL = Allentown, PA; T = Thailand).
XXXXX = five-digit wafer lot number.
ZZZZZZZ = seven-digit assembly lot number on production parts.
ZZZZZZZZZZZZ = 12-digit (five-digit lot, two-digit wafer, and five-digit serial number) on models and engineering prototypes.