SMMS690B − AUGUST 1997 − REVISED FEBRUARY 1998
D Organization:
D
D
D
D
D
D
D
D Read Latencies 2 and 3 Supported
D Support Burst-Interleave and
− TM8SK64JPU . . . 8 388 608 x 64 Bits
Single 3.3-V Power Supply
(±10% Tolerance)
Designed for 66-MHz 4-Clock Systems
JEDEC 144-Pin Small Outline Dual-In-Line
Memory Module (SODIMM) Without Buffer
for Use With Socket
Uses Eight 64M-Bit Synchronous Dynamic
RAMs (SDRAMs) (8M × 8-Bit) in Plastic Thin
Small-Outline Packages (TSOPs)
Byte-Read/Write Capability
Performance Ranges:
High-Speed, Low-Noise Low-Voltage TTL
(LVTTL) Interface
’8SK64JPU-10
SYNCHRONOUS
CLOCK CYCLE
TIME
tCK3
tCK2
ACCESS TIME
CLOCK TO
OUTPUT
tAC3
tAC2
10 ns
8 ns
15 ns
9 ns
Burst-Interrupt Operations
D Burst Length Programmable to
D
D
D
D
D
1, 2, 4, and 8
Four Banks for On-Chip Interleaving
(Gapless Access)
Ambient Temperature Range
0°C to 70°C
Gold-Plated Contacts
Pipeline Architecture
Serial Presence Detect (SPD) Using
EEPROM
REFRESH
INTERVAL
tREF
64 ms
description
The TM8SK64JPU is a 64M-byte, 144-pin SODIMM. The SODIMM is composed of eight TMS664814DGE,
8 388 608 x 8-bit SDRAMs, each in a 400-mil, 54-pin plastic thin small-outline package (TSOP) mounted on a
substrate with decoupling capacitors. See the TMS664814 data sheet (literature number SMOS690).
operation
The TM8SK64JPU operates as eight TMS664814DGE devices that are connected as shown in the
TM8SK64JPU functional block diagram.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1998, Texas Instruments Incorporated
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POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
1
SMMS690B − AUGUST 1997 − REVISED FEBRUARY 1998
DUAL-IN-LINE MEMORY MODULE
( TOP VIEW )
TM8SK64JPU
( SIDE VIEW )
PIN NOMENCLATURE
A[0:11]
A[0:8]
A13/BA0
A12/BA1
CAS
CKE[0:1]
CK[0:3]
DQ[0:63]
DQMB[0:7]
1
NC
RAS
S0
SCL
SDA
VDD
VSS
WE
59
61
143
2
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
Row Address Inputs
Column Address Inputs
Bank-Select Zero
Bank-Select One
Column-Address Strobe
Clock Enable
System Clock
Data-In / Data Out
Data-In/Data-Out
Mask Enable
No Connect
Row-Address Strobe
Chip-Select
SPD Clock
SPD Address / Data
3.3-V Supply
Ground
Write Enable
SMMS690B − AUGUST 1997 − REVISED FEBRUARY 1998
Pin Assignments
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
PIN
PIN
NAME
NO.
NAME
NO.
NO.
1
37
DQ8
73
2
VSS
VSS
38
DQ40
3
DQ0
39
DQ9
4
DQ32
40
DQ41
5
DQ1
41
6
DQ33
42
7
DQ2
8
DQ34
9
PIN
NAME
NO.
PIN
NAME
NC
109
A9
74
CK1
110
A12/BA1
75
111
A10
76
VSS
VSS
112
A11
DQ10
77
NC
113
DQ42
78
NC
114
VDD
VDD
43
DQ11
79
NC
115
DQMB2
44
DQ43
80
NC
116
DQMB6
DQ3
45
81
DQMB3
DQ35
46
82
VDD
VDD
117
10
VDD
VDD
118
DQMB7
11
47
DQ12
83
DQ16
119
12
VDD
VDD
48
DQ44
84
DQ48
120
VSS
VSS
13
DQ4
49
DQ13
85
DQ17
121
DQ24
14
DQ36
50
DQ45
86
DQ49
122
DQ56
15
DQ5
51
DQ14
87
DQ18
123
DQ25
16
DQ37
52
DQ46
88
DQ50
124
DQ57
17
DQ6
53
DQ15
89
DQ19
125
DQ26
18
DQ38
54
DQ47
90
DQ51
126
DQ58
19
DQ7
55
91
DQ27
DQ39
56
92
VSS
VSS
127
20
VSS
VSS
128
DQ59
21
57
NC
93
DQ20
129
22
VSS
VSS
58
NC
94
DQ52
130
VDD
VDD
23
DQMB0
59
NC
95
DQ21
131
DQ28
24
DQMB4
60
NC
96
DQ53
132
DQ60
25
DQMB1
61
CK0
97
DQ22
133
DQ29
26
DQMB5
62
CKE0
98
DQ54
134
DQ61
27
63
DQ23
135
DQ30
64
VDD
VDD
99
28
VDD
VDD
100
DQ55
136
DQ62
29
A0
65
RAS
101
137
DQ31
30
A3
66
CAS
102
VDD
VDD
138
DQ63
31
A1
67
WE
103
A6
139
32
A4
68
NC
104
A7
140
VSS
VSS
33
A2
69
S0
105
A8
141
SDA
34
A5
70
NC
106
A13/BA0
142
SCL
35
VSS
VSS
71
NC
107
143
72
NC
108
VSS
VSS
VDD
VDD
36
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
144
3
SMMS690B − AUGUST 1997 − REVISED FEBRUARY 1998
small-outline dual-in-line memory module and components
The small-outline dual-in-line memory module and components include:
D PC substrate: 1,10 ± 0,1 mm (0.04 inch) nominal thickness
D Bypass capacitors: Multilayer ceramic
D Contact area: Nickel plate and gold plate over copper
functional block diagram
S0
RC
CS
CK: U0, UB0
CS
RC
CK0
CK: U1, UB1
DQMB0
U0
DQM
R
DQ[0:7]
8
DQMB4
DQM
R
DQ[0:7]
DQ[32:39]
8
RC
UB0
CK: U2, UB2
RC
CK1
DQ[0:7]
CK: U3, UB3
RC
CK2
CS
C
CS
RC
CK3
DQMB1
U1
DQM
R
DQ[8:15]
8
DQMB5
DQ[0:7]
UB1
DQM
R
DQ[40:47]
8
CS
C
DQ[0:7]
R = 10 Ω
RC = 10 Ω
C = 10 pF
CS
VDD
DQMB2
U2
DQM
R
DQ[16:23]
8
DQMB6
R
DQ[0:7]
DQ[48:55]
8
U[0:3], UB[0:3]
Two 0.22 µF and
one 0.01 µF per
SDRAM
U[0:3], UB[0:3]
UB2
DQM
DQ[0:7]
VSS
CS
DQMB3
DQ[24:31]
RAS
CAS
WE
CKE0
A[0:13]
CS
U3
DQM
R
8
DQMB7
DQ[0:7]
DQ[56:63]
8
DQ[0:7]
SPD EEPROM
RAS: SDRAM U[0:3], UB[0:3]
CAS: SDRAM U[0:3], UB[0:3]
WE: SDRAM U[0:3], UB[0:3]
CKE: SDRAM U[0:3], UB[0:3]
A[0:13]: SDRAM U[0:3], UB[0:3]
LEGEND: CS =
SPD =
4
UB3
DQM
R
POST OFFICE BOX 1443
SCL
SDA
A0
A1
VSS
Chip select
Serial Presence Detect
• HOUSTON, TEXAS 77251−1443
A2
SMMS690B − AUGUST 1997 − REVISED FEBRUARY 1998
absolute maximum ratings over ambient temperature range (unless otherwise noted)†
Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.5 V to 4.6 V
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 W
Ambient temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 55°C to 125°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
recommended operating conditions
MIN
NOM
MAX
UNIT
3
3.3
3.6
V
VDD
VSS
Supply voltage
VIH
VIH-SPD
High-level input voltage
2
High-level input voltage for SPD device
2
VIL
TA
Low-level input voltage
Supply voltage
0
Ambient temperature
V
VDD + 0.3
5.5
V
V
−0.3
0.8
V
0
70
°C
capacitance over recommended ranges of supply voltage and ambient temperature,
f = 1 MHz (see Note 2)‡
TM8SK64JPU
PARAMETER
MIN
MAX
UNIT
Ci(CK)
Input capacitance, CK input
5
pF
Ci(AC)
Input capacitance, address and control inputs: A0 −A13, RAS, CAS, WE
5
pF
Ci(CKE)
Input capacitance, CKE input
5
pF
Co
Output capacitance
7
pF
Ci(DQMBx)
Input capacitance, DQMBx input
5
pF
Ci(Sx)
Input capacitance, Sx input
5
pF
Ci/o(SDA)
Input/output capacitance, SDA input
9
pF
7
pF
Ci(SPD)
Input capacitance, SPD inputs (except SDA)
‡ Specifications in this table represent a single SDRAM device.
NOTE 2: VDD = 3.3 V ± 0.3 V. Bias on pins under test is 0 V.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
5
SMMS690B − AUGUST 1997 − REVISED FEBRUARY 1998
electrical characteristics over recommended ranges of supply voltage and ambient temperature
(unless otherwise noted) (see Note 3)†
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
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’8SK64JPU-10
PARAMETER
VOH
VOL
TEST CONDITIONS
High-level output voltage
IOH = − 2 mA
IOL = 2 mA
Low-level output voltage
µA
"10
µA
CAS latency = 2
105
mA
CAS latency = 3
135
mA
CKE ≤ VIL MAX, tCK = 15 ns (see Note 7)
2
mA
CKE and CK ≤ VIL MAX, tCK = ∞ (see Note 8)
2
mA
CKE ≥ VIH MIN, tCK = 15 ns (see Note 7)
40
mA
tCK = infinite (see Note 8)
CKE ≤ VIL MAX, tCK = 15 ns (see Notes 4 and 7)
3
mA
15
mA
CKE and CK ≤ VIL MAX, tCK = ∞
(see Notes 4 and 8)
15
mA
CKE ≥ VIH MIN, tCK = 15 ns (see Notes 4 and 7)
70
mA
CKE ≥ VIH MIN, CK ≤ VIL MAX, tCK = ∞
(see Notes 4 and 8)
20
mA
Page burst, IOH/IOL = 0 mA CAS latency = 2
All banks activated,
nCCD = one cycle
CAS latency = 3
(see Notes 9 and 10)
130
mA
185
mA
CAS latency = 2
1 65
mA
CAS latency = 3
1 95
mA
IO
Output current (leakage)
0 V < VO < VDD +0.3 V,
Output disabled
Operating current
Burst length = 1,
tRC ≥ tRC MIN
IOH/IOL = 0 mA,
(see Notes 4, 5, and 6)
ICC2N
ICC2NS
Precharge standby current in non-power-down
mode
ICC3P
ICC3PS
Active standby current in power-down mode
ICC3N
ICC3NS
ICC4
ICC5
Active standby current in non-power-down mode
Burst current
Auto-refresh current
V
"10
Input current (leakage)
Precharge standby current in power-down mode
2.4
UNIT
V
II
ICC2P
ICC2PS
MAX
0.4
0 V < VI < VDD + 0.3 V,
All other pins = 0 V to VDD
ICC1
MIN
tRC ≤ tRC MIN
(see Notes 5 and 8)
ICC6
Self-refresh current
CKE ≤ VIL MAX
2
mA
† Specifications in this table represent a single SDRAM device.
NOTES: 3. All specifications apply to the device after power-up initialization. All control and address inputs must be stable and valid.
4. Only one bank is activated.
5. tRC ≥ MIN
6. Control and address inputs change state twice during tRC.
7. Control and address inputs change state once every 30 ns.
8. Control and address inputs do not change state (stable).
9. Control and address inputs change once every cycle.
10. Continuous burst access, nCCD = 1 cycle
6
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
SMMS690B − AUGUST 1997 − REVISED FEBRUARY 1998
ac timing requirements†‡
’8SK64JPU-10
MIN
MAX
UNIT
tCK2
tCK3
Cycle time, CK
CAS latency = 2
15
ns
Cycle time, CK
CAS latency = 3
10
ns
tCH
tCL
Pulse duration, CK high
3
ns
tAC2
tAC3
Access time, CK high to data out (see Note 11)
CAS latency = 2
9
ns
Access time, CK high to data out (see Note 11)
CAS latency = 3
8
ns
tOH
tLZ
Hold time, CK high to data out
3
ns
Delay time, CK high to DQ in low−impedance state (see Note 12)
1
ns
tHZ
tIS
Delay time, CK high to DQ in high−impedance state (see Note 13)
tIH
tCESP
Hold time, address, control, and data input
Power down/self−refresh exit time
10
tRAS
tRC
Delay time, ACTV command to DEAC or DCAB command
50
Delay time, ACTV, MRS, REFR, or SLFR to ACTV, MRS, REFR, or SLFR command
80
ns
tRCD
tRP
Delay time ACTV command to READ, READ−P, WRT, or WRT−P command (see Note 14)
30
ns
Delay time, DEAC or DCAB command to ACTV, MRS, REFR, or SLFR command
30
ns
tRRD
tRSA
Delay time, ACTV command in one bank to ACTV command in the other bank
20
ns
Delay time, MRS command to ACTV, MRS, REFR, or SLFR command
20
ns
tAPR
tAPW
Final data out of READ−P operation to ACTV, MRS, SLFR, or REFR command
Pulse duraction, CK low
3
Setup time, address, control, and data input
Final data in of WRT−P operation to ACTV, MRS, SLFR, or REFR command
ns
8
ns
3
ns
1
ns
ns
100000
tRP − (CL−1)* tCK
tRP + 1 tCK
ns
ns
ns
tWR
Delay time, final data in of WRT operation to DEAC or DCAB command
10
ns
tT
Transition time
1
5
ms
† All references are made to the rising transition of CK unless otherwise noted.
‡ Specifications in this table represent a single SDRAM device.
NOTES: 11. tAC is referenced from the rising transition of CK that precedes the data-out cycle. For example, the first data out tAC is referenced
from the rising transition of CK that is read latency (one cycle after the READ command). Access time is measured at output
reference level 1.4 V.
12. tLZ is measured from the rising transition of CK that is read latency (one cycle after the READ command).
13. tHZ (max) defines the time at which the outputs are no longer driven and is not referenced to output voltage levels.
14. For read or write operations with automatic deactivate, tRCD must be set to satisfy minimum tRAS.
POST OFFICE BOX 1443
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7
SMMS690B − AUGUST 1997 − REVISED FEBRUARY 1998
clock timing requirements†
’8SK64JPU-10
MIN
MAX
64
UNIT‡
tREF
nCCD
Refresh interval
Delay time, READ or WRT command to an interrupting command
1
nCDD
nCLE
Delay time, CS low or high to input enabled or inhibited
0
Delay time, CKE high or low to CLK enabled or disabled
1
nCWL
nDID
Delay time, final data in of WRT operation to READ, READ-P, WRT, or WRT-P
1
Delay time, ENBL or MASK command to enabled or masked data in
0
0
cycles
nDOD
Delay time, ENBL or MASK command to enabled or masked data out
2
2
cycles
nHZP2
Delay time, DEAC or DCAB, command to DQ in
high−impedance state
2
cycles
nHZP3
Delay time, DEAC or DCAB, command to DQ in
high−impedance state
3
cycles
CAS latency = 2
CAS latency = 3
ms
cycles
cycles
1
cycles
cycles
nWCD Delay time, WRT command to first data in
0
0 cycles
† All references are made to the rising transition of CK unless otherwise noted.
‡ A CK cycle can be considered as contributing to a timing requirement for those parameters defined in cycle units only when not gated by CKE
(those CK cycles occurring during the time when CKE is asserted low).
8
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SMMS690B − AUGUST 1997 − REVISED FEBRUARY 1998
serial presence detect
The serial presence detect (SPD) is contained in a 2K-bit serial EEPROM located on the module. The SPD
nonvolatile EEPROM contains various data such as module configuration, SDRAM organization, and timing
parameters (see Table 1). Only the first 128 bytes are programmed by Texas Instruments, while the remaining
128 bytes are available for customer use. Programming is done through an IIC bus using the clock (SCL) and
data (SDA) signals. All Texas Instruments modules comply with the current JEDEC SPD standards. See the
Texas Instruments Serial Presence Detect Technical Reference (literature number SMMU001) for further
details. Table 1 lists SPD contents as follows:
Table 1. Serial Presence Detect Data
TM8SK64JPU-10
BYTE
NO.
DESCRIPTION OF FUNCTION
ITEM
DATA
0
Defines number of bytes written into serial memory during module manufacturing
128 bytes
80h
1
Total number of bytes of SPD memory device
256 bytes
08h
2
Fundamental memory type (FPM, EDO, SDRAM, . . .)
SDRAM
04h
3
Number of row addresses on this assembly
12
0Ch
4
Number of column addresses on this assembly
9
09h
5
Number of module banks on this assembly
1 bank
01h
6
Data width of this assembly
64 bits
40h
7
Data width continuation
8
Voltage interface standard of this assembly
00h
LVTTL
01h
9
SDRAM cycle time at maximum supported CAS latency (CL), CL = X
SDRAM access from clock at CL = X
tCK = 10 ns
tAC =8 ns
A0h
10
11
SODIMM configuration type (non-parity, parity, error correcting code [ECC])
Non-Parity
00h
12
Refresh rate / type
15.6 µs/
self-refresh
80h
13
SDRAM width, primary DRAM
x8
08h
14
Error-checking SDRAM data width
N/A
00h
15
Minimum clock delay, back-to-back random column addresses
16
Burst lengths supported
17
Number of banks on each SDRAM device
18
CAS latencies supported
19
CS latency
20
Write latency
21
SDRAM module attributes
22
SDRAM device attributes: general
23
Minimum clock cycle time at CL = X − 1
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80h
1 CK cycle
01h
1, 2, 4, and 8
0Fh
4 banks
04h
2, 3
06h
0
01h
0
01h
Non-buffered/
Non-registered
00h
VDD tolerance =
("10%)
Burst read / write,
precharge all,
auto precharge
0Eh
tCK = 15 ns
F0h
9
SMMS690B − AUGUST 1997 − REVISED FEBRUARY 1998
serial presence detect (continued)
Table 1. Serial Presence Detect Data (Continued)
TM8SK64JPU-10
BYTE
NO.
DESCRIPTION OF FUNCTION
DATA
tAC = 9 ns
N/A
90h
N/A
00h
tRP = 30 ns
tRRD = 20 ns
tRCD = 30 ns
1Eh
tRAS =50 ns
64M Bytes
32h
30h
24
Maximum data-access time from clock at CL = X − 1
25
Minimum clock cycle time at CL = X − 2
26
Maximum data-access time from clock at CL = X − 2
27
Minimum row precharge time
28
Minimum row-active to row-active delay
29
Minimum RAS-to-CAS delay
30
Minimum RAS pulse width
31
Density of each bank on module
32
Command and address signal input setup time
33
Command and address signal input hold time
34
Data signal input setup time
tIS = 3 ns
tIH = 1 ns
tIS = 3 ns
35
Data signal input hold time
tIH = 1 ns
10h
Rev. 2
02h
36 −61
00h
14h
1Eh
10h
10h
30h
Superset features (may be used in the future)
62
SPD revision
63
Checksum for byte 0 −62
73
49h
Manufacturer’s JEDEC ID code per JEP −106E
Manufacturing location†
97
9700...00h
64 −71
72
TBD
Manufacturer’s part number†
Die revision code†
TBD
TBD
93 −94
PCB revision code†
Manufacturing date†
95 −98
Assembly serial number†
TBD
73 −90
91
92
TBD
TBD
Manufacturer specific data†
126 −127 Vendor specific data†
99 −125
128−166
167−255
TBD
TBD
System integrator’s specific data‡
Open
TBD
† TBD indicates values are determined at manufacturing time and are module dependent.
‡ These TBD values are determined and programmed by the customer (optional).
10
ITEM
POST OFFICE BOX 1443
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SMMS690B − AUGUST 1997 − REVISED FEBRUARY 1998
device symbolization (TM8SK64JPU)
TM8SK64JPU
-SS
YY
MM
T
-SS
=
=
=
=
YYMMT
Year Code
Month Code
Assembly Site Code
Speed Code
NOTE A: Location of symbolization may vary.
POST OFFICE BOX 1443
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11
SMMS690B − AUGUST 1997 − REVISED FEBRUARY 1998
MECHANICAL DATA
BDQ (R-SODIMM-N144)
SMALL OUTLINE DUAL IN-LINE MEMORY MODULE
2.665 (67,69)
2.655 (67,44)
Notch 0.157 (4,00) x 0.079 (2,00) Deep
2 Places
0.024 (0,61) TYP
0.044 (1,12)
0.036 (0,91)
Notch 0.060 (1,52) x 0.158 (4,01) Deep
0.031 (0,79)
0.010 (0,25) MAX
0.788 (20,00) TYP
0.098 (2,49)
1.130 (28,70)
1.120 (28,45)
0.196 (4,98)
0.157 (4,00)
0.126 (3,20)
0.095 (2,41) MAX
0.150 (3,81) MAX
(For Double-Sided Module Only)
4088188/A 07/97
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MO-190
12
POST OFFICE BOX 1443
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