SMMS704 − MAY 1998
D Organization: 16 777 216 x 64 Bits
D Single 3.3-V Power Supply
D Read Latencies 2 and 3 Supported
D Support Burst-Interleave and
(±10% Tolerance)
Burst-Interrupt Operations
D
D
D
D
D Burst Length Programmable to
D
Memory Module (SODIMM) Without Buffer
for Use With Socket
Uses Sixteen 64M-Bit Synchronous
Dynamic RAMs (SDRAMs) (8M × 8-Bit)
Memory Chips Assembled in
Board-On-Chip/Ball-Grid-Array
(BOC/BGAt) Packages.
Byte-Read/Write Capability
High-Speed, Low-Noise, Low-Voltage TTL
(LVTTL) Interface
Performance Ranges:
SYNCHRONOUS
CLOCK CYCLE
TIME
tCK3
tCK2
TM16SM64JBN−10
10 ns
15 ns
ACCESS TIME
CLOCK TO
OUTPUT
tAC3
tAC2
7.5 ns
D
D
D
D
1, 2, 4, and 8
Four Banks for On-Chip Interleaving
(Gapless Access)
Ambient Temperature Range
0°C to 70°C
Gold-Plated Contacts
Pipeline Architecture
Serial Presence Detect (SPD) Using
EEPROM
REFRESH
INTERVAL
7.5 ns
tREF
64 ms
description
The TM16SM64JBN is a 64M-byte, 144-pin SODIMM. The SODIMM is composed of sixteen TMS664814DGE,
8 388 608 x 8-bit SDRAMs, two per board-on-chip/ball-grid-array (BOC/BGA) package mounted on a substrate
with decoupling capacitors. See the TMS664814 data sheet (literature number SMOS695).
operation
The TM16SM64JBN operates as sixteen TMS664814DGE devices that are connected as shown in the
TM16SM64JBN functional block diagram.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
BOC/BGA is a trademark of Texas Instruments Incorporated.
Copyright 1998, Texas Instruments Incorporated
!"#$%! &!&'"( )"!*+&%( %,' !"#$%-' !"
*'(. ),$(' ! *'-'/!)#'%0 ,$"$&%'"(%& *$%$ $* !%,'"
()'&&$%!( $"' *'(. .!$/(0 '1$( (%"+#'%( "'('"-'( %,' ".,% %!
&,$.' !" *(&!%+' %,'(' )"!*+&%( 2%,!+% !%&'0
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1
PRODUCT PREVIEW
D Designed for 66-MHz Systems
D JEDEC 144-Pin Small Outline Dual-In-Line
SMMS704 − MAY 1998
DUAL-IN-LINE MEMORY MODULE
( TOP VIEW )
TM16SM64JBN
( SIDE VIEW )
A[0:11]
A[0:8]
A13/BA0
A12/BA1
CAS
CKE[0:1]
CK[0:3]
DQ[0:63]
DQMB[0:7]
1
NC
RAS
S[0:1]
SCL
SDA
VDD
VSS
WE
59
PRODUCT PREVIEW
PIN NOMENCLATURE
61
143
2
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Row-Address Inputs
Column-Address Inputs
Bank-Select Zero
Bank-Select One
Column-Address Strobe
Clock Enable
System Clock
Data-In / Data Out
Data-In/Data-Out
Mask Enable
No Connect
Row-Address Strobe
Chip-Select
SPD Clock
SPD Address / Data
3.3-V Supply
Ground
Write Enable
SMMS704 − MAY 1998
Pin Assignments
PIN
NAME
NAME
NO.
NO.
1
37
DQ8
73
2
VSS
VSS
38
DQ40
3
DQ0
39
DQ9
4
DQ32
40
DQ41
5
DQ1
41
6
DQ33
42
7
DQ2
8
DQ34
9
PIN
NAME
NO.
PIN
NAME
NC
109
A9
74
CK1
110
A12/BA1
75
111
A10
76
VSS
VSS
112
A11
DQ10
77
NC
113
DQ42
78
NC
114
VDD
VDD
43
DQ11
79
NC
115
DQMB2
44
DQ43
80
NC
116
DQMB6
DQ3
45
81
DQMB3
DQ35
46
82
VDD
VDD
117
10
VDD
VDD
118
DQMB7
11
47
DQ12
83
DQ16
119
12
VDD
VDD
48
DQ44
84
DQ48
120
VSS
VSS
13
DQ4
49
DQ13
85
DQ17
121
DQ24
14
DQ36
50
DQ45
86
DQ49
122
DQ56
15
DQ5
51
DQ14
87
DQ18
123
DQ25
16
DQ37
52
DQ46
88
DQ50
124
DQ57
17
DQ6
53
DQ15
89
DQ19
125
DQ26
18
DQ38
54
DQ47
90
DQ51
126
DQ58
19
DQ7
55
91
DQ27
DQ39
56
92
VSS
VSS
127
20
VSS
VSS
128
DQ59
21
57
NC
93
DQ20
129
22
VSS
VSS
58
NC
94
DQ52
130
VDD
VDD
23
DQMB0
59
NC
95
DQ21
131
DQ28
24
DQMB4
60
NC
96
DQ53
132
DQ60
25
DQMB1
61
CK0
97
DQ22
133
DQ29
26
DQMB5
62
CKE0
98
DQ54
134
DQ61
27
63
DQ23
135
DQ30
64
VDD
VDD
99
28
VDD
VDD
100
DQ55
136
DQ62
29
A0
65
RAS
101
137
DQ31
30
A3
66
CAS
102
VDD
VDD
138
DQ63
31
A1
67
WE
103
A6
139
32
A4
68
CEK1
104
A7
140
VSS
VSS
33
A2
69
S0
105
A8
141
SDA
34
A5
70
NC
106
A13/BA0
142
SCL
35
VSS
VSS
71
S1
107
143
72
NC
108
VSS
VSS
VDD
VDD
36
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144
PRODUCT PREVIEW
PIN
NO.
3
SMMS704 − MAY 1998
small-outline dual-in-line memory module and components
The small-outline dual-in-line memory module and components include:
D PC substrate: 1,10 ± 0,1 mm (0.04 inch) nominal thickness
D Bypass capacitors: Multilayer ceramic
D Contact area: Nickel plate and gold plate over copper
functional block diagram
S1
S0
DQMB0
DQMB4
CS
DQM
DQ[0:7]
R
DQM
U0
8
CS
U4
DQ[0:7]
DQ[0:7]
DQ[32:39]
PRODUCT PREVIEW
DQMB1
R 8
CS
DQM
UB0
CS
UB4
DQ[0:7]
DQ[0:7]
DQMB5
DQM
R
DQ[8:15]
CS
DQM
U1
8
DQM
CS
U5
R
DQ[0:7]
DQ[0:7]
DQ[40:47]
DQMB2
DQM
CS
UB1
8
CS
UB5
DQ[0:7]
DQ[0:7]
DQMB6
DQM
DQ[16:23]
DQM
R
CS
DQM
U2
8
CS
DQM
U6
DQ[0:7]
DQ[0:7]
DQ[48:55]
DQMB3
R 8
CS
DQM
UB2
CS
UB6
DQ[0:7]
DQ[0:7]
DQMB7
DQM
R
DQ[24:31]
CS
DQM
U3
8
R = 10 Ω
RC = 10 Ω
C = 15 pF
RAS
CAS
WE
CKE0
CKE1
A[0:13]
LEGEND: CS =
SPD =
PLL =
DQM
U7
R
DQ[0:7]
DQ[0:7]
CK0
CS
R
PLL
DQ[56:63]
Chip select
Serial Presence Detect
Phase Lock Loop
DQM
UB3
8
CS
UB7
DQ[0:7]
DQ[0:7]
U[0:7], UB[0:7]
VDD
PCK0: U0, U4, UB0, UB4
PCK1: U1, U5, UB1, UB5
PCK2: U2, U6, UB2, UB6
PCK3: U3, U7, UB3, UB7
RAS: SDRAM U[0:7], UB[0:7]
CAS: SDRAM U[0:7], UB[0:7]
WE: SDRAM U[0:7], UB[0:7]
CKE: SDRAM U[0:3], UB[0:3]
CKE: SDRAM U[4:7], UB[4:7]
A[0:13]: SDRAM U[0:7], UB[0:7]
CS
Two 0.1 µF per stacked
BOC/BGA SDRAM
VSS
U[0:7], UB[0:7]
SPD EEPROM
SCL
SDA
A0
A1
A2
SA0
SA1
SA2
NOTES: A. Ux devices are mounted on the top side and UBx devices are mounted on the bottom side of the module.
B. U[0:3] and UB[0:3] are located on top of the stack and U[4:7] and UB[4:7] are located on bottom of the stack.
C. DQMBx is connected to a single stacked device.
4
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SMMS704 − MAY 1998
absolute maximum ratings over ambient temperature range (unless otherwise noted)†
Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.5 V to 4.6 V
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 W
Ambient temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 55°C to 125°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
UNIT
3
3.3
3.6
V
Supply voltage
VIH
VIH-SPD
High-level input voltage
2
High-level input voltage for SPD device
2
VIL
TA
Low-level input voltage
Supply voltage
0
Ambient temperature
V
VDD + 0.3
5.5
V
V
−0.3
0.8
V
0
70
°C
capacitance over recommended ranges of supply voltage and ambient temperature,
f = 1 MHz (see Note 2)
TM16SM64JBN
PARAMETER
MIN
MAX
UNIT
Ci(CK)
Input capacitance, CK input
35
pF
Ci(AC)
Input capacitance, address and control inputs: A0 −A13, RAS, CAS, WE
50
pF
Ci(CKE)
Input capacitance, CKE input
50
pF
Co
Output capacitance
20
pF
Ci(DQMBx)
Input capacitance, DQMBx input
20
pF
Ci(Sx)
Input capacitance, Sx input
50
pF
Ci/o(SDA)
Input/output capacitance, SDA input
12
pF
10
pF
Ci(SPD)
Input capacitance, SPD inputs (except SDA)
NOTE 2: VDD = 3.3 V ± 0.3 V. Bias on pins under test is 0 V.
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5
PRODUCT PREVIEW
VDD
VSS
SMMS704 − MAY 1998
electrical characteristics over recommended ranges of supply voltage and ambient temperature
(unless otherwise noted) (see Note 3)
’16SM64JBN-10
PARAMETER
VOH
VOL
High-level output voltage
IOH = − 2 mA
IOL = 2 mA
Low-level output voltage
II
Input current (leakage)
0 V < VI < VDD + 0.3 V,
All other pins = 0 V to VDD
IO
Output current (leakage)
0 V < VO < VDD +0.3 V,
Output disabled
Operating current
Burst length = 1,
tRC ≥ tRC MIN
IOH/IOL = 0 mA,
(see Notes 4, 5, and 6)
ICC1
PRODUCT PREVIEW
TEST CONDITIONS
"10
µA
"10
µA
CAS latency = 2
860
mA
CAS latency = 3
920
mA
CKE ≤ VIL MAX, tCK = 15 ns (see Note 7)
16
CKE and CK ≤ VIL MAX, tCK = ∞ (see Note 8)
16
Precharge standby current in non-power-down
mode
CKE ≥ VIH MIN, tCK = 15 ns (see Note 7)
Active standby current in power-down mode
CKE and CK ≤ VIL MAX, tCK = ∞
(see Notes 4 and 8)
ICC3NS
ICC4
ICC5
Active standby current in non-power-down mode
Burst current
Auto-refresh current
V
V
ICC2N
ICC2NS
ICC3N
tCK = infinite (see Note 8)
CKE ≤ VIL MAX, tCK = 15 ns (see Notes 4 and 7)
80
mA
80
80
880
CKE ≥ VIH MIN, CK ≤ VIL MAX, tCK = ∞
(see Notes 4 and 8)
160
Page burst, IOH/IOL = 0 mA CAS latency = 2
All banks activated,
nCCD = one cycle
CAS latency = 3
(see Notes 9 and 10)
mA
640
CKE ≥ VIH MIN, tCK = 15 ns (see Notes 4 and 7)
tRC ≤ tRC MIN
(see Notes 5 and 8)
UNIT
0.4
Precharge standby current in power-down mode
ICC3PS
MAX
2.4
ICC2P
ICC2PS
ICC3P
MIN
mA
mA
976
mA
1416
CAS latency = 2
1 280
CAS latency = 3
1 280
mA
ICC6
Self-refresh current
CKE ≤ VIL MAX
32
mA
NOTES: 3. All specifications apply to the device after power-up initialization. All control and address inputs must be stable and valid.
4. Only one bank is activated.
5. tRC ≥ MIN
6. Control and address inputs change state twice during tRC.
7. Control and address inputs change state once every 30 ns.
8. Control and address inputs do not change state (stable).
9. Control and address inputs change once every cycle.
10. Continuous burst access, nCCD = 1 cycle
6
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SMMS704 − MAY 1998
ac timing requirements†‡
’16SM64JBN-10
MAX
UNIT
tCK2
tCK3
Cycle time, CK
CAS latency = 2
15
ns
Cycle time, CK
CAS latency = 3
10
ns
tCH
tCL
Pulse duration, CK high
3
ns
tAC2
tAC3
Access time, CK high to data out (see Note 11)
CAS latency = 2
7.5
ns
Access time, CK high to data out (see Note 11)
CAS latency = 3
7.5
ns
tOH
tLZ
Hold time, CK high to data out
3
ns
Delay time, CK high to DQ in low-impedance state (see Note 12)
2
ns
tHZ
tIS
Delay time, CK high to DQ in high-impedance state (see Note 13)
Setup time, address, control, and data input
2
ns
tIH
tCESP
Hold time, address, control, and data input
1
ns
Power down/self-refresh exit time
8
tRAS
tRC
Delay time, ACTV command to DEAC or DCAB command
50
Delay time, ACTV, MRS, REFR, or SLFR to ACTV, MRS, REFR,or SLFR command
80
ns
30
ns
tRCD
Pulse duraction, CK low
Delay time ACTV
(see Note 14)
command
3
to
READ,
READ-P,
WRT,
ns
10
or
WRT-P
command
ns
ns
100000
ns
tRP
tRRD
Delay time, DEAC or DCAB command to ACTV, MRS, REFR, or SLFR command
30
ns
Delay time, ACTV command in one bank to ACTV command in the other bank
20
ns
tRSA
tAPR
Delay time, MRS command to ACTV, MRS, REFR,or SLFR command
20
ns
tAPW
tT
Final data in of WRT-P operation to ACTV, MRS, SLFR,or REFR command
tREF
Refresh interval
nCCD
nCDD
Delay time, READ or WRT command to an interrupting command
1
cycles
Delay time, CS low or high to input enabled or inhibited
0
cycles
nCLE
nCWL
Delay time, CKE high or low to CLK enabled or disabled
1
Delay time, final data in of WRT operation to READ, READ-P, WRT, or WRT-P
1
nDID
nDOD
Delay time, ENBL or MASK command to enabled or masked data in
0
0
cycles
2
2
cycles
nHZP2
nHZP3
Delay time, DEAC or DCAB, command to DQ in high-impedance state
CAS latency = 2
2
cycles
Delay time, DEAC or DCAB, command to DQ in high-impedance state
CAS latency = 3
3
cycles
Final data out of READ-P operation to ACTV, MRS, SLFR,or REFR command
tRP − (CL−1)* tCK
tRP + 1 tCK
Transition time
1
ns
ns
5
64
Delay time, ENBL or MASK command to enabled or masked data out
PRODUCT PREVIEW
MIN
1
ms
ms
cycles
cycles
Delay time, final data in of WRT operation to DEAC or DCAB command
1
cycles
nWR
nWCD Delay time, WRT command to first data in
0
0 cycles
† All references are made to the rising transition of CK unless otherwise noted.
‡ Specifications in this table represent a single SDRAM device.
NOTES: 11. tAC is referenced from the rising transition of CK that precedes the data-out cycle. For example, the first data out tAC is referenced
from the rising transition of CK that is read latency (one cycle after the READ command). Access time is measured at output
reference level 1.4 V.
12. tLZ is measured from the rising transition of CK that is read latency (one cycle after the READ command).
13. tHZ (max) defines the time at which the outputs are no longer driven and is not referenced to output voltage levels.
14. For read or write operations with automatic deactivate, tRCD must be set to satisfy minimum tRAS.
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7
SMMS704 − MAY 1998
serial presence detect
The serial presence detect (SPD) is contained in a 256 byte serial EEPROM located on the module. The SPD
nonvolatile EEPROM contains various data such as module configuration, SDRAM organization, and timing
parameters (see Table 1). Only the first 128 bytes are programmed by Texas Instruments, while the remaining
128 bytes are available for customer use. Programming is done through an IIC bus using the clock (SCL) and
data (SDA) signals. All Texas Instruments modules comply with the current JEDEC SPD standards. See the
Texas Instruments Serial Presence Detect Technical Reference (literature number SMMU001) for further
details. Table 1 lists SPD contents as follows:
Table 1. Serial Presence Detect Data
TM16SM64JBN-10
PRODUCT PREVIEW
BYTE
NO.
ITEM
DATA
0
Defines number of bytes written into serial memory during module manufacturing
128 bytes
80h
1
Total number of bytes of SPD memory device
256 bytes
08h
2
Fundamental memory type (FPM, EDO, SDRAM, . . .)
SDRAM
04h
3
Number of row addresses on this assembly
12
0Ch
4
Number of column addresses on this assembly
9
09h
5
Number of module rows on this assembly
2 banks
02h
6
Data width of this assembly
64 bits
40h
7
Data width continuation
8
Voltage interface standard of this assembly
00h
9
SDRAM cycle time at maximum supported CAS latency (CL), CL = X
10
SDRAM access from clock at CL = X
11
SODIMM configuration type (non-parity, parity, error correcting code [ECC])
12
Refresh rate / type
13
SDRAM width, primary DRAM
14
Error-checking SDRAM data width
15
Minimum clock delay, back-to-back random column addresses
16
Burst lengths supported
17
Number of banks on each SDRAM device
18
CAS latencies supported
19
CS latency
20
Write latency
21
8
DESCRIPTION OF FUNCTION
SDRAM module attributes
LVTTL
01h
tCK = 10 ns
tAC = 7.5 ns
Non-Parity
A0h
75h
00h
15.6 µs/
self-refresh
80h
x8
08h
N/A
00h
1 CK cycle
01h
1, 2, 4, and 8
0Fh
4 banks
04h
2, 3
06h
0
01h
0
01h
Non-buffered/
Non-registered
00h
VDD tolerance =
("10%)
Burst read / write,
precharge all,
auto precharge
0Eh
22
SDRAM device attributes: general
23
Minimum clock cycle time at CL = X − 1
tCK = 15 ns
F0h
24
Maximum data-access time from clock at CL = X − 1
75h
25
Minimum clock cycle time at CL = X − 2
tAC = 7.5 ns
N/A
26
Maximum data-access time from clock at CL = X − 2
N/A
00h
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00h
SMMS704 − MAY 1998
serial presence detect (continued)
Table 1. Serial Presence Detect Data (Continued)
TM16SM64JBN-10
BYTE
NO.
DESCRIPTION OF FUNCTION
ITEM
DATA
tRP = 30 ns
tRRD = 20 ns
1Eh
tRCD = 30 ns
tRAS =50 ns
1Eh
Density of each bank on module
64M Bytes
10h
32
Command and address signal input setup time
20h
33
Command and address signal input hold time
tIS = 2 ns
tIH = 1 ns
34
Data signal input setup time
20h
35
Data signal input hold time
tIS = 2 ns
tIH = 1 ns
Rev. 1.2
12h
27
Minimum row-precharge time
28
Minimum row-active to row-active delay
29
Minimum RAS-to-CAS delay
30
Minimum RAS pulse width
31
32h
10h
10h
Superset features (may be used in the future)
62
SPD revision
63
Checksum for byte 0 −62
19
13h
97h
9700...00h
72
Manufacturer’s JEDEC ID code per JEP −106E
Manufacturing location†
73
Manufacturer’s part number
T
54h
74
Manufacturer’s part number
M
4Dh
75
Manufacturer’s part number
1
31h
76
Manufacturer’s part number
6
36h
77
Manufacturer’s part number
S
53h
78
Manufacturer’s part number
M
4Dh
79
Manufacturer’s part number
6
36h
80
Manufacturer’s part number
4
34h
81
Manufacturer’s part number
J
4Ah
82
Manufacturer’s part number
B
42h
83
Manufacturer’s part number
N
4Eh
84
Manufacturer’s part number
−
2Dh
85
Manufacturer’s part number
1
31h
86
Manufacturer’s part number
0
30h
87 −90
Manufacturer’s part number
Die revision code†
SPACE
20h
64 −71
91
TBD
TBD
TBD
93 −94
PCB revision code†
Manufacturing date†
95 −98
Assembly serial number†
TBD
99 −125
Manufacturer-specific data†
TBD
92
TBD
126
Clock frequency
127
SDRAM component and clock interconnection details
System-integrator’s-specific data‡
128−166
PRODUCT PREVIEW
36 −61
14h
66 MHz
66h
199
C7h
TBD
167−255 Open
† TBD indicates values that are determined at manufacturing time and are module dependent.
‡ These TBD values are determined and programmed by the customer (optional).
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9
SMMS704 − MAY 1998
device symbolization
TM16SM64JBN
-SS
YY
MM
T
-SS
=
=
=
=
Year Code
Month Code
Assembly Site Code
Speed Code
PRODUCT PREVIEW
NOTE A: Location of symbolization may vary.
10
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• HOUSTON, TEXAS 77251−1443
YYMMT
SMMS704 − MAY 1998
MECHANICAL DATA
BDQ (R-SODIMM-N144)
SMALL OUTLINE DUAL IN-LINE MEMORY MODULE
2.665 (67,69)
2.655 (67,44)
0.024 (0,61) TYP
0.044 (1,12)
0.036 (0,91)
Notch 0.060 (1,52) x 0.158 (4,01) Deep
PRODUCT PREVIEW
Notch 0.157 (4,00) x 0.079 (2,00) Deep
2 Places
0.010 (0,25) MAX
0.031 (0,79)
0.788 (20,00) TYP
0.098 (2,49)
1.130 (28,70)
1.120 (28,45)
0.196 (4,98)
0.157 (4,00)
0.126 (3,20)
0.095 (2,41) MAX
0.157 (4,00) MAX
(For Double-Sided Module Only)
4088188/B 03/98
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MO-190
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• HOUSTON, TEXAS 77251−1443
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