TI TM4EP64DPN

SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998
D Organization
D
D
D
D
D
D
D JEDEC 168-Pin Dual-In-Line Memory
− TM2EP64DxN . . . 2 097 152 × 64 Bits
− TM2EP72DxN . . . 2 097 152 × 72 Bits
− TM4EP64DxN . . . 4 194 304 × 64 Bits
− TM4EP72DxN . . . 4 194 304 × 72 Bits
Single 3.3-V Power Supply
(±10% Tolerance)
TM2EP64DxN — Uses Eight 16M-Bit
(2M × 8-Bit) Dynamic Random Access
Memories (DRAMs) in Thin Small-Outline
Package (TSOP), or Small-Outline J-Lead
Package (SOJ)
TM2EP72DxN — Uses Nine 16M-Bit
(2M × 8-Bit) DRAMs in TSOP, or SOJ
TM4EP64DxN — Uses 16 16M-Bit
(2M × 8-Bit) DRAMs in TSOP, or SOJ
TM4EP72DxN — Uses 18 16M-Bit
(2M × 8-Bit) DRAMs in TSOP, or SOJ
Performance ranges
’xEPxxDxN-50
’xEPxxDxN-60
’xEPxxDxN-70
ACCESS ACCESS ACCESS
TIME
TIME
TIME
tRAC
tCAC
tAA
MAX
MAX
MAX
50 ns
13 ns
25 ns
60 ns
15 ns
30 ns
70 ns
18 ns
35 ns
D
D
D
D
D
D
D
Module (DIMM) Without Buffer for Use With
Socket
High-Speed, Low-Noise LVTTL Interface
Long Refresh Period: 32 ms (2 048 Cycles)
3-State Output
Extended-Data-Out (EDO) Operation With
CAS-Before-RAS (CBR), RAS-Only, and
Hidden Refresh
Serial Presence Detect (SPD) Using
EEPROM
Ambient Air Temperature Range
0°C to 70°C
Gold-Plated Contacts
EDO
CYCLE
tHPC
MIN
20 ns
25 ns
30 ns
description
The TM2EP64DPN is a 16M-byte, 168-pin, dual-in-line memory module (DIMM). The DIMM is composed of
eight TMS427809A, 2 097 152 byte × 8-bit 2K-refresh EDO DRAMs, each in a 400-mil, 28-pin plastic TSOP
(DGC suffix) mounted on a substrate with decoupling capacitors. See the TMS427809A data sheet (literature
number SMKS887). The TM2EP64DJN is available with an SOJ package (DZ suffix).
The TM2EP72DPN is a 16M-byte, 168-pin DIMM. The DIMM is composed of nine TMS427809A,
2 097 152 byte × 8-bit 2K-refresh EDO DRAMs, mounted on a substrate with decoupling capacitors. See the
TMS427809A data sheet (literature number SMKS887). The TM2EP72DJN is available with an SOJ package
(DZ suffix).
The TM4EP64DPN is a 32M-byte, 168-pin, dual-in-line memory module (DIMM). The DIMM is composed of
sixteen TMS427809A, 2 097 152 × 8-bit 2K-refresh EDO DRAMs, mounted on a substrate with decoupling
capacitors. The TM4EP64DJN is available with an SOJ package (DZ suffix).
The TM4EP72DPN is a 32M-byte, 168-pin DIMM. The DIMM is composed of 18 TMS427809A, 2097152 × 8-bit
2K-refresh EDO DRAMs, mounted on a substrate with decoupling capacitors. See the TMS427809A data sheet
(literature number SMKS887). The TM4EP72DJN is available with an SOJ package (DZ suffix).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1998, Texas Instruments Incorporated
! "#$ ! %#&'" ($)
(#"! " !%$""! %$ *$ $! $+! !#$!
!(( ,-) (#" %"$!!. ($! $"$!!'- "'#($
$!. '' %$$!)
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•
1
SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998
operation
The TMxEPxxDxN DIMMs operate as displayed in Table 1.
Table 1. TMxEPxxDxN DIMM Device Table
2
DIMM
DEVICE AND QUANTITY ( )
TM2EP64DxN
TMS427809A (8)
TM2EP72DxN
TMS427809A (9)
TM4EP64DxN
TMS427809A (16)
TM4EP72DxN
TMS427809A (18)
Connected as shown in the functional
block diagram.
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•
SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998
DUAL-IN-LINE MEMORY MODULE
( TOP VIEW )
TM2EP64DPN
( SIDE VIEW )
TM4EP72DPN
( SIDE VIEW )
PIN NOMENCLATURE
A[0:10]
A[0:9]
DQ[0:63]
CB[0:7]
CAS[0:7]
RAS[0:3]
WE0 and WE2
OE0 and OE2
SA[0:2]
1
10
SDA
SCL
NC
VDD
VSS
11
Row Address Inputs
Column Address Inputs
Data In / Data Out
Check-Bit In / Check-Bit Out
Column-Address Strobe
Row-Address Strobe
Write Enable
Output Enable
Serial Presence Detect (SPD)
Device Add Input
SPD Address / Data
SPD Clock
No-Connect Pin
3.3-V Supply
Ground
40
41
84
•
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•
3
SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998
Pin Assignments
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
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ÁÁÁÁÁÁÁÁ
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ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
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ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
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ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
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ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
PIN
NO.
NAME
NO.
1
43
2
VSS
DQ0
3
DQ1
4
NO.
85
44
VSS
OE2
45
RAS2
DQ2
46
5
DQ3
6
7
VDD
DQ4
8
DQ5
9
PIN
NAME
NO.
PIN
NAME
127
86
VSS
DQ32
128
VSS
NC
87
DQ33
129
RAS3
CAS2
88
DQ34
130
CAS6
47
CAS3
89
DQ35
131
CAS7
48
WE2
90
132
NC
49
91
133
50
VDD
NC
VDD
DQ36
92
DQ37
134
VDD
NC
DQ6
51
NC
93
DQ38
135
NC
10
DQ7
52
CB2
94
DQ39
136
CB6
11
DQ8
53
CB3
95
DQ40
137
CB7
12
VSS
DQ9
54
97
VSS
DQ41
138
55
VSS
DQ16
96
13
139
VSS
DQ48
14
DQ10
56
DQ17
98
DQ42
140
DQ49
15
DQ11
57
DQ18
99
DQ43
141
DQ50
16
DQ12
58
DQ19
100
DQ44
142
DQ51
17
DQ13
59
101
DQ45
143
18
60
102
144
61
NC
103
VDD
DQ46
VDD
DQ52
19
VDD
DQ14
VDD
DQ20
145
NC
20
DQ15
62
NC
104
DQ47
146
NC
21
CB0
63
NC
105
CB4
147
NC
22
CB1
64
106
CB5
148
23
VSS
NC
65
VSS
DQ21
107
149
66
DQ22
108
VSS
NC
VSS
DQ53
150
DQ54
25
NC
67
DQ23
109
NC
151
DQ55
26
68
111
VDD
NC
152
69
VSS
DQ24
110
27
VDD
WE0
153
VSS
DQ56
28
CAS0
70
DQ25
112
CAS4
154
DQ57
29
CAS1
71
DQ26
113
CAS5
155
DQ58
30
RAS0
72
DQ27
114
RAS1
156
DQ59
31
OE0
73
115
NC
157
32
74
116
VDD
DQ60
75
DQ29
117
VSS
A1
158
33
VSS
A0
VDD
DQ28
159
DQ61
34
A2
76
DQ30
118
A3
160
DQ62
35
A4
77
DQ31
119
A5
161
DQ63
36
A6
78
A7
162
A8
79
VSS
NC
120
37
121
A9
163
VSS
NC
38
A10
80
NC
122
NC
164
NC
39
NC
81
NC
123
NC
165
SA0
40
82
SDA
124
SA1
83
SCL
125
VDD
NC
166
41
VDD
VDD
167
SA2
42
NC
84
VDD
126
NC
168
VDD
24
4
PIN
NAME
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•
SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998
dual-in-line memory module and components
The dual-in-line memory module and components include:
D PC substrate: 1,27 " 0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage
D Bypass capacitors: Multilayer ceramic
D Contact area: Nickel plate and gold plate over copper
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•
5
SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998
functional block diagram
The following table shows the four DIMM modules and locations (Ux/UBx) that are used.
COMPONENT TABLE
MODULE
LOCATIONS USED
TM2EP64DxN
U[0:7]
TM2EP72DxN
U[0:8]
TM4EP64DxN
U[0:7], UB[0:7]
TM4EP72DxN
U[0:8], UB[0:8]
RAS0
RAS1
RAS2
RAS3
WE0
OE0
WE0
OE0
WE2
OE2
WE2
OE2
CAS0
DQ[0:7]
CAS1
DQ[8:15]
CAS1
CB[0:7]
CAS2
DQ[16:23]
CAS3
DQ[24:31]
CAS OE W RAS
CAS OE W RAS
DQ[0:7] U0
DQ[0:7] UB0
CAS OE W RAS
CAS OE W RAS
DQ[0:7] U1
DQ[0:7] UB1
CAS OE W RAS
CAS OE W RAS
DQ[0:7] U8
DQ[0:7] UB8
CAS OE W RAS
CAS OE W RAS
DQ[0:7] U2
DQ[0:7] UB2
CAS OE W RAS
CAS OE W RAS
DQ[0:7] U3
DQ[0:7] UB3
CAS4
DQ[32:39]
CAS5
DQ[40:47]
CAS6
DQ[48:55]
CAS7
DQ[56:63]
CAS
OE W RAS
CAS OE W RAS
DQ[0:7] U4
DQ[0:7] UB4
CAS
CAS OE W RAS
OE W RAS
DQ[0:7] U5
DQ[0:7] UB5
CAS
CAS OE W RAS
OE W RAS
DQ[0:7] U6
DQ[0:7] UB6
CAS
CAS OE W RAS
OE W RAS
DQ[0:7] UB7
DQ[0:7] U7
A[0: 10]
A[0 : 10] : U[0:8], UB[0:8]
SPD EEPROM
SCL
SDA
Legend: SPD = Serial Presence Detect
A0
A1
A2
SA0
SA1
SA2
VDD
VSS
6
•
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•
U[0:8], UB[0:8]
Two 0.1 µF
(minimum) per
DRAM
U[0:8], UB[0:8]
SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998
absolute maximum ratings over ambient temperature range (unless otherwise noted)†
Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.5 V to 4.6 V
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation: TM2EP64DxN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 W
TM2EP72DxN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 W
TM4EP64DxN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 W
TM4EP72DxN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 W
Ambient temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 55°C to 125°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
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ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
recommended operating conditions
MIN
NOM
MAX
UNIT
3
3.3
3.6
V
VDD
VSS
Supply voltage
VIH
VIH −SPD
High-level input voltage
2
High-level input voltage for the SPD device
2
VIL
TA
Low-level input voltage
Supply voltage
0
V
VDD + 0.3
5.5
V
V
−0.3
0.8
V
0
70
°C
Ambient temperature
capacitance over recommended ranges of supply voltage and ambient temperature, f = 1 MHz
(see Note 2)
’2EP64DxN
PARAMETER
MIN
’2EP72DxN
MAX
MIN
MAX
’4EP64DxN
MIN
MAX
’4EP72DxN
MIN
MAX
UNIT
Ci(A)
Input capacitance, A0 −A10
42
47
82
92
pF
Ci(OE)
Input capacitance, OEx
30
37
58
72
pF
Ci(CAS)
Input capacitance, CASx
9
16
16
30
pF
Ci(RAS)
Input capacitance, RASx
30
37
30
37
pF
Ci(W)
Input capacitance, WEx
30
37
38
37
pF
Co
Output capacitance
9
9
16
16
pF
Ci/o(SDA)
Input/output capacitance, SDA input
9
9
9
9
pF
Ci(SPD)
Input capacitance, SA0,SA1,SA2,SCL inputs
7
7
7
7
pF
NOTE 2: VDD = NOM supply voltage ± 10%, and the bias on pins under test is 0 V.
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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•
7
SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998
electrical characteristics over recommended ranges of supply voltage and ambient temperature
(unless otherwise noted)
TM2EP64DxN
PARAMETER
’2EP64DxN-50
TEST CONDITIONS†
MIN
’2EP64DxN-60
MAX
MIN
’2EP64DxN-70
MAX
MIN
MAX
UNIT
High-level
output
voltage
IOH = − 2 mA
LVTTL
VOH
IOH = − 100 µA
LVCMOS
Low-level
output
voltage
IOL = 2 mA
LVTTL
0.4
0.4
0.4
VOL
IOL = 100 µA
LVCMOS
0.2
0.2
0.2
II
Input current
(leakage)
VDD = 3.6 V,
VI = 0 V to 3.9 V,
All others = 0 V to VDD
± 10
± 10
± 10
µA
IO
Output
current
(leakage)
VDD = 3.6 V,
CASx high
VO = 0 V to VDD,
± 10
± 10
± 10
µA
ICC1‡§
Read- or
write-cycle
current
VDD = 3.6 V,
Minimum cycle
960
800
720
mA
VIH = 2 V (LVTTL),
After one memory cycle,
RASx and CASx high
16
16
16
mA
VIH = VDD − 0.2 V
(LVCMOS),
After one memory cycle,
RASx and CASx high
8
8
8
mA
ICC2
Standby
current
2.4
2.4
2.4
V
VDD −0.2
VDD −0.2
VDD −0.2
V
ICC3‡§
Average
refresh
current
(RAS-only
refresh
or CBR)
VDD = 3.6 V,
Minimum cycle,
RASx cycling,
CASx high (RAS-only refresh),
RASx low after CASx low (CBR)
960
800
720
mA
ICC4‡¶
Average
EDO current
VDD = 3.6 V,
RASx low,
880
720
640
mA
tHPC = MIN,
CASx cycling
† For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements.
‡ Measured with outputs open
§ Measured with a maximum of one address change while RASx = VIL
¶ Measured with a maximum of one address change during each EDO cycle, tHPC
8
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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•
SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998
electrical characteristics over recommended ranges of supply voltage and ambient temperature
(unless otherwise noted) (continued)
TM2EP72DxN
PARAMETER
’2EP72DxN-50
TEST CONDITIONS†
MIN
’2EP72DxN-60
MAX
MIN
’2EP72DxN-70
MAX
MIN
MAX
UNIT
High-level
output
voltage
IOH = − 2 mA
LVTTL
VOH
IOH = − 100 µA
LVCMOS
Low-level
output
voltage
IOL = 2 mA
LVTTL
0.4
0.4
0.4
VOL
IOL = 100 µA
LVCMOS
0.2
0.2
0.2
II
Input current
(leakage)
VDD = 3.6 V,
VI = 0 V to 3.9 V,
All others = 0 V to VDD
± 10
± 10
± 10
µA
IO
Output
current
(leakage)
VDD = 3.6 V,
CASx high
VO = 0 V to VDD,
± 10
± 10
± 10
µA
ICC1‡§
Read- or
write-cycle
current
VDD = 3.6 V,
Minimum cycle
976
816
736
mA
VIH = 2 V (LVTTL),
After one memory cycle,
RASx and CASx high
18
18
18
mA
VIH = VDD − 0.2 V
(LVCMOS),
After one memory cycle,
RASx and CASx high
9
9
9
mA
ICC2
Standby
current
2.4
2.4
2.4
V
VDD −0.2
VDD −0.2
VDD −0.2
V
ICC3‡§
Average
refresh
current
(RASx-only
refresh
or CBR)
VDD = 3.6 V,
Minimum cycle,
RASx cycling,
CASx high (RAS-only refresh),
RASx low after CASx low (CBR)
976
816
736
mA
ICC4‡¶
Average
EDO current
VDD = 3.6 V,
RASx low,
990
810
720
mA
tHPC = MIN,
CASx cycling
† For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements.
‡ Measured with outputs open
§ Measured with a maximum of one address change while RASx = VIL
¶ Measured with a maximum of one address change during each EDO cycle, tHPC
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
9
SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998
electrical characteristics over recommended ranges of supply voltage and ambient temperature
(unless otherwise noted) (continued)
TM4EP64DxN
PARAMETER
’4EP64DxN-50
TEST CONDITIONS†
MIN
’4EP64DxN-60
MAX
MIN
MAX
’4EP64DxN-70
MIN
MAX
UNIT
High-level
output
voltage
IOH = − 2 mA
LVTTL
VOH
IOH = − 100 µA
LVCMOS
Low-level
output
voltage
IOL = 2 mA
LVTTL
0.4
0.4
0.4
VOL
IOL = 100 µA
LVCMOS
0.2
0.2
0.2
II
Input current
(leakage)
VDD = 3.6 V,
VI = 0 V to 3.9 V,
All others = 0 V to VDD
± 20
± 20
± 20
µA
IO
Output
current
(leakage)
VDD = 3.6 V,
CASx high
VO = 0 V to VDD,
± 20
± 20
± 20
µA
ICC1‡§
Read- or
write-cycle
current
VDD = 3.6 V,
Minimum cycle
976
816
736
mA
VIH = 2 V (LVTTL),
After one memory cycle,
RASx and CASx high
32
32
32
mA
VIH = VDD − 0.2 V
(LVCMOS),
After one memory cycle,
RASx and CASx high
16
16
16
mA
ICC2
Standby
current
2.4
2.4
2.4
V
VDD −0.2
VDD−0.2
VDD −0.2
V
ICC3‡§
Average
refresh
current
(RASx-only
refresh
or CBR)
VDD = 3.6 V,
Minimum cycle,
RASx cycling,
CASx high (RAS-only refresh),
RASx low after CASx low (CBR)
976
816
736
mA
ICC4‡¶
Average
EDO current
VDD = 3.6 V,
RASx low,
896
736
656
mA
tHPC = MIN,
CASx cycling
† For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements.
‡ Measured with outputs open
§ Measured with a maximum of one address change while RASx = VIL
¶ Measured with a maximum of one address change during each EDO cycle, tHPC
10
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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•
SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998
electrical characteristics over recommended ranges of supply voltage and ambient temperature
(unless otherwise noted) (continued)
TM4EP72DxN
PARAMETER
’4EP72DxN-50
TEST CONDITIONS†
MIN
’4EP72DxN-60
MAX
MIN
MAX
’4EP72DxN-70
MIN
MAX
UNIT
High-level
output
voltage
IOH = − 2 mA
LVTTL
VOH
IOH = − 100 µA
LVCMOS
Low-level
output
voltage
IOL = 2 mA
LVTTL
0.4
0.4
0.4
VOL
IOL = 100 µA
LVCMOS
0.2
0.2
0.2
II
Input current
(leakage)
VDD = 3.6 V,
VI = 0 V to 3.9 V,
All others = 0 V to VDD
± 20
± 20
± 20
µA
IO
Output
current
(leakage)
VDD = 3.6 V,
CASx high
VO = 0 V to VDD,
± 20
± 20
± 20
µA
ICC1‡§
Read- or
write-cycle
current
VDD = 3.6 V,
Minimum cycle
1098
918
828
mA
VIH = 2 V (LVTTL),
After one memory cycle,
RASx and CASx high
36
36
36
mA
VIH = VDD − 0.2 V
(LVCMOS),
After one memory cycle,
RASx and CASx high
18
18
18
mA
ICC2
Standby
current
2.4
2.4
2.4
V
VDD −0.2
VDD −0.2
VDD −0.2
V
ICC3‡§
Average
refresh
current
(RASx-only
refresh
or CBR)
VDD = 3.6 V,
Minimum cycle,
RASx cycling,
CASx high (RAS-only refresh),
RASx low after CASx low (CBR)
1098
918
828
mA
ICC4‡¶
Average
EDO current
VDD = 3.6 V,
RASx low,
1008
828
738
mA
tHPC = MIN,
CASx cycling
† For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements.
‡ Measured with outputs open
§ Measured with a maximum of one address change while RASx = VIL
¶ Measured with a maximum of one address change during each EDO cycle, tHPC
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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•
11
SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998
switching characteristics over recommended ranges of supply voltage and ambient temperature
(see Note 3)
’xEP64DxN-50
’xEP72DxN-50
PARAMETER
MIN
MAX
’xEP64DxN-60
’xEP72DxN-60
MIN
MAX
’xEP64DxN-70
’xEP72DxN-70
MIN
UNIT
MAX
tAA
tCAC
Access time from column address (see Note 4)
25
30
35
ns
Access time from CASx (see Note 4)
13
15
18
ns
tCPA
tRAC
Access time from CASx precharge (see Note 4)
28
35
40
ns
Access time from RASx (see Note 4)
50
60
70
ns
tOEA
tCLZ
Access time from OEx (see Note 4)
18
ns
Delay time, CASx to output in low impedance
0
tREZ
tCEZ
Output buffer turn off delay from RASx (see Note 5)
3
13
3
15
3
18
ns
Output buffer turn off delay from CASx (see Note 5)
3
13
3
15
3
18
ns
tOEZ
tWEZ
Output buffer turn off delay from OEx (see Note 5)
3
13
3
15
3
18
ns
Output buffer turn off delay from WEx (see Note 5)
3
13
3
15
3
18
ns
13
15
0
0
ns
NOTES: 3. With ac parameters, it is assumed that tT = 2 ns.
4. Access times are measured with output reference levels of VOH = 2 V and VOL = 0.8 V.
5. The maximum values of tREZ, tCEZ, tOEZ, and tWEZ are specified when the outputs are no longer driven. Data-in should not be driven
until one of the applicable maximum values is satisfied.
EDO timing requirements (see Note 3)
’xEP64DxN-50
’xEP72DxN-50
MIN
MAX
’xEP64DxN-60
’xEP72DxN-60
MIN
MAX
’xEP64DxN-70
’xEP72DxN-70
MIN
UNIT
MAX
tHPC
tPRWC
Cycle time, EDO page mode, read-write
20
25
30
ns
Cycle time, EDO read-write
57
68
78
ns
tCSH
tCHO
Delay time, RASx active to CASx precharge
40
48
58
ns
Hold time, OEx from CASx
7
10
10
ns
tDOH
tOEP
Hold time, output from CASx
5
5
5
ns
Precharge time, OEx
5
5
5
ns
tCAS
tWPE
Pulse duration, CASx active
8
Pulse duration, WEx active (output disable only)
7
7
7
ns
tCP
tOCH
Pulse duration, CASx precharge
8
10
10
ns
Setup time, OEx before CASx
8
10
10
ns
5
5
5
ns
tOEP
Precharge time, OEx
NOTE 3: With ac parameters, it is assumed that tT = 2 ns.
12
•
10 000
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
10
10 000
12
10 000
ns
SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998
ac timing requirements
’xEP64DxN-50
’xEP72DxN-50
’xEP64DxN-60
’xEP72DxN-60
’xEP64DxN-70
’xEP72DxN-70
MIN
MIN
MIN
MAX
MAX
tRC
tRWC
Cycle time, random read or write
tRASP
tRAS
Pulse duration, RASx active, fast page mode (see Note 6)
50
100 000
60
100 000
70
100 000
ns
Pulse duration, RASx active, non-page mode (see Note 6)
50
10 000
60
10 000
70
10 000
ns
tRP
tWP
Pulse duration, RASx precharge
30
tRASS
tRPS
Pulse duration, RASx active, self refresh (see Note 7)
tASC
tASR
Cycle time, read-write
104
124
135
160
40
ns
ns
50
ns
ns
8
10
10
100
100
100
ms
90
110
130
ns
Setup time, column address
0
0
0
ns
Setup time, row address
0
0
0
ns
tDS
tRCS
Setup time, data in (see Note 8)
0
0
0
ns
Setup time, read command
0
0
0
ns
tCWL
tRWL
Setup time, write command before CASx precharge
8
10
12
ns
Setup time, write command before RASx precharge
8
10
12
ns
Setup time, write command before CASx active
(early-write only)
0
0
0
ns
tWCS
Pulse duration, write command
84
111
UNIT
MAX
Pulse duration, RASx precharge after self refresh
tWRP
tCSR
Setup time, WEx high before RASx low (CBR refresh only)
10
10
10
ns
Setup time, CASx referenced to RASx ( CBR refresh only )
5
5
5
ns
tCAH
tDH
Hold time, column address
8
10
12
ns
Hold time, data in (see Note 8)
8
10
12
ns
tRAH
tRCH
Hold time, row address
8
10
10
ns
Hold time, read command referenced to CASx (see Note 9)
0
0
0
ns
tRRH
Hold time, read command referenced to RASx (see Note 9)
0
0
0
ns
tWCH
Hold time, write command during CASx active
( early-write only )
8
10
12
ns
tROH
tWRH
Hold time, RASx referenced to OEx
8
10
10
ns
Hold time, WEx high after RASx low (CBR refresh only)
10
10
10
ns
tCHR
tOEH
Hold time, CASx referenced to RASx ( CBR refresh only )
10
10
10
ns
Hold time, OEx command
13
15
18
ns
tRHCP
tCHS
Hold time, RASx active from CASx precharge
28
35
40
ns
− 50
− 50
− 50
ns
42
49
57
ns
tAWD
Hold time, CASx referenced to RASx (self refresh only)
Delay time, column address to write command
( read-write only )
tCRP
Delay time, CASx precharge to RASx
5
5
5
ns
NOTES: 6. In a read-write cycle, tRWD and tRWL must be observed.
7. During the period of 10 µs ≤ tRASS ≤100 µs, the device is in a transition state from normal-operation mode to self-refresh mode.
8. Referenced to the later of CASx or WEx in write operations
9. Either tRRH or tRCH must be satisfied for a read cycle.
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
13
SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998
ac timing requirements (continued)
’xEP64DxN-50
’xEP72DxN-50
’xEP64DxN-60
’xEP72DxN-60
’xEP64DxN-70
’xEP72DxN-70
MIN
MIN
MIN
MAX
MAX
UNIT
MAX
tCWD
tOED
Delay time, CASx to write command ( read-write only )
30
34
40
Delay time, OEx to data in
13
15
18
tRAD
tRAL
Delay time, RASx to column address ( see Note 10)
10
Delay time, column address to RASx precharge
25
30
35
ns
tCAL
Delay time, column address to CASx precharge
18
20
25
ns
tRCD
tRPC
Delay time, RASx to CASx ( see Note 10)
12
tRSH
tRWD
Delay time, CASx active to RASx precharge
tCPW
tREF
tT
Delay time, RASx precharge to CASx
25
37
14
30
45
12
14
ns
35
52
ns
ns
5
5
5
ns
8
10
12
ns
Delay time, RASx to write command (read-write only)
67
79
92
ns
Delay time, CASx precharge to write command
(read-write only)
45
54
62
ns
Refresh time interval
32
Transition time
2
30
NOTE 10: The maximum value is specified only to ensure access time.
14
12
ns
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
32
2
30
2
32
ms
30
ns
SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998
serial presence detect
The serial presence detect (SPD) is contained in a 2K-bit serial EEPROM located on the module. The SPD
nonvolatile EEPROM contains various data such as module configuration, DRAM organization, and timing
parameters (see tables below). Only the first 128 bytes are programmed by Texas Instruments, while the
remaining 128 bytes are available for customer use. Programming is done through an IIC bus using the clock
(SCL) and data (SDA) signals. All Texas Instruments module comply with the current JEDEC SPD Standard.
Please see the Texas Instruments Serial Presence Detect Technical Reference (literature number SMMU001)
for further details.
Tables in this section list the SPD contents as follows:
Table 2 −TM2EP64DxN
Table 4 −TM4EP64DxN
Table 3 −TM2EP72DxN
Table 5 −TM4EP72DxN
Table 2. Serial Presence Detect Data for the TM2EP64DxN
BYTE
NO.
’2EP64DxN-50
FUNCTION DESCRIBED
’2EP64DxN-60
’2EP64DxN-70
ITEM
DATA
ITEM
DATA
ITEM
DATA
0
Defines number of bytes written
into serial memory during module
manufacturing
128 bytes
80h
128 bytes
80h
128 bytes
80h
1
Total number of bytes of SPD
memory device
256 bytes
08h
256 bytes
08h
256 bytes
08h
2
Fundamental memory type (FPM,
EDO, SDRAM)
EDO
02h
EDO
02h
EDO
02h
3
Number of row addresses on this
assembly
11
0Bh
11
0Bh
11
0Bh
4
Number of column addresses on
this assembly
10
0Ah
10
0Ah
10
0Ah
5
Number of module banks on this
assembly
1 bank
01h
1 bank
01h
1 bank
01h
6
Data width of this assembly
64 bits
40h
64 bits
40h
64 bits
40h
7
Data width continuation
8
Voltage interface standard of this
assembly
00h
00h
00h
LVTTL
01h
LVTTL
01h
LVTTL
01h
tRAC = 50 ns
tCAC = 13 ns
32h
tRAC = 60 ns
tCAC = 15 ns
3Ch
0Fh
tRAC = 70 ns
tCAC = 18 ns
46h
0Dh
Non-Parity
00h
Non-Parity
00h
Non-Parity
00h
15.6 µs
00h
15.6 µs
00h
15.6 µs
00h
x8
08h
x8
08h
x8
08h
N/A
00h
N/A
00h
N/A
00h
9
RASx access time of module
10
CASx access time of module
11
DIMM configuration type
(non-parity, parity, ECC)
12
Refresh rate / type
13
DRAM width, primary DRAM
14
Error-checking SDRAM data width
62
SPD revision
Rev. 1
01h
Rev. 1
01h
Rev. 1
01h
63
Checksum for bytes 0 −62
41
29h
53
35h
66
42h
Manufacturer’s JEDEC ID code per
JEP-106E
97h
9700...00h
97h
9700...00h
97h
9700...00h
64−71
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
12h
15
SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998
serial presence detect (continued)
Table 2. Serial Presence Detect Data for the TM2EP64DxN (Continued)
BYTE
NO.
’2EP64DxN-50
FUNCTION DESCRIBED
ITEM
DATA
’2EP64DxN-60
ITEM
DATA
’2EP64DxN-70
ITEM
Manufacturing location†
TBD
TBD
TBD
Manufacturer’s part number†
Die revision code†
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
93−94
PCB revision code†
Manufacturing date†
TBD
TBD
TBD
95−98
Assembly serial number†
TBD
TBD
TBD
99−125
TBD
TBD
TBD
126−127
Manufacturer specific data†
Vendor specific data†
TBD
TBD
TBD
128−166
System integrator’s specific data‡
TBD
TBD
TBD
72
73−90
91
92
167−255 Open
† TBD indicates values are determined at manufacturing time and are module dependent.
‡ These TBD values are determined and programmed by the customer (optional).
16
•
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•
DATA
SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998
serial presence detect (continued)
Table 3. Serial Presence Detect Data for the TM2EP72DxN
BYTE
NO.
’2EP72DxN-50
FUNCTION DESCRIBED
’2EP72DxN-60
’2EP72DxN-70
ITEM
DATA
ITEM
DATA
ITEM
DATA
0
Defines number of bytes written
into serial memory during module
manufacturing
128 bytes
80h
128 bytes
80h
128 bytes
80h
1
Total number of bytes of SPD
memory device
256 bytes
08h
256 bytes
08h
256 bytes
08h
2
Fundamental memory type (FPM,
EDO, SDRAM)
EDO
02h
EDO
02h
EDO
02h
3
Number of row addresses on this
assembly
11
0Bh
11
0Bh
11
0Bh
4
Number of column addresses on
this assembly
10
0Ah
10
0Ah
10
0Ah
5
Number of module banks on this
assembly
1 bank
01h
1 bank
01h
1 bank
01h
6
Data width of this assembly
72 bits
48h
72 bits
48h
72 bits
48h
7
Data width continuation
8
Voltage interface standard of this
assembly
9
RASx access time of module
10
CASx access time of module
11
DIMM configuration type
(non-parity, parity, ECC)
12
Refresh rate / type
13
DRAM width, primary DRAM
14
Error-checking SDRAM data width
62
SPD revision
63
00h
00h
00h
LVTTL
01h
LVTTL
01h
LVTTL
01h
tRAC = 50 ns
tCAC = 13 ns
32h
3Ch
0Fh
tRAC = 70 ns
tCAC = 18 ns
46h
0Dh
tRAC = 60 ns
tCAC = 15 ns
ECC
02h
ECC
02h
ECC
02h
15.6 µs
00h
15.6 µs
00h
15.6 µs
00h
x8
08h
x8
08h
x8
08h
12h
x8
08h
x8
08h
x8
08h
Rev. 1
01h
Rev. 1
01h
Rev. 1
01h
Checksum for bytes 0 −62
59
3Bh
71
47h
84
54h
Manufacturer’s JEDEC ID code per
JEP-106E
97h
9700...00h
97h
9700...00h
97h
9700...00h
Manufacturing location†
TBD
TBD
TBD
Manufacturer’s part number†
Die revision code†
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
93−94
PCB revision code†
Manufacturing date†
TBD
TBD
TBD
95−98
Assembly serial number†
TBD
TBD
TBD
99−125
TBD
TBD
TBD
126−127
Manufacturer specific data†
Vendor specific data†
TBD
TBD
TBD
128−166
System integrator’s specific data‡
TBD
TBD
TBD
64−71
72
73−90
91
92
167−255 Open
† TBD indicates values are determined at manufacturing time and are module dependent.
‡ These TBD values are determined and programmed by the customer (optional).
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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•
17
SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998
serial presence detect (continued)
Table 4. Serial Presence Detect Data for the TM4EP64DxN
BYTE
NO.
’4EP64DxN-50
FUNCTION DESCRIBED
’4EP64DxN-60
’4EP64DxN-70
ITEM
DATA
ITEM
DATA
ITEM
DATA
0
Defines number of bytes written
into serial memory during module
manufacturing
128 bytes
80h
128 bytes
80h
128 bytes
80h
1
Total number of bytes of SPD
memory device
256 bytes
08h
256 bytes
08h
256 bytes
08h
2
Fundamental memory type (FPM,
EDO, SDRAM)
EDO
02h
EDO
02h
EDO
02h
3
Number of row addresses on this
assembly
11
0Bh
11
0Bh
11
0Bh
4
Number of column addresses on
this assembly
10
0Ah
10
0Ah
10
0Ah
5
Number of module banks on this
assembly
2 banks
02h
2 banks
02h
2 banks
02h
6
Data width of this assembly
64 bits
40h
64 bits
40h
64 bits
40h
7
Data width continuation
8
Voltage interface standard of this
assembly
9
RASx access time of module
10
CASx access time of module
11
DIMM configuration type
(non-parity, parity, ECC)
12
Refresh rate / type
13
DRAM width, primary DRAM
14
Error-checking SDRAM data width
62
SPD revision
63
00h
00h
00h
LVTTL
01h
LVTTL
01h
LVTTL
01h
tRAC = 50 ns
tCAC = 13 ns
32h
3Ch
0Fh
tRAC = 70 ns
tCAC = 18 ns
46h
0Dh
tRAC = 60 ns
tCAC = 15 ns
Non-Parity
00h
Non-Parity
00h
Non-Parity
00h
15.6 µs
00h
15.6 µs
00h
15.6 µs
00h
x8
08h
x8
08h
x8
08h
12h
N/A
00h
N/A
00h
N/A
00h
Rev. 1
01h
Rev. 1
01h
Rev. 1
01h
Checksum for bytes 0 −62
42
2Ah
54
36h
67
43h
Manufacturer’s JEDEC ID code per
JEP-106E
97h
9700...00h
97h
9700...00h
97h
9700...00h
Manufacturing location†
TBD
TBD
TBD
Manufacturer’s part number†
Die revision code†
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
93−94
PCB revision code†
Manufacturing date†
TBD
TBD
TBD
95−98
Assembly serial number†
TBD
TBD
TBD
99−125
TBD
TBD
TBD
126−127
Manufacturer specific data†
Vendor specific data†
TBD
TBD
TBD
128−166
System integrator’s specific data‡
TBD
TBD
TBD
64−71
72
73−90
91
92
167−255 Open
† TBD indicates values are determined at manufacturing time and are module dependent.
‡ These TBD values are determined and programmed by the customer (optional).
18
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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•
SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998
serial presence detect (continued)
Table 5. Serial Presence Detect for the TM4EP72DxN
BYTE
NO.
’4EP72DxN-50
FUNCTION DESCRIBED
’4EP72DxN-60
’4EP72DxN-70
ITEM
DATA
ITEM
DATA
ITEM
DATA
0
Defines number of bytes written
into serial memory during module
manufacturing
128 bytes
80h
128 bytes
80h
128 bytes
80h
1
Total number of bytes of SPD
memory device
256 bytes
08h
256 bytes
08h
256 bytes
08h
2
Fundamental memory type (FPM,
EDO, SDRAM)
EDO
02h
EDO
02h
EDO
02h
3
Number of row addresses on this
assembly
11
0Bh
11
0Bh
11
0Bh
4
Number of column addresses on
this assembly
10
0Ah
10
0Ah
10
0Ah
5
Number of module banks on this
assembly
2 banks
02h
2 banks
02h
2 banks
02h
6
Data width of this assembly
72 bits
48h
72 bits
48h
72 bits
48h
7
Data width continuation
8
Voltage interface standard of this
assembly
9
RASx access time of module
10
CASx access time of module
11
DIMM configuration type
(non-parity, parity, ECC)
12
Refresh rate / type
13
DRAM width, primary DRAM
14
Error-checking SDRAM data width
62
SPD revision
63
00h
00h
00h
LVTTL
01h
LVTTL
01h
LVTTL
01h
tRAC = 50 ns
tCAC = 13 ns
32h
3Ch
0Fh
tRAC = 70 ns
tCAC = 18 ns
46h
0Dh
tRAC = 60 ns
tCAC = 15 ns
ECC
02h
ECC
02h
ECC
02h
15.6 µs
00h
15.6 µs
00h
15.6 µs
00h
x8
08h
x8
08h
x8
08h
12h
x8
08h
x8
08h
x8
08h
Rev. 1
01h
Rev. 1
01h
Rev. 1
01h
Checksum for bytes 0 −62
60
3Ch
72
48h
85
55h
Manufacturer’s JEDEC ID code per
JEP-106E
97h
9700...00h
97h
9700...00h
97h
9700...00h
Manufacturing location†
TBD
TBD
TBD
Manufacturer’s part number†
Die revision code†
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
93−94
PCB revision code†
Manufacturing date†
TBD
TBD
TBD
95−98
Assembly serial number†
TBD
TBD
TBD
99−125
TBD
TBD
TBD
126−127
Manufacturer specific data†
Vendor specific data†
TBD
TBD
TBD
128−166
System integrator’s specific data‡
TBD
TBD
TBD
64−71
72
73−90
91
92
167−255 Open
† TBD indicates values are determined at manufacturing time and are module dependent.
‡ These TBD values are determined and programmed by the customer (optional).
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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•
19
SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998
device symbolization (TM4EP64DPN illustrated)
TM4EP64DPN
-SS
Unbuffered Key Position
3.3-V Voltage Key Position
YY
MM
T
-SS
=
=
=
=
Year Code
Month Code
Assembly Site Code
Speed Code
NOTE A: Location of symbolization may vary.
20
YYMMT
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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•
SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998
MECHANICAL DATA
BR (R-PDIM-N168)
DUAL IN-LINE MEMORY MODULE
5.255 (133,48)
5.245 (133,22)
Notch 0.157 (4,00) x 0.122 (3,10) Deep
2 Places
0.039 (1,00) TYP
0.125 (3,18)
(Note D)
0.054 (1,37)
0.046 (1,17)
Notch 0.079 (2,00) x 0.122 (3,10) Deep
2 Places
0.050 (1,27)
0.014 (0,35) MAX
0.118 (3,00) TYP
0.125 (3,18)
0.700 (17,78) TYP
0.118 (3,00) DIA
2 Places
1.005 (25,53)
0.995 (25,27)
0.106 (2,70) MAX
0.157 (4,00) MAX
(For Double Sided DIMM Only)
4088180/A 07/97
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Falls within JEDEC MO-161
Dimension includes de-panelization variations; applies between notch and tab edge.
Outline may vary above notches to allow router/panelization irregularities.
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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•
21
SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998
D Organization
D
D
D
D
D
D
D JEDEC 168-Pin Dual-In-Line Memory
− TM2EP64DxN . . . 2 097 152 × 64 Bits
− TM2EP72DxN . . . 2 097 152 × 72 Bits
− TM4EP64DxN . . . 4 194 304 × 64 Bits
− TM4EP72DxN . . . 4 194 304 × 72 Bits
Single 3.3-V Power Supply
(±10% Tolerance)
TM2EP64DxN — Uses Eight 16M-Bit
(2M × 8-Bit) Dynamic Random Access
Memories (DRAMs) in Thin Small-Outline
Package (TSOP), or Small-Outline J-Lead
Package (SOJ)
TM2EP72DxN — Uses Nine 16M-Bit
(2M × 8-Bit) DRAMs in TSOP, or SOJ
TM4EP64DxN — Uses 16 16M-Bit
(2M × 8-Bit) DRAMs in TSOP, or SOJ
TM4EP72DxN — Uses 18 16M-Bit
(2M × 8-Bit) DRAMs in TSOP, or SOJ
Performance ranges
’xEPxxDxN-50
’xEPxxDxN-60
’xEPxxDxN-70
ACCESS ACCESS ACCESS
TIME
TIME
TIME
tRAC
tCAC
tAA
MAX
MAX
MAX
50 ns
13 ns
25 ns
60 ns
15 ns
30 ns
70 ns
18 ns
35 ns
D
D
D
D
D
D
D
Module (DIMM) Without Buffer for Use With
Socket
High-Speed, Low-Noise LVTTL Interface
Long Refresh Period: 32 ms (2 048 Cycles)
3-State Output
Extended-Data-Out (EDO) Operation With
CAS-Before-RAS (CBR), RAS-Only, and
Hidden Refresh
Serial Presence Detect (SPD) Using
EEPROM
Ambient Air Temperature Range
0°C to 70°C
Gold-Plated Contacts
EDO
CYCLE
tHPC
MIN
20 ns
25 ns
30 ns
description
The TM2EP64DPN is a 16M-byte, 168-pin, dual-in-line memory module (DIMM). The DIMM is composed of
eight TMS427809A, 2 097 152 byte × 8-bit 2K-refresh EDO DRAMs, each in a 400-mil, 28-pin plastic TSOP
(DGC suffix) mounted on a substrate with decoupling capacitors. See the TMS427809A data sheet (literature
number SMKS887). The TM2EP64DJN is available with an SOJ package (DZ suffix).
The TM2EP72DPN is a 16M-byte, 168-pin DIMM. The DIMM is composed of nine TMS427809A,
2 097 152 byte × 8-bit 2K-refresh EDO DRAMs, mounted on a substrate with decoupling capacitors. See the
TMS427809A data sheet (literature number SMKS887). The TM2EP72DJN is available with an SOJ package
(DZ suffix).
The TM4EP64DPN is a 32M-byte, 168-pin, dual-in-line memory module (DIMM). The DIMM is composed of
sixteen TMS427809A, 2 097 152 × 8-bit 2K-refresh EDO DRAMs, mounted on a substrate with decoupling
capacitors. The TM4EP64DJN is available with an SOJ package (DZ suffix).
The TM4EP72DPN is a 32M-byte, 168-pin DIMM. The DIMM is composed of 18 TMS427809A, 2097152 × 8-bit
2K-refresh EDO DRAMs, mounted on a substrate with decoupling capacitors. See the TMS427809A data sheet
(literature number SMKS887). The TM4EP72DJN is available with an SOJ package (DZ suffix).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1998, Texas Instruments Incorporated
! "#$ ! %#&'" ($)
(#"! " !%$""! %$ *$ $! $+! !#$!
!(( ,-) (#" %"$!!. ($! $"$!!'- "'#($
$!. '' %$$!)
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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•
23
SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998
operation
The TMxEPxxDxN DIMMs operate as displayed in Table 1.
Table 1. TMxEPxxDxN DIMM Device Table
24
DIMM
DEVICE AND QUANTITY ( )
TM2EP64DxN
TMS427809A (8)
TM2EP72DxN
TMS427809A (9)
TM4EP64DxN
TMS427809A (16)
TM4EP72DxN
TMS427809A (18)
Connected as shown in the functional
block diagram.
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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•
SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998
DUAL-IN-LINE MEMORY MODULE
( TOP VIEW )
TM2EP64DPN
( SIDE VIEW )
TM4EP72DPN
( SIDE VIEW )
PIN NOMENCLATURE
A[0:10]
A[0:9]
DQ[0:63]
CB[0:7]
CAS[0:7]
RAS[0:3]
WE0 and WE2
OE0 and OE2
SA[0:2]
1
10
SDA
SCL
NC
VDD
VSS
11
Row Address Inputs
Column Address Inputs
Data In / Data Out
Check-Bit In / Check-Bit Out
Column-Address Strobe
Row-Address Strobe
Write Enable
Output Enable
Serial Presence Detect (SPD)
Device Add Input
SPD Address / Data
SPD Clock
No-Connect Pin
3.3-V Supply
Ground
40
41
84
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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•
25
SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998
Pin Assignments
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
PIN
NO.
NAME
NO.
1
43
2
VSS
DQ0
3
DQ1
4
NO.
85
44
VSS
OE2
45
RAS2
DQ2
46
5
DQ3
6
7
VDD
DQ4
8
DQ5
9
PIN
NAME
NO.
PIN
NAME
127
86
VSS
DQ32
128
VSS
NC
87
DQ33
129
RAS3
CAS2
88
DQ34
130
CAS6
47
CAS3
89
DQ35
131
CAS7
48
WE2
90
132
NC
49
91
133
50
VDD
NC
VDD
DQ36
92
DQ37
134
VDD
NC
DQ6
51
NC
93
DQ38
135
NC
10
DQ7
52
CB2
94
DQ39
136
CB6
11
DQ8
53
CB3
95
DQ40
137
CB7
12
VSS
DQ9
54
97
VSS
DQ41
138
55
VSS
DQ16
96
13
139
VSS
DQ48
14
DQ10
56
DQ17
98
DQ42
140
DQ49
15
DQ11
57
DQ18
99
DQ43
141
DQ50
16
DQ12
58
DQ19
100
DQ44
142
DQ51
17
DQ13
59
101
DQ45
143
18
60
102
144
61
NC
103
VDD
DQ46
VDD
DQ52
19
VDD
DQ14
VDD
DQ20
145
NC
20
DQ15
62
NC
104
DQ47
146
NC
21
CB0
63
NC
105
CB4
147
NC
22
CB1
64
106
CB5
148
23
VSS
NC
65
VSS
DQ21
107
149
66
DQ22
108
VSS
NC
VSS
DQ53
150
DQ54
25
NC
67
DQ23
109
NC
151
DQ55
26
68
111
VDD
NC
152
69
VSS
DQ24
110
27
VDD
WE0
153
VSS
DQ56
28
CAS0
70
DQ25
112
CAS4
154
DQ57
29
CAS1
71
DQ26
113
CAS5
155
DQ58
30
RAS0
72
DQ27
114
RAS1
156
DQ59
31
OE0
73
115
NC
157
32
74
116
VDD
DQ60
75
DQ29
117
VSS
A1
158
33
VSS
A0
VDD
DQ28
159
DQ61
34
A2
76
DQ30
118
A3
160
DQ62
35
A4
77
DQ31
119
A5
161
DQ63
36
A6
78
A7
162
A8
79
VSS
NC
120
37
121
A9
163
VSS
NC
38
A10
80
NC
122
NC
164
NC
39
NC
81
NC
123
NC
165
SA0
40
82
SDA
124
SA1
83
SCL
125
VDD
NC
166
41
VDD
VDD
167
SA2
42
NC
84
VDD
126
NC
168
VDD
24
26
PIN
NAME
•
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•
SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998
dual-in-line memory module and components
The dual-in-line memory module and components include:
D PC substrate: 1,27 " 0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage
D Bypass capacitors: Multilayer ceramic
D Contact area: Nickel plate and gold plate over copper
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
27
SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998
functional block diagram
The following table shows the four DIMM modules and locations (Ux/UBx) that are used.
COMPONENT TABLE
MODULE
LOCATIONS USED
TM2EP64DxN
U[0:7]
TM2EP72DxN
U[0:8]
TM4EP64DxN
U[0:7], UB[0:7]
TM4EP72DxN
U[0:8], UB[0:8]
RAS0
RAS1
RAS2
RAS3
WE0
OE0
WE0
OE0
WE2
OE2
WE2
OE2
CAS0
DQ[0:7]
CAS1
DQ[8:15]
CAS1
CB[0:7]
CAS2
DQ[16:23]
CAS3
DQ[24:31]
CAS OE W RAS
CAS OE W RAS
DQ[0:7] U0
DQ[0:7] UB0
CAS OE W RAS
CAS OE W RAS
DQ[0:7] U1
DQ[0:7] UB1
CAS OE W RAS
CAS OE W RAS
DQ[0:7] U8
DQ[0:7] UB8
CAS OE W RAS
CAS OE W RAS
DQ[0:7] U2
DQ[0:7] UB2
CAS OE W RAS
CAS OE W RAS
DQ[0:7] U3
DQ[0:7] UB3
CAS4
DQ[32:39]
CAS5
DQ[40:47]
CAS6
DQ[48:55]
CAS7
DQ[56:63]
CAS
OE W RAS
CAS OE W RAS
DQ[0:7] U4
DQ[0:7] UB4
CAS
CAS OE W RAS
OE W RAS
DQ[0:7] U5
DQ[0:7] UB5
CAS
CAS OE W RAS
OE W RAS
DQ[0:7] U6
DQ[0:7] UB6
CAS
CAS OE W RAS
OE W RAS
DQ[0:7] UB7
DQ[0:7] U7
A[0: 10]
A[0 : 10] : U[0:8], UB[0:8]
SPD EEPROM
SCL
SDA
Legend: SPD = Serial Presence Detect
A0
A1
A2
SA0
SA1
SA2
VDD
VSS
28
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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•
U[0:8], UB[0:8]
Two 0.1 µF
(minimum) per
DRAM
U[0:8], UB[0:8]
SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998
absolute maximum ratings over ambient temperature range (unless otherwise noted)†
Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.5 V to 4.6 V
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation: TM2EP64DxN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 W
TM2EP72DxN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 W
TM4EP64DxN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 W
TM4EP72DxN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 W
Ambient temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 55°C to 125°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
recommended operating conditions
MIN
NOM
MAX
UNIT
3
3.3
3.6
V
VDD
VSS
Supply voltage
VIH
VIH −SPD
High-level input voltage
2
High-level input voltage for the SPD device
2
VIL
TA
Low-level input voltage
Supply voltage
0
V
VDD + 0.3
5.5
V
V
−0.3
0.8
V
0
70
°C
Ambient temperature
capacitance over recommended ranges of supply voltage and ambient temperature, f = 1 MHz
(see Note 2)
’2EP64DxN
PARAMETER
MIN
’2EP72DxN
MAX
MIN
MAX
’4EP64DxN
MIN
MAX
’4EP72DxN
MIN
MAX
UNIT
Ci(A)
Input capacitance, A0 −A10
42
47
82
92
pF
Ci(OE)
Input capacitance, OEx
30
37
58
72
pF
Ci(CAS)
Input capacitance, CASx
9
16
16
30
pF
Ci(RAS)
Input capacitance, RASx
30
37
30
37
pF
Ci(W)
Input capacitance, WEx
30
37
38
37
pF
Co
Output capacitance
9
9
16
16
pF
Ci/o(SDA)
Input/output capacitance, SDA input
9
9
9
9
pF
Ci(SPD)
Input capacitance, SA0,SA1,SA2,SCL inputs
7
7
7
7
pF
NOTE 2: VDD = NOM supply voltage ± 10%, and the bias on pins under test is 0 V.
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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•
29
SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998
electrical characteristics over recommended ranges of supply voltage and ambient temperature
(unless otherwise noted)
TM2EP64DxN
PARAMETER
’2EP64DxN-50
TEST CONDITIONS†
MIN
’2EP64DxN-60
MAX
MIN
’2EP64DxN-70
MAX
MIN
MAX
UNIT
High-level
output
voltage
IOH = − 2 mA
LVTTL
VOH
IOH = − 100 µA
LVCMOS
Low-level
output
voltage
IOL = 2 mA
LVTTL
0.4
0.4
0.4
VOL
IOL = 100 µA
LVCMOS
0.2
0.2
0.2
II
Input current
(leakage)
VDD = 3.6 V,
VI = 0 V to 3.9 V,
All others = 0 V to VDD
± 10
± 10
± 10
µA
IO
Output
current
(leakage)
VDD = 3.6 V,
CASx high
VO = 0 V to VDD,
± 10
± 10
± 10
µA
ICC1‡§
Read- or
write-cycle
current
VDD = 3.6 V,
Minimum cycle
960
800
720
mA
VIH = 2 V (LVTTL),
After one memory cycle,
RASx and CASx high
16
16
16
mA
VIH = VDD − 0.2 V
(LVCMOS),
After one memory cycle,
RASx and CASx high
8
8
8
mA
ICC2
Standby
current
2.4
2.4
2.4
V
VDD −0.2
VDD −0.2
VDD −0.2
V
ICC3‡§
Average
refresh
current
(RAS-only
refresh
or CBR)
VDD = 3.6 V,
Minimum cycle,
RASx cycling,
CASx high (RAS-only refresh),
RASx low after CASx low (CBR)
960
800
720
mA
ICC4‡¶
Average
EDO current
VDD = 3.6 V,
RASx low,
880
720
640
mA
tHPC = MIN,
CASx cycling
† For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements.
‡ Measured with outputs open
§ Measured with a maximum of one address change while RASx = VIL
¶ Measured with a maximum of one address change during each EDO cycle, tHPC
30
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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•
SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998
electrical characteristics over recommended ranges of supply voltage and ambient temperature
(unless otherwise noted) (continued)
TM2EP72DxN
PARAMETER
’2EP72DxN-50
TEST CONDITIONS†
MIN
’2EP72DxN-60
MAX
MIN
’2EP72DxN-70
MAX
MIN
MAX
UNIT
High-level
output
voltage
IOH = − 2 mA
LVTTL
VOH
IOH = − 100 µA
LVCMOS
Low-level
output
voltage
IOL = 2 mA
LVTTL
0.4
0.4
0.4
VOL
IOL = 100 µA
LVCMOS
0.2
0.2
0.2
II
Input current
(leakage)
VDD = 3.6 V,
VI = 0 V to 3.9 V,
All others = 0 V to VDD
± 10
± 10
± 10
µA
IO
Output
current
(leakage)
VDD = 3.6 V,
CASx high
VO = 0 V to VDD,
± 10
± 10
± 10
µA
ICC1‡§
Read- or
write-cycle
current
VDD = 3.6 V,
Minimum cycle
976
816
736
mA
VIH = 2 V (LVTTL),
After one memory cycle,
RASx and CASx high
18
18
18
mA
VIH = VDD − 0.2 V
(LVCMOS),
After one memory cycle,
RASx and CASx high
9
9
9
mA
ICC2
Standby
current
2.4
2.4
2.4
V
VDD −0.2
VDD −0.2
VDD −0.2
V
ICC3‡§
Average
refresh
current
(RASx-only
refresh
or CBR)
VDD = 3.6 V,
Minimum cycle,
RASx cycling,
CASx high (RAS-only refresh),
RASx low after CASx low (CBR)
976
816
736
mA
ICC4‡¶
Average
EDO current
VDD = 3.6 V,
RASx low,
990
810
720
mA
tHPC = MIN,
CASx cycling
† For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements.
‡ Measured with outputs open
§ Measured with a maximum of one address change while RASx = VIL
¶ Measured with a maximum of one address change during each EDO cycle, tHPC
•
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•
31
SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998
electrical characteristics over recommended ranges of supply voltage and ambient temperature
(unless otherwise noted) (continued)
TM4EP64DxN
PARAMETER
’4EP64DxN-50
TEST CONDITIONS†
MIN
’4EP64DxN-60
MAX
MIN
MAX
’4EP64DxN-70
MIN
MAX
UNIT
High-level
output
voltage
IOH = − 2 mA
LVTTL
VOH
IOH = − 100 µA
LVCMOS
Low-level
output
voltage
IOL = 2 mA
LVTTL
0.4
0.4
0.4
VOL
IOL = 100 µA
LVCMOS
0.2
0.2
0.2
II
Input current
(leakage)
VDD = 3.6 V,
VI = 0 V to 3.9 V,
All others = 0 V to VDD
± 20
± 20
± 20
µA
IO
Output
current
(leakage)
VDD = 3.6 V,
CASx high
VO = 0 V to VDD,
± 20
± 20
± 20
µA
ICC1‡§
Read- or
write-cycle
current
VDD = 3.6 V,
Minimum cycle
976
816
736
mA
VIH = 2 V (LVTTL),
After one memory cycle,
RASx and CASx high
32
32
32
mA
VIH = VDD − 0.2 V
(LVCMOS),
After one memory cycle,
RASx and CASx high
16
16
16
mA
ICC2
Standby
current
2.4
2.4
2.4
V
VDD −0.2
VDD−0.2
VDD −0.2
V
ICC3‡§
Average
refresh
current
(RASx-only
refresh
or CBR)
VDD = 3.6 V,
Minimum cycle,
RASx cycling,
CASx high (RAS-only refresh),
RASx low after CASx low (CBR)
976
816
736
mA
ICC4‡¶
Average
EDO current
VDD = 3.6 V,
RASx low,
896
736
656
mA
tHPC = MIN,
CASx cycling
† For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements.
‡ Measured with outputs open
§ Measured with a maximum of one address change while RASx = VIL
¶ Measured with a maximum of one address change during each EDO cycle, tHPC
32
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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•
SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998
electrical characteristics over recommended ranges of supply voltage and ambient temperature
(unless otherwise noted) (continued)
TM4EP72DxN
PARAMETER
’4EP72DxN-50
TEST CONDITIONS†
MIN
’4EP72DxN-60
MAX
MIN
MAX
’4EP72DxN-70
MIN
MAX
UNIT
High-level
output
voltage
IOH = − 2 mA
LVTTL
VOH
IOH = − 100 µA
LVCMOS
Low-level
output
voltage
IOL = 2 mA
LVTTL
0.4
0.4
0.4
VOL
IOL = 100 µA
LVCMOS
0.2
0.2
0.2
II
Input current
(leakage)
VDD = 3.6 V,
VI = 0 V to 3.9 V,
All others = 0 V to VDD
± 20
± 20
± 20
µA
IO
Output
current
(leakage)
VDD = 3.6 V,
CASx high
VO = 0 V to VDD,
± 20
± 20
± 20
µA
ICC1‡§
Read- or
write-cycle
current
VDD = 3.6 V,
Minimum cycle
1098
918
828
mA
VIH = 2 V (LVTTL),
After one memory cycle,
RASx and CASx high
36
36
36
mA
VIH = VDD − 0.2 V
(LVCMOS),
After one memory cycle,
RASx and CASx high
18
18
18
mA
ICC2
Standby
current
2.4
2.4
2.4
V
VDD −0.2
VDD −0.2
VDD −0.2
V
ICC3‡§
Average
refresh
current
(RASx-only
refresh
or CBR)
VDD = 3.6 V,
Minimum cycle,
RASx cycling,
CASx high (RAS-only refresh),
RASx low after CASx low (CBR)
1098
918
828
mA
ICC4‡¶
Average
EDO current
VDD = 3.6 V,
RASx low,
1008
828
738
mA
tHPC = MIN,
CASx cycling
† For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements.
‡ Measured with outputs open
§ Measured with a maximum of one address change while RASx = VIL
¶ Measured with a maximum of one address change during each EDO cycle, tHPC
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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•
33
SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998
switching characteristics over recommended ranges of supply voltage and ambient temperature
(see Note 3)
’xEP64DxN-50
’xEP72DxN-50
PARAMETER
MIN
MAX
’xEP64DxN-60
’xEP72DxN-60
MIN
MAX
’xEP64DxN-70
’xEP72DxN-70
MIN
UNIT
MAX
tAA
tCAC
Access time from column address (see Note 4)
25
30
35
ns
Access time from CASx (see Note 4)
13
15
18
ns
tCPA
tRAC
Access time from CASx precharge (see Note 4)
28
35
40
ns
Access time from RASx (see Note 4)
50
60
70
ns
tOEA
tCLZ
Access time from OEx (see Note 4)
18
ns
Delay time, CASx to output in low impedance
0
tREZ
tCEZ
Output buffer turn off delay from RASx (see Note 5)
3
13
3
15
3
18
ns
Output buffer turn off delay from CASx (see Note 5)
3
13
3
15
3
18
ns
tOEZ
tWEZ
Output buffer turn off delay from OEx (see Note 5)
3
13
3
15
3
18
ns
Output buffer turn off delay from WEx (see Note 5)
3
13
3
15
3
18
ns
13
15
0
0
ns
NOTES: 3. With ac parameters, it is assumed that tT = 2 ns.
4. Access times are measured with output reference levels of VOH = 2 V and VOL = 0.8 V.
5. The maximum values of tREZ, tCEZ, tOEZ, and tWEZ are specified when the outputs are no longer driven. Data-in should not be driven
until one of the applicable maximum values is satisfied.
EDO timing requirements (see Note 3)
’xEP64DxN-50
’xEP72DxN-50
MIN
MAX
’xEP64DxN-60
’xEP72DxN-60
MIN
MAX
’xEP64DxN-70
’xEP72DxN-70
MIN
UNIT
MAX
tHPC
tPRWC
Cycle time, EDO page mode, read-write
20
25
30
ns
Cycle time, EDO read-write
57
68
78
ns
tCSH
tCHO
Delay time, RASx active to CASx precharge
40
48
58
ns
Hold time, OEx from CASx
7
10
10
ns
tDOH
tOEP
Hold time, output from CASx
5
5
5
ns
Precharge time, OEx
5
5
5
ns
tCAS
tWPE
Pulse duration, CASx active
8
Pulse duration, WEx active (output disable only)
7
7
7
ns
tCP
tOCH
Pulse duration, CASx precharge
8
10
10
ns
Setup time, OEx before CASx
8
10
10
ns
5
5
5
ns
tOEP
Precharge time, OEx
NOTE 3: With ac parameters, it is assumed that tT = 2 ns.
34
•
10 000
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
10
10 000
12
10 000
ns
SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998
ac timing requirements
’xEP64DxN-50
’xEP72DxN-50
’xEP64DxN-60
’xEP72DxN-60
’xEP64DxN-70
’xEP72DxN-70
MIN
MIN
MIN
MAX
MAX
tRC
tRWC
Cycle time, random read or write
tRASP
tRAS
Pulse duration, RASx active, fast page mode (see Note 6)
50
100 000
60
100 000
70
100 000
ns
Pulse duration, RASx active, non-page mode (see Note 6)
50
10 000
60
10 000
70
10 000
ns
tRP
tWP
Pulse duration, RASx precharge
30
tRASS
tRPS
Pulse duration, RASx active, self refresh (see Note 7)
tASC
tASR
Cycle time, read-write
104
124
135
160
40
ns
ns
50
ns
ns
8
10
10
100
100
100
ms
90
110
130
ns
Setup time, column address
0
0
0
ns
Setup time, row address
0
0
0
ns
tDS
tRCS
Setup time, data in (see Note 8)
0
0
0
ns
Setup time, read command
0
0
0
ns
tCWL
tRWL
Setup time, write command before CASx precharge
8
10
12
ns
Setup time, write command before RASx precharge
8
10
12
ns
Setup time, write command before CASx active
(early-write only)
0
0
0
ns
tWCS
Pulse duration, write command
84
111
UNIT
MAX
Pulse duration, RASx precharge after self refresh
tWRP
tCSR
Setup time, WEx high before RASx low (CBR refresh only)
10
10
10
ns
Setup time, CASx referenced to RASx ( CBR refresh only )
5
5
5
ns
tCAH
tDH
Hold time, column address
8
10
12
ns
Hold time, data in (see Note 8)
8
10
12
ns
tRAH
tRCH
Hold time, row address
8
10
10
ns
Hold time, read command referenced to CASx (see Note 9)
0
0
0
ns
tRRH
Hold time, read command referenced to RASx (see Note 9)
0
0
0
ns
tWCH
Hold time, write command during CASx active
( early-write only )
8
10
12
ns
tROH
tWRH
Hold time, RASx referenced to OEx
8
10
10
ns
Hold time, WEx high after RASx low (CBR refresh only)
10
10
10
ns
tCHR
tOEH
Hold time, CASx referenced to RASx ( CBR refresh only )
10
10
10
ns
Hold time, OEx command
13
15
18
ns
tRHCP
tCHS
Hold time, RASx active from CASx precharge
28
35
40
ns
− 50
− 50
− 50
ns
42
49
57
ns
tAWD
Hold time, CASx referenced to RASx (self refresh only)
Delay time, column address to write command
( read-write only )
tCRP
Delay time, CASx precharge to RASx
5
5
5
ns
NOTES: 6. In a read-write cycle, tRWD and tRWL must be observed.
7. During the period of 10 µs ≤ tRASS ≤100 µs, the device is in a transition state from normal-operation mode to self-refresh mode.
8. Referenced to the later of CASx or WEx in write operations
9. Either tRRH or tRCH must be satisfied for a read cycle.
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
35
SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998
ac timing requirements (continued)
’xEP64DxN-50
’xEP72DxN-50
’xEP64DxN-60
’xEP72DxN-60
’xEP64DxN-70
’xEP72DxN-70
MIN
MIN
MIN
MAX
MAX
UNIT
MAX
tCWD
tOED
Delay time, CASx to write command ( read-write only )
30
34
40
Delay time, OEx to data in
13
15
18
tRAD
tRAL
Delay time, RASx to column address ( see Note 10)
10
Delay time, column address to RASx precharge
25
30
35
ns
tCAL
Delay time, column address to CASx precharge
18
20
25
ns
tRCD
tRPC
Delay time, RASx to CASx ( see Note 10)
12
tRSH
tRWD
Delay time, CASx active to RASx precharge
tCPW
tREF
tT
Delay time, RASx precharge to CASx
25
37
14
30
45
12
14
ns
35
52
ns
ns
5
5
5
ns
8
10
12
ns
Delay time, RASx to write command (read-write only)
67
79
92
ns
Delay time, CASx precharge to write command
(read-write only)
45
54
62
ns
Refresh time interval
32
Transition time
2
30
NOTE 10: The maximum value is specified only to ensure access time.
36
12
ns
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
32
2
30
2
32
ms
30
ns
SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998
serial presence detect
The serial presence detect (SPD) is contained in a 2K-bit serial EEPROM located on the module. The SPD
nonvolatile EEPROM contains various data such as module configuration, DRAM organization, and timing
parameters (see tables below). Only the first 128 bytes are programmed by Texas Instruments, while the
remaining 128 bytes are available for customer use. Programming is done through an IIC bus using the clock
(SCL) and data (SDA) signals. All Texas Instruments module comply with the current JEDEC SPD Standard.
Please see the Texas Instruments Serial Presence Detect Technical Reference (literature number SMMU001)
for further details.
Tables in this section list the SPD contents as follows:
Table 2 −TM2EP64DxN
Table 4 −TM4EP64DxN
Table 3 −TM2EP72DxN
Table 5 −TM4EP72DxN
Table 2. Serial Presence Detect Data for the TM2EP64DxN
BYTE
NO.
’2EP64DxN-50
FUNCTION DESCRIBED
’2EP64DxN-60
’2EP64DxN-70
ITEM
DATA
ITEM
DATA
ITEM
DATA
0
Defines number of bytes written
into serial memory during module
manufacturing
128 bytes
80h
128 bytes
80h
128 bytes
80h
1
Total number of bytes of SPD
memory device
256 bytes
08h
256 bytes
08h
256 bytes
08h
2
Fundamental memory type (FPM,
EDO, SDRAM)
EDO
02h
EDO
02h
EDO
02h
3
Number of row addresses on this
assembly
11
0Bh
11
0Bh
11
0Bh
4
Number of column addresses on
this assembly
10
0Ah
10
0Ah
10
0Ah
5
Number of module banks on this
assembly
1 bank
01h
1 bank
01h
1 bank
01h
6
Data width of this assembly
64 bits
40h
64 bits
40h
64 bits
40h
7
Data width continuation
8
Voltage interface standard of this
assembly
00h
00h
00h
LVTTL
01h
LVTTL
01h
LVTTL
01h
tRAC = 50 ns
tCAC = 13 ns
32h
tRAC = 60 ns
tCAC = 15 ns
3Ch
0Fh
tRAC = 70 ns
tCAC = 18 ns
46h
0Dh
Non-Parity
00h
Non-Parity
00h
Non-Parity
00h
15.6 µs
00h
15.6 µs
00h
15.6 µs
00h
x8
08h
x8
08h
x8
08h
N/A
00h
N/A
00h
N/A
00h
9
RASx access time of module
10
CASx access time of module
11
DIMM configuration type
(non-parity, parity, ECC)
12
Refresh rate / type
13
DRAM width, primary DRAM
14
Error-checking SDRAM data width
62
SPD revision
Rev. 1
01h
Rev. 1
01h
Rev. 1
01h
63
Checksum for bytes 0 −62
41
29h
53
35h
66
42h
Manufacturer’s JEDEC ID code per
JEP-106E
97h
9700...00h
97h
9700...00h
97h
9700...00h
64−71
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
12h
37
SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998
serial presence detect (continued)
Table 2. Serial Presence Detect Data for the TM2EP64DxN (Continued)
BYTE
NO.
’2EP64DxN-50
FUNCTION DESCRIBED
ITEM
DATA
’2EP64DxN-60
ITEM
DATA
’2EP64DxN-70
ITEM
Manufacturing location†
TBD
TBD
TBD
Manufacturer’s part number†
Die revision code†
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
93−94
PCB revision code†
Manufacturing date†
TBD
TBD
TBD
95−98
Assembly serial number†
TBD
TBD
TBD
99−125
TBD
TBD
TBD
126−127
Manufacturer specific data†
Vendor specific data†
TBD
TBD
TBD
128−166
System integrator’s specific data‡
TBD
TBD
TBD
72
73−90
91
92
167−255 Open
† TBD indicates values are determined at manufacturing time and are module dependent.
‡ These TBD values are determined and programmed by the customer (optional).
38
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
DATA
SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998
serial presence detect (continued)
Table 3. Serial Presence Detect Data for the TM2EP72DxN
BYTE
NO.
’2EP72DxN-50
FUNCTION DESCRIBED
’2EP72DxN-60
’2EP72DxN-70
ITEM
DATA
ITEM
DATA
ITEM
DATA
0
Defines number of bytes written
into serial memory during module
manufacturing
128 bytes
80h
128 bytes
80h
128 bytes
80h
1
Total number of bytes of SPD
memory device
256 bytes
08h
256 bytes
08h
256 bytes
08h
2
Fundamental memory type (FPM,
EDO, SDRAM)
EDO
02h
EDO
02h
EDO
02h
3
Number of row addresses on this
assembly
11
0Bh
11
0Bh
11
0Bh
4
Number of column addresses on
this assembly
10
0Ah
10
0Ah
10
0Ah
5
Number of module banks on this
assembly
1 bank
01h
1 bank
01h
1 bank
01h
6
Data width of this assembly
72 bits
48h
72 bits
48h
72 bits
48h
7
Data width continuation
8
Voltage interface standard of this
assembly
9
RASx access time of module
10
CASx access time of module
11
DIMM configuration type
(non-parity, parity, ECC)
12
Refresh rate / type
13
DRAM width, primary DRAM
14
Error-checking SDRAM data width
62
SPD revision
63
00h
00h
00h
LVTTL
01h
LVTTL
01h
LVTTL
01h
tRAC = 50 ns
tCAC = 13 ns
32h
3Ch
0Fh
tRAC = 70 ns
tCAC = 18 ns
46h
0Dh
tRAC = 60 ns
tCAC = 15 ns
ECC
02h
ECC
02h
ECC
02h
15.6 µs
00h
15.6 µs
00h
15.6 µs
00h
x8
08h
x8
08h
x8
08h
12h
x8
08h
x8
08h
x8
08h
Rev. 1
01h
Rev. 1
01h
Rev. 1
01h
Checksum for bytes 0 −62
59
3Bh
71
47h
84
54h
Manufacturer’s JEDEC ID code per
JEP-106E
97h
9700...00h
97h
9700...00h
97h
9700...00h
Manufacturing location†
TBD
TBD
TBD
Manufacturer’s part number†
Die revision code†
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
93−94
PCB revision code†
Manufacturing date†
TBD
TBD
TBD
95−98
Assembly serial number†
TBD
TBD
TBD
99−125
TBD
TBD
TBD
126−127
Manufacturer specific data†
Vendor specific data†
TBD
TBD
TBD
128−166
System integrator’s specific data‡
TBD
TBD
TBD
64−71
72
73−90
91
92
167−255 Open
† TBD indicates values are determined at manufacturing time and are module dependent.
‡ These TBD values are determined and programmed by the customer (optional).
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
39
SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998
serial presence detect (continued)
Table 4. Serial Presence Detect Data for the TM4EP64DxN
BYTE
NO.
’4EP64DxN-50
FUNCTION DESCRIBED
’4EP64DxN-60
’4EP64DxN-70
ITEM
DATA
ITEM
DATA
ITEM
DATA
0
Defines number of bytes written
into serial memory during module
manufacturing
128 bytes
80h
128 bytes
80h
128 bytes
80h
1
Total number of bytes of SPD
memory device
256 bytes
08h
256 bytes
08h
256 bytes
08h
2
Fundamental memory type (FPM,
EDO, SDRAM)
EDO
02h
EDO
02h
EDO
02h
3
Number of row addresses on this
assembly
11
0Bh
11
0Bh
11
0Bh
4
Number of column addresses on
this assembly
10
0Ah
10
0Ah
10
0Ah
5
Number of module banks on this
assembly
2 banks
02h
2 banks
02h
2 banks
02h
6
Data width of this assembly
64 bits
40h
64 bits
40h
64 bits
40h
7
Data width continuation
8
Voltage interface standard of this
assembly
9
RASx access time of module
10
CASx access time of module
11
DIMM configuration type
(non-parity, parity, ECC)
12
Refresh rate / type
13
DRAM width, primary DRAM
14
Error-checking SDRAM data width
62
SPD revision
63
00h
00h
00h
LVTTL
01h
LVTTL
01h
LVTTL
01h
tRAC = 50 ns
tCAC = 13 ns
32h
3Ch
0Fh
tRAC = 70 ns
tCAC = 18 ns
46h
0Dh
tRAC = 60 ns
tCAC = 15 ns
Non-Parity
00h
Non-Parity
00h
Non-Parity
00h
15.6 µs
00h
15.6 µs
00h
15.6 µs
00h
x8
08h
x8
08h
x8
08h
12h
N/A
00h
N/A
00h
N/A
00h
Rev. 1
01h
Rev. 1
01h
Rev. 1
01h
Checksum for bytes 0 −62
42
2Ah
54
36h
67
43h
Manufacturer’s JEDEC ID code per
JEP-106E
97h
9700...00h
97h
9700...00h
97h
9700...00h
Manufacturing location†
TBD
TBD
TBD
Manufacturer’s part number†
Die revision code†
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
93−94
PCB revision code†
Manufacturing date†
TBD
TBD
TBD
95−98
Assembly serial number†
TBD
TBD
TBD
99−125
TBD
TBD
TBD
126−127
Manufacturer specific data†
Vendor specific data†
TBD
TBD
TBD
128−166
System integrator’s specific data‡
TBD
TBD
TBD
64−71
72
73−90
91
92
167−255 Open
† TBD indicates values are determined at manufacturing time and are module dependent.
‡ These TBD values are determined and programmed by the customer (optional).
40
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998
serial presence detect (continued)
Table 5. Serial Presence Detect for the TM4EP72DxN
BYTE
NO.
’4EP72DxN-50
FUNCTION DESCRIBED
’4EP72DxN-60
’4EP72DxN-70
ITEM
DATA
ITEM
DATA
ITEM
DATA
0
Defines number of bytes written
into serial memory during module
manufacturing
128 bytes
80h
128 bytes
80h
128 bytes
80h
1
Total number of bytes of SPD
memory device
256 bytes
08h
256 bytes
08h
256 bytes
08h
2
Fundamental memory type (FPM,
EDO, SDRAM)
EDO
02h
EDO
02h
EDO
02h
3
Number of row addresses on this
assembly
11
0Bh
11
0Bh
11
0Bh
4
Number of column addresses on
this assembly
10
0Ah
10
0Ah
10
0Ah
5
Number of module banks on this
assembly
2 banks
02h
2 banks
02h
2 banks
02h
6
Data width of this assembly
72 bits
48h
72 bits
48h
72 bits
48h
7
Data width continuation
8
Voltage interface standard of this
assembly
9
RASx access time of module
10
CASx access time of module
11
DIMM configuration type
(non-parity, parity, ECC)
12
Refresh rate / type
13
DRAM width, primary DRAM
14
Error-checking SDRAM data width
62
SPD revision
63
00h
00h
00h
LVTTL
01h
LVTTL
01h
LVTTL
01h
tRAC = 50 ns
tCAC = 13 ns
32h
3Ch
0Fh
tRAC = 70 ns
tCAC = 18 ns
46h
0Dh
tRAC = 60 ns
tCAC = 15 ns
ECC
02h
ECC
02h
ECC
02h
15.6 µs
00h
15.6 µs
00h
15.6 µs
00h
x8
08h
x8
08h
x8
08h
12h
x8
08h
x8
08h
x8
08h
Rev. 1
01h
Rev. 1
01h
Rev. 1
01h
Checksum for bytes 0 −62
60
3Ch
72
48h
85
55h
Manufacturer’s JEDEC ID code per
JEP-106E
97h
9700...00h
97h
9700...00h
97h
9700...00h
Manufacturing location†
TBD
TBD
TBD
Manufacturer’s part number†
Die revision code†
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
93−94
PCB revision code†
Manufacturing date†
TBD
TBD
TBD
95−98
Assembly serial number†
TBD
TBD
TBD
99−125
TBD
TBD
TBD
126−127
Manufacturer specific data†
Vendor specific data†
TBD
TBD
TBD
128−166
System integrator’s specific data‡
TBD
TBD
TBD
64−71
72
73−90
91
92
167−255 Open
† TBD indicates values are determined at manufacturing time and are module dependent.
‡ These TBD values are determined and programmed by the customer (optional).
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
41
SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998
device symbolization (TM4EP64DPN illustrated)
TM4EP64DPN
-SS
Unbuffered Key Position
3.3-V Voltage Key Position
YY
MM
T
-SS
=
=
=
=
Year Code
Month Code
Assembly Site Code
Speed Code
NOTE A: Location of symbolization may vary.
42
YYMMT
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998
MECHANICAL DATA
BR (R-PDIM-N168)
DUAL IN-LINE MEMORY MODULE
5.255 (133,48)
5.245 (133,22)
Notch 0.157 (4,00) x 0.122 (3,10) Deep
2 Places
0.039 (1,00) TYP
0.125 (3,18)
(Note D)
0.054 (1,37)
0.046 (1,17)
Notch 0.079 (2,00) x 0.122 (3,10) Deep
2 Places
0.050 (1,27)
0.014 (0,35) MAX
0.118 (3,00) TYP
0.125 (3,18)
0.700 (17,78) TYP
0.118 (3,00) DIA
2 Places
1.005 (25,53)
0.995 (25,27)
0.106 (2,70) MAX
0.157 (4,00) MAX
(For Double Sided DIMM Only)
4088180/A 07/97
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Falls within JEDEC MO-161
Dimension includes de-panelization variations; applies between notch and tab edge.
Outline may vary above notches to allow router/panelization irregularities.
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