SMMS705A − FEBRUARY 1998 − REVISED APRIL 1998 D Organization D D D D D D D High-Speed, Low-Noise Low-Voltage TTL − TM2SR72EPH . . . 2 097 152 x 72 Bits − TM4SR72EPH . . . 4 194 304 x 72 Bits Single 3.3-V Power Supply (±10% Tolerance) Designed for 66-MHz 4-Clock Systems JEDEC 168-Pin Dual-In-Line Memory Module (DIMM) Without Buffer for Use With Socket TM2SR72EPH — Uses Nine 16M-Bit Synchronous Dynamic RAMs (SDRAMs) (2M × 8-Bit) in Plastic Thin Small-Outline Packages (TSOPs) TM4SR72EPH — Uses 18 16M-Bit SDRAMs (2M × 8-Bit) in Plastic TSOPs Performance Ranges: SYNCHRONOUS CLOCK CYCLE TIME tCK3 tCK2 (CL = 3)† (CL = 2) ’xSR72EPH-10 10 ns 15 ns ACCESS TIME (CLOCK TO OUTPUT) tAC3 tAC2 (CL = 3) (CL = 2) 7.5 ns 7.5 ns D D D D D D D D D (LVTTL) Interface Byte-Read/Write Capability Read Latencies 2 and 3 Supported Support Burst-Interleave and Burst-Interrupt Operations Burst Length Programmable to 1, 2, 4, and 8 Two Banks for On-Chip Interleaving (Gapless Access) Ambient Temperature Range 0°C to 70°C Gold-Plated Contacts Pipeline Architecture Serial Presence Detect (SPD) Using EEPROM REFRESH INTERVAL 64 ms † CL = CAS latency description The TM2SR72EPH is a 16M-byte, 168-pin dual-in-line memory module (DIMM). The DIMM is composed of nine TMS626812BDGE, 2 097 152 × 8-bit SDRAMs, each in a 400-mil, 44-pin plastic thin small-outline package (TSOP) mounted on a substrate with decoupling capacitors. See the TMS626812B data sheet (literature number SMOS693). The TM4SR72EPH is a 32M-byte, 168-pin DIMM. The DIMM is composed of eighteen TMS626812BDGE, 2 097 152 × 8-bit SDRAMs, each in a 400-mil, 44-pin plastic TSOP mounted on a substrate with decoupling capacitors. See the TMS626812B data sheet (literature number SMOS693). operation The TM2SR72EPH operates as nine TMS626812BDGE devices that are connected as shown in the TM2SR72EPH functional block diagram. The TM4SR72EPH operates as eighteen TMS626812BDGE devices connected as shown in the TM4SR72EPH functional block diagram. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1998, Texas Instruments Incorporated !"#$ % &'!!($ #% )'*+&#$ ,#$(!,'&$% &!" $ %)(&&#$% )(! $.( $(!"% (/#% %$!'"($% %$#,#!, 0#!!#$1- !,'&$ )!&(%%2 ,(% $ (&(%%#!+1 &+',( $(%$2 #++ )#!#"($(!%- POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 1 SMMS705A − FEBRUARY 1998 − REVISED APRIL 1998 DUAL-IN-LINE MEMORY MODULE ( TOP VIEW ) TM2SR72EPH ( SIDE VIEW ) TM4SR72EPH ( SIDE VIEW ) PIN NOMENCLATURE A[0:10] A[0:8] A11/BA0 CAS CB[0:7] CKE[0:1] CK[0:3] DQ[0:63] DQMB[0:7] 1 10 NC RAS S[0:3] SA[0:2] 11 SCL SDA VDD VSS WE 40 41 84 2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Row-Address Inputs Column-Address Inputs Bank-Select Zero Column-Address Strobe Data In / Data Out Clock Enable System Clock Data In / Data Out Data-In / Data-Out Mask Enable No Connect Row-Address Strobe Chip-Select Serial Presence Detect (SPD) Device Address Input SPD Clock SPD Address / Data 3.3-V Supply Ground Write Enable SMMS705A − FEBRUARY 1998 − REVISED APRIL 1998 Pin Assignments PIN NO. NAME NO. 1 43 2 VSS DQ0 3 DQ1 4 PIN NAME NO. 85 44 VSS NC 45 S2 DQ2 46 5 DQ3 6 7 VDD DQ4 8 DQ5 9 PIN NAME NO. PIN NAME 127 86 VSS DQ32 87 DQ33 129 S3 DQMB2 88 DQ34 130 DQMB6 47 DQMB3 89 DQ35 131 DQMB7 48 NC 90 132 NC 49 91 133 50 VDD NC VDD DQ36 92 DQ37 134 VDD NC DQ6 51 NC 93 DQ38 135 NC 10 DQ7 52 CB2 94 DQ39 136 CB6 11 DQ8 53 CB3 95 DQ40 137 CB7 12 VSS DQ9 54 97 VSS DQ41 138 55 VSS DQ16 96 13 139 VSS DQ48 14 DQ10 56 DQ17 98 DQ42 140 DQ49 15 DQ11 57 DQ18 99 DQ43 141 DQ50 16 DQ12 58 DQ19 100 DQ44 142 DQ51 17 DQ13 59 101 DQ45 143 18 60 102 144 61 NC 103 VDD DQ46 VDD DQ52 19 VDD DQ14 VDD DQ20 145 NC 20 DQ15 62 NC 104 DQ47 146 NC 21 CB0 63 CKE1 105 CB4 147 NC 22 CB1 64 106 CB5 148 23 VSS NC 65 VSS DQ21 107 149 66 DQ22 108 VSS NC VSS DQ53 150 DQ54 25 NC 67 DQ23 109 NC 151 DQ55 26 68 111 VDD CAS 152 69 VSS DQ24 110 27 VDD WE 153 VSS DQ56 28 DQMB0 70 DQ25 112 DQMB4 154 DQ57 29 DQMB1 71 DQ26 113 DQMB5 155 DQ58 30 S0 72 DQ27 114 S1 156 DQ59 31 NC 73 115 RAS 157 32 74 116 VDD DQ60 75 DQ29 117 VSS A1 158 33 VSS A0 VDD DQ28 159 DQ61 34 A2 76 DQ30 118 A3 160 DQ62 35 A4 77 DQ31 119 A5 161 DQ63 36 A6 78 A7 162 A8 79 VSS CK2 120 37 121 A9 163 VSS CK3 38 A10 80 NC 122 A11/BA0 164 NC 39 NC 81 NC 123 NC 165 SA0 40 82 SDA 124 SA1 83 SCL 125 VDD CK1 166 41 VDD VDD 167 SA2 42 CK0 84 VDD 126 NC 168 VDD 24 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 128 VSS CKE0 3 SMMS705A − FEBRUARY 1998 − REVISED APRIL 1998 dual-in-line memory module and components The dual-in-line memory module and components include: D PC substrate: 1,27 ± 0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage D Bypass capacitors: Multilayer ceramic D Contact area: Nickel plate and gold plate over copper functional block diagram for the TM2SR72EPH S0 RB CS DQMB0 U0 DQM R DQ[0:7] 8 U0, U4 CS DQMB4 DQM R DQ[0:7] DQ[32:39] 8 RB CK0 U1, U5, U8 U4 RC U2, U6 DQ[0:7] RC CK1 U3, U7 CS RC CS CK2 DQMB1 U1 DQM R DQ[8:15] 8 DQMB5 DQM R DQ[0:7] DQ[40:47] 8 U5 C RC DQ[0:7] CK3 DQMB1 U8 DQM R CB[0:7] 8 DQ[0:7] S2 VDD CS DQMB2 DQ[16:23] 8 U2 DQMB6 DQM R DQ[0:7] DQ[48:55] 8 CS DQMB3 8 U3 DQMB7 DQ[0:7] DQ[56:63] RAS: SDRAM U[0:8] CAS CAS: SDRAM U[0:8] WE WE: SDRAM U[0:8] A[0:11] 8 U[0:8] U7 DQ[0:7] SPD EEPROM SCL CKE: SDRAM U[0:8] A[0:11]: SDRAM U[0:8] LEGEND: CS = Chip Select SPD = Serial Presence Detect 4 VSS DQ[0:7] DQM R RAS CKE0 U6 CS DQM R U[0:8] Two 0.33 µF per SDRAM CS DQM R DQ[24:31] C R = 10 Ω RB = 5 Ω RC = 10Ω C = 10 pF CS POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 SDA A0 A1 A2 SA0 SA1 SA2 SMMS705A − FEBRUARY 1998 − REVISED APRIL 1998 functional block diagram for the TM4SR72EPH S1 VDD S0 CS CS CS U[0:8], UB[0:8] Two 0.33 µF per SDRAM CS VSS U0 DQMB0 DQM R DQ[0:7] 8 UB0 U4 DQMB4 DQM R DQ[0:7] DQ[0:7] CS CS DQ[32:39] 8 U[0:8], UB[0:8] UB4 DQM DQM DQ[0:7] DQ[0:7] CS CS R = 10 Ω RC = 10Ω RB = 5Ω RB CK: U0, U4 RB CK0 CK: U1, U5, U8 U1 DQMB1 R DQ[8:15] 8 UB1 DQM DQM DQ[0:7] DQ[0:7] U5 DQMB5 R DQ[40:47] 8 RB UB5 DQM DQM DQ[0:7] DQ[0:7] CK: UB0, UB4 RB CK1 CK: UB1, UB5, UB8 RC CK: U2, U6 CS CS RC CK2 CK: U3, U7 U8 DQMB1 R CB[0:7] 8 RC UB8 DQM DQM DQ[0:7] DQ[0:7] CK: UB2, UB6 RC CK3 CK: UB3, UB7 VDD S3 10 kΩ S2 CS U2 DQMB2 R DQ[16:23] 8 CS CS UB2 DQM DQM DQ[0:7] DQ[0:7] CS U6 DQMB6 R DQ[48:55] 8 UB6 DQM DQM DQ[0:7] DQ[0:7] CKE1 CKE: UB[0:8] CKE0 CKE: U[0:8] RAS RAS: U[0:8], UB[0:8] CAS CAS: U[0:8], UB[0:8] WE WE: U[0:8], UB[0:8] A[0:11] CS U3 DQMB3 R DQ[24:31] 8 CS CS DQM DQM DQ[0:7] DQ[0:7] CS U7 UB3 DQMB7 R DQ[56:63] 8 A[0:11]: U[0:8], UB[0:8] UB7 DQM DQM DQ[0:7] DQ[0:7] SPD EEPROM SDA SCL A0 A1 A2 SA0 SA1 SA2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 5 SMMS705A − FEBRUARY 1998 − REVISED APRIL 1998 absolute maximum ratings over operating ambient temperature range (unless otherwise noted)† Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.5 V to 4.6 V Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Power dissipation: TM2SR72EPH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 W TM4SR72EPH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 W Operating ambient temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 55°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS. recommended operating conditions MIN NOM MAX UNIT 3 3.3 3.6 V VDD VSS Supply voltage VIH VIH-SPD High-level input voltage 2 High-level input voltage for SPD device Low-level input voltage ‡ 2 Supply voltage 0 VIL TA Operating ambient temperature ‡ VIL MIN = −1.5 V ac (pulse width v 5 ns) V VDD + 0.3 5.5 V V −0.3 0.8 V 0 70 °C capacitance over recommended ranges of supply voltage and ambient temperature, f = 1 MHz (see Note 2)§ TMxSR72EPH PARAMETER MIN MAX UNIT Ci(CK) Input capacitance, CK input 2.5 4 pF Ci(AC) Input capacitance, address and control inputs: A0 −A11, RAS, CAS, WE 2.5 5 pF Ci(CKE) Input capacitance, CKE input 5 pF Co Output capacitance 4 6.5 pF Ci(DQMBx) Input capacitance, DQMBx input 2.5 5 pF Ci(Sx) Input capacitance, Sx input 2.5 5 pF Ci/o(SDA) Input/output capacitor, SDA input 9 pF Ci(SPD) Input capacitor, SA0, SA1, SA2, SCL inputs § Specifications in this table represent a single SDRAM device. NOTE 2: VDD = 3.3 V ± 0.3 V. Bias on pins under test is 0 V. 7 pF 6 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 SMMS705A − FEBRUARY 1998 − REVISED APRIL 1998 electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) (see Note 3)† ’xSR72EPH-10 PARAMETER VOH VOL TEST CONDITIONS High-level output voltage IOH = − 2 mA IOL = 2 mA Low-level output voltage II Input current (leakage) IO Output current (leakage) 0 V < VO < VDD Output disabled Operating current Burst length = 1, CAS latency = 2 tRC ≥ tRC MIN IOH/IOL = 0 mA, one bank CAS latency = 3 activated (see Note 4) ICC2P ICC2PS ICC2N ICC2NS Precharge standby current in power-down mode Precharge standby current in non-power-down mode ICC3P ICC3PS Active standby current in power-down mode ICC3N ICC3NS ICC4 ICC5 Active standby current in non-power-down mode Burst current Auto-refresh current MAX 2.4 0 V < VI < VDD + 0.3 V, All other pins = 0 V to VDD ICC1 MIN V 0.4 V "10 µA "10 µA 85 mA 90 CKE ≤ VIL MAX, tCK = 15 ns (see Note 5) 1 CKE and CK ≤ VIL MAX, tCK = ∞ (see Note 6) 1 CKE ≥ VIH MIN, tCK = 15 ns (see Note 5) 30 CKE ≥ VIH MIN, CK ≤ VIL MAX, tCK = ∞ (see Note 6) 2 CKE ≤ VIL MAX, tCK = 15 ns (see Note 5) 3 CKE and CK ≤ VIL MAX, tCK = ∞ (see Note 6) 3 CKE ≥ VIH MIN, tCK = 15 ns (see Note 5) 40 CKE ≥ VIH MIN, CK ≤ VIL MAX, tCK = ∞ (see Note 6) 10 Page burst, IOH/IOL = 0 mA CAS latency = 2 All banks activated, nCCD = one cycle CAS latency = 3 (see Note 7) 130 CAS latency = 2 80 CAS latency = 3 85 tRC ≤ tRC MIN UNIT mA mA mA mA mA 140 mA ICC6 Self-refresh current CKE ≤ VIL MAX 0.4 mA † Specifications in this table represent a single SDRAM device. NOTES: 3. All specifications apply to the device after power-up initialization. All control and address inputs must be stable and valid. 4. Control, DQ, and address inputs change state only twice during tRC. 5. Control, DQ, and address inputs change state only once every 30 ns. 6. Control, DQ, and address inputs do not change (stable). 7. Control, DQ, and address inputs change only once every cycle. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 7 SMMS705A − FEBRUARY 1998 − REVISED APRIL 1998 ac timing requirements† ‡ ’xSR72EPH-10 MIN UNIT MAX tCK2 tCK3 Cycle time, CLK, CAS latency = 2 15 ns Cycle time, CLK, CAS latency = 3 10 ns tCH tCL Pulse duration, CLK high 3 ns Pulse duration, CLK low 3 tAC2 tAC3 Access time, CLK high to data out, CAS latency = 2 (see Note 8) 7.5 ns Access time, CLK high to data out, CAS latency = 3 (see Note 8) 7.5 ns tOH tLZ Hold time, CLK high to data out 3 ns Delay time, CLK high to DQ in low-impedance state (see Note 9) 2 ns tHZ tIS Delay time, CLK high to DQ in high-impedance state (see Note 10) Setup time, address, control, and data input 2 ns tIH tCESP Hold time, address, control, and data input 1 ns Power-down/self-refresh exit time 10 tRAS tRC Delay time, ACTV command to DEAC or DCAB command 50 Delay time, ACTV, REFR, or SLFR exit to ACTV, MRS, REFR, or SLFR command 80 ns Delay time, ACTV command to READ, READ-P, WRT, or WRT-P command (see Note 11) 20 ns tRP tRRD Delay time, DEAC or DCAB command to ACTV, MRS, REFR, or SLFR command 30 ns Delay time, ACTV command in one bank to ACTV command in the other bank 30 ns tRSA tAPR Delay time, MRS command to ACTV, MRS, REFR, or SLFR command 20 ns tAPW tT Final data in of WRT-P operation to ACTV, MRS, SLFR, or REFR command tREF nCCD Refresh interval Delay time, READ or WRT command to an interrupting command 1 nCDD nCLE Delay time, CS low or high to input enabled or inhibited 0 0 cycle Delay time, CKE high or low to CLK enabled or disabled 1 1 cycle nCWL nDID Delay time, final data in of WRT operation to READ, READ-P, WRT, WRT-P 1 Delay time, ENBL or MASK command to enabled or masked data in 0 0 cycle nDOD Delay time, ENBL or MASK command to enabled or masked data out 2 2 cycle nHZP2 Delay time, DEAC or DCAB command to DQ in high-impedance state, CAS latency = 2 2 cycle nHZP3 Delay time, DEAC or DCAB command to DQ in high-impedance state, CAS latency = 3 3 cycle nWCD Delay time, WRT command to first data in 0 cycle tRCD Final data out of READ-P operation to ACTV, MRS, SLFR, or REFR command Transition time (see Note 12) ns 8 ns ns 100 000 tRP − (CL −1) * tCK tRP + tCK 1 0 ns ns ns 5 ns 64 ms cycle cycle nWR Delay time, final data in of WRT operation to DEAC or DCAB command 1 cycle † All references are made to the rising transition of CKx, unless otherwise noted. ‡ Specifications in this table represent a single SDRAM device. NOTES: 8. tAC is referenced from the rising transition of CK that precedes the data-out cycle. For example, the first data out tAC is referenced from the rising transition of CKx that is CAS latency − one cycle after the READ command. Access time is measured at output reference level 1.4 V. 9. tLZ is measured from the rising transition of CKx that is CAS latency − one cycle after the READ command. 10. tHZ MAX defines the time at which the outputs are no longer driven and is not referenced to output voltage levels. 11. For read or write operations with automatic deactivate, tRCD must be set to satisfy minimum tRAS. 12. Transition time, tT, is measured between VIH and VIL. 8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 SMMS705A − FEBRUARY 1998 − REVISED APRIL 1998 serial presence detect The serial presence detect (SPD) is contained in a 2K-bit serial EEPROM located on the module. The SPD nonvolatile EEPROM contains various data such as module configuration, SDRAM organization, and timing parameters (see Table 1 and Table 2). Only the first 128 bytes are programmed by Texas Instruments; the remaining 128 bytes are available for customer use. Programming is done through a IIC bus using the clock (SCL) and data (SDA) signals. All Texas Instruments modules comply with the current JEDEC SPD Standard. See the Texas Instruments Serial Presence Detect Technical Reference (literature number SMMU001) for further details. SPD contents for the TMxSR72EPH devices are listed in the following tables: Table 1−TM2SR72EPH Table 2−TM4SR72EPH Table 1. Serial Presence Detect Data for the TM2SR72EPH TM2SR72EPH-10 BYTE NO. DESCRIPTION OF FUNCTION ITEM DATA 0 Defines number of bytes written into serial memory during module manufacturing 128 bytes 80h 1 Total number of bytes of SPD memory device 256 bytes 08h 2 Fundamental memory type (FPM, EDO, SDRAM, . . .) 3 Number of row addresses on this assembly 4 Number of column addresses on this assembly 5 Number of module rows on this assembly 6 Data width of this assembly 72 bits 48h 7 Data width continuation 8 Voltage interface standard of this assembly SDRAM 04h 11 0Bh 9 09h 1 bank 01h 00h 9 SDRAM cycle time at maximum supported CAS latency (CL), CL = X 10 SDRAM access from clock at CL = X 11 DIMM configuration type (non-parity, parity, error correcting code [ECC]) LVTTL 01h tCK = 10 ns tAC = 7.5 ns ECC A0h 75h 02h 15.6 µs/ self-refresh 80h 12 Refresh rate / type 13 SDRAM width, primary DRAM x8 08h 14 Error-checking SDRAM data width x8 08h 15 Minimum clock delay, back-to-back random column addresses 1 CK cycle 01h 16 Burst lengths supported 1, 2, 4, 8 0Fh 17 Number of banks on each SDRAM device 2 banks 02h 18 CAS latencies supported 2, 3 06h 19 CS latency 0 01h 20 Write latency 21 SDRAM module attributes 22 SDRAM device attributes: general 23 Minimum clock cycle time at CL = X − 1 24 Maximum data-access time from clock at CL = X − 1 25 Minimum clock cycle time at CL = X − 2 26 Maximum data-access time from clock at CL = X − 2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 0 01h Non-buffered/ Non-registered 00h VDD tolerance = (+10%) , Burst read / write, precharge all, auto precharge 0Eh tCK = 15 ns tAC = 7.5 ns N/A F0h N/A 00h 75h 00h 9 SMMS705A − FEBRUARY 1998 − REVISED APRIL 1998 serial presence detect (continued) Table 1. Serial Presence Detect Data for the TM2SR72EPH (Continued) TM2SR72EPH-10 BYTE NO. DESCRIPTION OF FUNCTION 27 Minimum row-precharge time 28 Minimum row-active to row-active delay 29 Minimum RAS-to-CAS delay 30 Minimum RAS pulse width 31 Density of each bank on module 32 Command and address signal input setup time 33 Command and address signal input hold time 34 35 36−61 ITEM DATA tRP = 20 ns 14h tRRD = 20 ns tRCD = 30 ns 1Eh tRAS = 50 ns 16M Bytes 32h 20h Data signal input setup time tIS = 2 ns tIH = 1 ns tIS = 2 ns Data signal input hold time tIH = 1 ns 10h 04h 10h 20h Superset features (may be used in the future) 62 SPD revision Rev. 1.2 12h 63 Checksum for byte 0 −62 12 0Ch 97h 9700...00h 72 Manufacturer’s JEDEC ID code per JEP −106E Manufacturing location† 73 Manufacturer’s part number T 54h 74 Manufacturer’s part number M 4Dh 75 Manufacturer’s part number 2 32h 76 Manufacturer’s part number S 53h 77 Manufacturer’s part number R 52h 78 Manufacturer’s part number 7 37h 79 Manufacturer’s part number 2 32h 80 Manufacturer’s part number E 45h 81 Manufacturer’s part number P 50h 82 Manufacturer’s part number H 48h 83 Manufacturer’s part number − 2Dh 84 Manufacturer’s part number 1 31h 85 Manufacturer’s part number 0 30h 86−90 Manufacturer’s part number Die revision code† space 20h 64 −71 91 TBD TBD TBD 93−94 PCB revision code† Manufacturing date† 95−98 Assembly serial number† TBD 99−125 Manufacturer-specific data† TBD 92 TBD 126 Clock frequency 127 SDRAM component and clock interconnection details System-integrator-specific data‡ 128−166 POST OFFICE BOX 1443 66 Mhz 66h 199 C7h TBD 167−255 Open † TBD indicates that values are determined at manufacturing time and are module-dependent. ‡ These TBD values are determined and programmed by the customer (optional). 10 14h • HOUSTON, TEXAS 77251−1443 SMMS705A − FEBRUARY 1998 − REVISED APRIL 1998 serial presence detect (continued) Table 2. Serial Presence Detect Data for the TM4SR72EPH TM4SR72EPH-10 BYTE NO. DESCRIPTION OF FUNCTION ITEM DATA 0 Defines number of bytes written into serial memory during module manufacturing 128 bytes 80h 1 Total number of bytes of SPD memory device 256 bytes 08h 2 Fundamental memory type (FPM, EDO, SDRAM, . . .) SDRAM 04h 3 Number of row addresses on this assembly 11 0Bh 4 Number of column addresses on this assembly 9 09h 5 Number of module banks on this assembly 2 banks 02h 6 Data width of this assembly 72 bits 48h 7 Data width continuation 8 Voltage interface standard of this assembly 9 SDRAM cycle time at maximum supported CAS latency (CL), CL = X 10 SDRAM access from clock at CL = X 11 DIMM configuration type (non-parity, parity, error correcting code [ECC]) 12 Refresh rate / type 13 14 15 Minimum clock delay, back-to-back random column addresses 16 17 18 CAS latencies supported 19 CS latency 20 Write latency 21 SDRAM module attributes 00h LVTTL 01h tCK = 10 ns tAC = 7.5 ns A0h ECC 02h 15.6 µs/ self-refresh 80h SDRAM width, primary DRAM x8 08h Error-checking SDRAM data width x8 08h 1 CK cycle 01h Burst lengths supported 1, 2, 4, 8 0Fh Number of banks on each SDRAM device 2 banks 02h 2, 3 06h 0 01h 0 01h Non-buffered/ Non-registered 00h VDD tolerance = (+10%) , Burst read / write, precharge all, auto precharge 0Eh 22 SDRAM device attributes: general 23 Minimum clock cycle time at CL = X − 1 24 Maximum data-access time from clock at CL = X − 1 25 75h tCK = 15 ns tAC = 7.5 ns F0h Minimum clock cycle time at CL = X − 2 N/A 00h 26 Maximum data-access time from clock at CL = X − 2 N/A 00h 27 Minimum row-precharge time Minimum row-active to row-active delay 29 Minimum RAS-to-CAS delay tRP = 20 ns tRRD = 20 ns tRCD = 30 ns 14h 28 30 Minimum RAS pulse width 31 Density of each bank on module tRAS = 50 ns 16M Bytes POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 75h 14h 1Eh 32h 04h 11 SMMS705A − FEBRUARY 1998 − REVISED APRIL 1998 serial presence detect (continued) Table 2. Serial Presence Detect Data for the TM4SR72EPH (Continued) TM4SR72EPH-10 BYTE NO. DESCRIPTION OF FUNCTION 32 Command and address signal input setup time 33 Command and address signal input hold time 34 Data signal input setup time 35 Data signal input hold time 36 −61 ITEM DATA tIS = 2 ns tIH = 1 ns 20h tIS = 2 ns tIH = 1 ns 20h Rev. 1.2 12h 10h Superset features (may be used in the future) 62 SPD revision 63 Checksum for byte 0 −62 13 0Dh 97h 9700...00h 72 Manufacturer’s JEDEC ID code per JEP −106E Manufacturing location† 73 Manufacturer’s part number T 54h 74 Manufacturer’s part number M 4Dh 75 Manufacturer’s part number 4 34h 76 Manufacturer’s part number S 53h 77 Manufacturer’s part number R 52h 78 Manufacturer’s part number 7 37h 79 Manufacturer’s part number 2 32h 80 Manufacturer’s part number E 45h 81 Manufacturer’s part number P 50h 82 Manufacturer’s part number H 48h 83 Manufacturer’s part number − 2Dh 84 Manufacturer’s part number 1 31h 85 Manufacturer’s part number 0 30h 86−90 Manufacturer’s part number Die revision code† space 20h 64 −71 91 TBD TBD TBD 93−94 PCB revision code† Manufacturing date† 95−98 Assembly serial number† TBD 99−125 Manufacturer-specific data† 92 TBD TBD 126 Clock frequency 127 SDRAM component and clock interconnection details System-integrator-specific data‡ 128−166 POST OFFICE BOX 1443 66 Mhz 66h 247 F7h TBD 167−255 Open † TBD indicates that values are determined at manufacturing time and are module-dependent. ‡ These TBD values are determined and programmed by the customer (optional). 12 10h • HOUSTON, TEXAS 77251−1443 SMMS705A − FEBRUARY 1998 − REVISED APRIL 1998 device symbolization (TM2SR72EPH) TM2SR72EPH -SS YYMMT 3.3-V Voltage Key Position Unbuffered Key Position YY MM T -SS = = = = Year Code Month Code Assembly Site Code Speed Code NOTE A: Location of symbolization may vary. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 13 SMMS705A − FEBRUARY 1998 − REVISED APRIL 1998 MECHANICAL DATA BU (R-PDIM-N168) DUAL IN-LINE MEMORY MODULE 5.255 (133,48) 5.245 (133,22) (Note D) Notch 0.157 (4,00) x 0.122 (3,10) Deep 2 Places 0.050 (1,27) 0.039 (1,00) TYP 0.125 (3,18) 0.054 (1,37) 0.046 (1,17) Notch 0.079 (2,00) x 0.122 (3,10) Deep 2 Places 0.014 (0,35) MAX 0.118 (3,00) TYP 0.125 (3,18) 0.700 (17,78) TYP 0.118 (3,00) DIA 2 Places 1.255 (31,88) 1.245 (31,62) 0.106 (2,70) MAX 0.157 (4,00) MAX (For Double Sided DIMM Only) 4088183/A 06/97 NOTES: A. B. C. D. E. 14 All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Falls within JEDEC MO-161 Dimension includes de-panelization variations; applies between notch and tab edge. Outline may vary above notches to allow router/panelization irregularities. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety-critical applications. TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Amplifiers Data Converters DSP Clocks and Timers Interface Logic Power Mgmt Microcontrollers RFID RF/IF and ZigBee® Solutions amplifier.ti.com dataconverter.ti.com dsp.ti.com www.ti.com/clocks interface.ti.com logic.ti.com power.ti.com microcontroller.ti.com www.ti-rfid.com www.ti.com/lprf Applications Audio Automotive Broadband Digital Control Medical Military Optical Networking Security Telephony Video & Imaging Wireless www.ti.com/audio www.ti.com/automotive www.ti.com/broadband www.ti.com/digitalcontrol www.ti.com/medical www.ti.com/military www.ti.com/opticalnetwork www.ti.com/security www.ti.com/telephony www.ti.com/video www.ti.com/wireless Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2008, Texas Instruments Incorporated