TI SN75061

SLLS026C − JANUARY 1987 − REVISED JULY 1990
•
•
•
•
•
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IEEE 802.3 1BASE5 Driver and Receiver
On-Chip Receiver Squelch With Adjustable
Threshold
Adjustable Squelch Delay
Direct TTL-Level Squelch Output
Squelch Circuit Allows for External Noise
Filtering
Two Driver-Enable Options
On-Chip Start-of-Idle Detection and Disable
Driver Provides 2-V Minimum into a 50-Ω
Differential Load Allowing for Use With
Doubly-Terminated Lines and Multipoint
Architectures
On-Chip Driver Slew-Rate Control for Very
Closely Matched Output Rise and Fall
Times
N PACKAGE
(TOP VIEW)
DRDLAJ
DRO +
DRO −
SQDLAJ
RXI +
RXI −
SQTHAJ
GND
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
DATEN
DRI
DLEN
RXO
SQO
SQDLI
SQRXO
Function Tables
RECEIVER§
DRIVER
INPUTS
DRI
L
H
X
H
L
OUTPUTS
CONDITION
DATEN DLEN DRO + DRO −
L
L
H
H
H
X
X
H
L
L
No active signal ¶
H
L
Z
L†
H‡
L
H
Z
H†
L‡
Active signal ¶
INPUTS
RXI +
RXI −
X
L
H
X
H
L
OUTPUTS
RXO
SQO
H
L
H
H
L
L
† This condition is valid during the time period set by DRDLAJ following a rising transition on DRI. Following this, when a
subsequent positive transition does not occur on DRI, the outputs go to the high-impedance state.
‡ This condition is valid when it occurs within the enable time set by DRDLAJ after a rising transition on DRI. Otherwise, the
outputs are in the high-impedance state.
§ Pins 9 and 10 are tied together.
¶ An active signal is one that has an amplitude greater than the threshold level set by SQTHAJ.
Copyright  1990, Texas Instruments Incorporated
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SLLS026C − JANUARY 1987 − REVISED JULY 1990
logic diagram (positive logic)
VCC
Slew Control
16
2
V
DRO +
Slew Control
14
DRI
DATEN
DLEN
3
15
DRO −
Output Enable
13
V
RT
1
DRDLAJ
CT
V
RXI +
RXI −
V
5
12
6
V
V
11
V
V
SQTHAJ
7
RT
9
4
CT
SQRXO
10
SQDLI
2−2
•
SQDLAJ
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•
RXO
SQO
SLLS026C − JANUARY 1987 − REVISED JULY 1990
logic symbol†
DRI
14
≥1
&
DLEN
DRDLAJ
DATEN
13
2
DRO+
EN
1
X
3
[ADJDEL]
DRO −
15
1
RXI+
1
5
3
12
RXO
Z1
2
1
RXI −
6
Z2
1
2
7
SQTHAJ
SQRXO
X
[ADJTHRES]
9
≥1
SQDLI
10
11
V3
SQDLAJ
4
X
SQO
[ADJDEL]
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
description
The SN75061 is a single-channel driver/receiver pair designed for use in IEEE 802.3, 1BASE5 applications as
well as other general data communications circuits. The SN75061 offers both a driver and a receiver that are
easily configured for use with a variety of controllers and data encoder/decoders.
The receiver features a full analog squelch circuit with an adjustable threshold and a programmable squelch
delay. Internal nodes of the squelch circuitry are brought out to external connections to allow for the insertion
of noise-filtering circuitry of the designer’s choice.
As with the receiver, the driver offers a variety of implementation options. Driver enabling may be directly
controlled by an external logic input or by use of an on-chip one-shot that is retriggered as long as data is being
sent to the driver. The driver then automatically goes to the high-impedance state when end-of-packet common
phrase occurs. The driver features internal slew-rate control for optimal matching of rise and fall times allowing
for reduction of driver-induced jitter.
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2−3
SLLS026C − JANUARY 1987 − REVISED JULY 1990
receiver
The SN75061 receiver implements full analog squelch functions by integrating both a separate, parallel squelch
receiver with an externally programmable threshold, and a programmable one-shot. The output of the squelch
receiver and the input to the high-level, dc-triggered one-shot are brought out to external connections. These
pins can be shorted for direct implementation or used for the insertion of noise-filtering circuitry of the
implementer’s design. The receiver one-shot can be effectively bypassed by applying a high logic level to
SQDLI. The squelch threshold may be set externally by applying an external voltage set to a level that is −2 times
the desired threshold voltage. When SQTHAJ is left open, the squelch receiver defaults to its internal preset
value of −600 mV. The receiver also outputs a high logic squelch signal when there is not any active data present
at the receiver inputs. When data is not present on the transmission line, the receiver output assumes a high
level. The unsquelch duration is set externally with an R-C combination at SQDLAJ.
driver
The driver offers a variety of implementation options. Driver enabling may be controlled directly by an active-low,
external logic input on DATEN or by use of another on-chip one-shot that retriggers with positive-going
transitions on the driver input line. When positive transition does not occur within the pulse duration set by an
external R-C combination, the one-shot times out and the driver is automatically put into a high-impedance state.
When operating in the delay-enable mode, the 2-bit-time, high-level, start-of-idle pulse prescribed by IEEE
802.3 1BASE5 causes the one-shot to time out and automatically place the driver outputs in the high-impedance
state. This delay time is also adjustable for use in other applications. The driver implements an output slew-rate
control that is internally set for nominally 40 mV/ns. (This is roughly a 100-ns peak-to-peak differential transition
time.) The driver outputs are capable of driving a 50-Ω differential load with a minimum output level of 2 V.
Short-circuit output current is greater than 100 mA.
2−4
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•
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Terminal Functions
PIN
DESCRIPTION
NAME
NO.
DATEN
15
Driver data enable. When this sign is low, driver outputs are in an active state. When the signal is high, the driver outputs
are in a high-impedance state when DLEN is also high.
DLEN
13
Driver delay enable. When this signal is low and DATEN is high, the driver outputs are active for a period of time set by
DRDLAJ after a positive-going transition on DRI. When there is not any active data on DRI, the outputs are in a high-impedance state.
1
Driver delay adjust is a connection for the external R-C combination that determines the duration of the driver output active
state after a positive transition on DRI when DLEN is low and DATEN is high.
DRDLAJ
DRI
14
Driver data input
DRO +
2
Noninverting driver output
DRO −
3
Inverting driver output
GND
8
Ground. Common for all voltages
RXI +
5
Noninverting receiver input
RXI −
6
Inverting receiver input
RXO
12
SQDLAJ
4
Main receiver input
Squelch delay adjust is a connection for an external R-C combination that determines the duration of the
receiver unsquelch after a negative-going transition on SQDLI.
SQDLI
10
Squelch delay input is the input to the one-shot that controls the duration of the receiver unsquelch period. The main
receiver output remains unsquelched as long as SQDLI is held high. Timing of the unsquelch period begins on the high-tolow transition of SQDLI.
SQO
11
Squelch output is high while the receiver is squelched.
SQRXO
9
Squelch receiver output is high only when the differential receiver input exceeds the threshold set by SQTHAJ.
SQTHAJ
7
Squelch receiver threshold adjust. The voltage at this input determines the threshold of the squelch receiver in a ratio of
−2, SQTHAJ to threshold. When the receiver is left open, the squelch receiver threshold defaults to − 600 mV.
VCC
16
Supply-voltage input
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage, VI (any logic input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Receiver differential input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 25 V
Receiver input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 15 V
Driver output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 15 V
Continuous total dissipation at (or below) 25°C free-air temperature (see Note 1) . . . . . . . . . . . . . . 1150 mW
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: For operation above 25°C free-air temperature, derate to 736 mW at 70°C at the rate of 9.2 mW/°C.
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2−5
SLLS026C − JANUARY 1987 − REVISED JULY 1990
recommended operating conditions
Supply voltage, VCC
Driver high-level input voltage, VIH
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
2
V
Driver low-level input voltage, VIL
0.8
Receiver common-mode input voltage, VIC (see Note 2)
−2.5
5
Driver high-level output current, IOH
V
V
−150
mA
150
mA
260
kΩ
Driver low-level output current, IOL
External timing resistance, Rext
5
External timing capacitance, Cext
No restriction
Operating free-air temperature, TA
0
70
°C
NOTE 2: The algebraic convention, in which the less-positive (more negative) limit is designated as minimum, is used in this data sheet for
common-mode input voltage VIC and threshold levels VIT+ and VIT− .
electrical characteristics over recommended operating free-air temperature and supply voltage
ranges (unless otherwise noted)
driver
PARAMETER
TEST CONDITIONS
VIK
Input clamp voltage
II = − 18 mA
RL = 50 Ω
VOD
Differential output voltage
∆VOD
Change in differential output voltage for a change in
logic input state
IIH
IIL
High-level input current
Low-level input current
VI = 2 4 V
VI = 0.5 V
IOS
Short-circuit output current
VO = 0 or 6 V,
IOZ
High-impedance output current
VCC = 5.25 V
2
RL = 115 Ω
± 100
•
2.4
MAX
UNIT
−1.5
V
3.3
V
50
mV
20
µA
−35
µA
VI = 0.8 V or 2.5 V
VOC = 10 V
± 300
mA
VOC = 0
−100
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TYP†
3.65
† All typical values are at VCC = 5 V, TA = 25°C.
2−6
MIN
100
µA
SLLS026C − JANUARY 1987 − REVISED JULY 1990
electrical characteristics over recommended operating free-air temperature and supply voltage
ranges (unless otherwise noted) (continued)
receiver
PARAMETER
VIK
VIT+
Input clamp voltage, squelch delay
TEST CONDITIONS
Positive-going input threshold voltage
II = − 18 mA
VO = 2.7 V,
IO = − 0.4 mA
VIT −
Negative-going input threshold voltage
VO = 0.5 V,
IO = 16 mA
Vhys
VIC
Hysteresis voltage (VIT+ − VIT −)
SQRXO
VCC = 4.75 V,
SQDLAJ at 0.8 V
IOH = − 400 µA,
VCC = 4.75 V,
VID(RXI) = − 0.7 V,
IOH = − 20 µA,
SQDLAJ open
VCC = 4.75 V,
SQDLAJ at 2 V
IOL = 8 mA
IOL = 16 mA
RXO
IIH
IIL
−50‡
SQO
SQRXO
VCC = 4.75 V,
VID(RXI) = 50 mV
SQDLI
VI = 2.4 V
VI = 0.5 V
High-level input current
Low-level input current
Short-circuit output current
mV
mV
3.5
4.65
0.5
IOL = 8 mA
IOL = 8 mA
0.35
0.5
IOL = 16 mA
0.5
−15
−15
VCC = 5 V,
VO = 0
−0.8
20
µA
−35
µA
−85
−100
−1
VIC = 1.5 V to 3.5 V
−525
VIC = − 2.5 V to 1.5 V
or 3.5 V to 5 V
SQTHAJ at 200 mV to 4 V
−600
mA
−1.2
10
VCC = 5 V,
SQTHAJ open
V
0.45
SQRXO
Squelch preset input threshold voltage
V
0.45
VO = 0
VIT −(sq)
Ratio of SQTHAJ input voltage to
actual squelch threshold voltage
2.7
VCC = 5.25 V,
Input resistance
V
mV
V
SQO
ri
UNIT
2.7
2.7
RXO
IOS
50
5
High-level output voltage
Low-level output voltage
MAX
−1.5
Common-mode input voltage
SQO
VOL
TYP†
50
RXO
VOH
MIN
kΩ
−675
mV
−500
−700
mV
−1.9
−2.1
driver and receiver
ICC
Supply current
VCC = 5.25 V,
No load
Driver outputs disabled,
70
mA
† All typical values are at VCC = 5 V, TA = 25°C.
‡ The algebraic convention, in which the less positive (more negative) limit is designated as minimum, is used in this data sheet for common-mode
input voltage VIC and threshold levels VIT + and VIT − .
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2−7
SLLS026C − JANUARY 1987 − REVISED JULY 1990
switching characteristics, VCC = 5 V, TA = 25°C
driver
PARAMETER
TEST CONDITIONS
SR
Differential-output slew rate
VO = − 2 V to 2 V,
RL =100 Ω (differential),
td(OD)
Differential-output delay time
(td(OD)+ and td(OD)− )
CL= 15 pF,
RL =100 Ω (differential),
See Figure 2
Differential-output delay time difference
(td(OD)+ − td(OD)− )
RL =100 Ω (differential),
See Figure 2
tPHZ
tPLZ
MIN
TYP
MAX
UNIT
28
40
52
mV/ns
160
ns
5
ns
220
ns
300
ns
220
ns
290
ns
250
ns
µss
Disable time from DATEN
tPZH
tPZL
Enable time from DATEN
tPZH
Enable time from DLEN
tw(en)
See Figure 1
See Figure 3, 4, and 5
Enable pulse duration time (with DLEN low)
Cext = 100 pF,
See Figure 6
Rext = 62 kΩ,
2
2.5
3
MIN
TYP
MAX
receiver
PARAMETER
TEST CONDITIONS
UNIT
ten(RX)
tPLH
Receiver enable time
Squelch off,
See Figure 7
117
Propagation delay time, low- to high level output
Squelch off,
See Figure 8
20
35
ns
tPHL
Propagation delay time, high- to low level output
Squelch off,
See Figure 8
22
35
ns
Cext = 50 pF,
See Figure 9
Rext = 51 kΩ,
1.2
1.45
µss
Cext = 15 pF,
See Figure 9
Rext = 6.8 kΩ,
180
ns
td(unsq)
Unsquelch delay time
1
ns
PARAMETER MEASUREMENT INFORMATION
5V
DRDLAJ
Rext = 62 kΩ
3V
Input
Cext = 100 pF
0V
DLEN at 3 V
DRI
Generator
(see Note A)
50 Ω
RL = 100 Ω
DRO +
Output
DRO −
2V
Output
tr
0V
−2 V
tf
SR + 4 V
t r or t
f
DATEN at 0.5 V
VOLTAGE WAVEFORMS
TEST CIRCUIT
NOTE A: The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, duty cycle ≤ 50%, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
Figure 1. Test Circuit and Voltage Waveforms for Driver Slew Rate
2−8
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•
SLLS026C − JANUARY 1987 − REVISED JULY 1990
PARAMETER MEASUREMENT INFORMATION
5V
Rext = 62 kΩ
DRDLAJ
3V
Input
Cext = 100 pF
DLEN at 3 V
S1
Generator
(see Note A)
50 Ω
4
1.5 V
td(OD)+
Output
DRO +
CL
DRI
2
1.5 V
0V
td(OD) −
VO +
RL = 100 Ω
RL = 100 Ω
50%
Output
DRO −
50%
3
S2
PE-64352
or Equivalent
(see Note C)
CL = 15 pF
(see Note B)
DATEN at 0.5 V
VO −
1
VOLTAGE WAVEFORMS
TEST CIRCUIT
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, duty cycle ≤ 50%, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
C. When measuring differential-output delay time difference, switches S1 and S2 are closed (Isolation transformer from Pulse
Engineering P/N PE-64352).
Figure 2. Test Circuit and Voltage Waveforms for Driver Differential Delay Time
5V
Rext = 62 kΩ
DRDLAJ
Cext = 100 pF
DLEN at 3 V
3V
DRO +
Output
Input
DRI at 0 V or 3 V
DATEN
Generator
(see Note A)
DRO −
CL = 50 pF
(see Note B)
RL = 100 Ω
1.5 V
1.5 V
0V
tPZH
tPHZ
0.5 V
VOH
Output
50 Ω
TEST CIRCUIT
2.3 V
VOLTAGE WAVEFORMS
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 500 kHz, duty cycle ≤ 50%, tr ≤ 6 ns,
tf ≤ 6 ns, ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 3. Test Circuit and Voltage Waveforms for Driver Enable and Disable Time
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2−9
SLLS026C − JANUARY 1987 − REVISED JULY 1990
PARAMETER MEASUREMENT INFORMATION
5V
Rext = 62 kΩ
DRDLAJ
Cext = 100 pF
5V
DLEN at 3 V
DRO +
3V
RL = 100 Ω
Input
Output
tPZL
0V
DRI at 0 V or 3 V
DATEN
DRO −
tPLZ
CL = 50 pF
(see Note B)
≈5V
2.3 V
Output
Generator
(see Note A)
VOL
50 Ω
0.5 V
TEST CIRCUIT
VOLTAGE WAVEFORMS
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 200 kHz, duty cycle ≤ 50%, tr ≤ 6 ns,
tf ≤ 6 ns, ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 4. Test Circuit and Voltage Waveforms for Driver Enable and Disable Time
5V
Rext = 62 kΩ
DRDLAJ
3V
Cext = 100 pF
Input
1.5 V
DLEN at 3 V
0V
DRO +
tPZH
DRI
GENERATOR
(see Note A)
50 Ω
VOH
Output
Output
DRO −
CL = 50 pF
DATEN at 3 V (see Note B)
2.3 V
≈0 V
RL = 100 Ω
TEST CIRCUIT
VOLTAGE WAVEFORMS
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, duty cycle ≤ 50%, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 5. Test Circuit and Voltage Waveforms for Enable Time From Delay Enable
2−10
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•
SLLS026C − JANUARY 1987 − REVISED JULY 1990
PARAMETER MEASUREMENT INFORMATION
5V
Rext = 62 kΩ
DRDLAJ
Cext = 100 pF
DLEN at 0.5 V
DRO +
DRI
Generator
(see Note A)
Output
50 Ω
RL = 100 Ω
CL = 50 pF
(see Note B)
DRO −
DATEN at 3 V
TEST CIRCUIT
3V
Input
0V
0.5 V
tw(en)
VOH
2.3 V
Output
0V
VOLTAGE WAVEFORMS
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 200 kHz, duty cycle ≤ 50%, tr ≤ 6 ns,
tf ≤ 6 ns, ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 6. Test Circuit and Voltage Waveforms for Enable Pulse Duration With Delay Enable Low
5V
Rext = 51 kΩ
Generator
(see Note A)
SQDLAJ
50 Ω
3V
Input
Cext = 50 pF
1.5 V
1.5 V
0V
ten(RX)
RXI +
1.5 V
Open
RXI −
SQTHAJ
SQRXO
RXO
SQDLI
VOH
Output
CL = 15 pF
(see Note B)
Output
1.3 V
1.3 V
VOL
VOLTAGE WAVEFORMS
TEST CIRCUIT
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 500 kHz, duty cycle ≤ 50%, tr ≤ 6 ns,
tf ≤ 6 ns, ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 7. Test Circuit and Voltage Waveforms for Receiver Enable (Unsquelch) Time
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2−11
SLLS026C − JANUARY 1987 − REVISED JULY 1990
PARAMETER MEASUREMENT INFORMATION
5V
SQDLAJ
Rext = 51 kΩ
Generator
(see Note A)
3V
50 Ω
Input
Cext = 50 pF
1.5 V
0V
tPLH
RXI +
1.5 V
Open
1.5 V
RXO
RXI −
SQTHAJ
tPHL
VOH
Output
Output
1.3 V
1.3 V
VOL
CL = 15 pF
(see Note B)
SQDLI
3V
VOLTAGE WAVEFORMS
TEST CIRCUIT
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, duty cycle ≤ 50%, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 8. Test Circuit and Voltage Waveforms for Receiver Propagation Delay Time
5V
SQDLAJ
Rext
Generator
(see Note A)
50 Ω
3V
Input
Cext
1.5 V
0V
td(unsq)
RXI +
1.5 V
Open
1.5 V
VOH
RXO
RXI −
SQTHAJ
SQRXO
SQO
Output
1.3 V
1.3 V
VOL
Output
SQDLI
VOLTAGE WAVEFORMS
TEST CIRCUIT
Figure 9. Test Circuit and Voltage Waveforms for Unsquelch Duration Time
NOTE A: The input pulse is supplied by a generator having the following characteristics: PRR ≤ 100 kHz, duty cycle ≤ 50%, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
2−12
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