Agilent HCPL-810J PLC Powerline DAA IC Data Sheet EMC performance. Application robustness is enhanced by the inherent properties of optoisolation devices, to effectively block the transfer of damaging surge transients. Description The HCPL- 810J is a galvanically isolated Powerline Data Access Arrangement IC. It provides the key features of isolation, Tx line driver and Rx amplifier as required in a powerline modem application. Used together with a simple LC coupling circuit, the HCPL- 810J offers a highly integrated, cost effective Analogue Front End (AFE) solution. Optical coupling technology provides very high isolation mode rejection, facilitating excellent EMI and Features • Highly Efficient Tx Line Driver • Built-in Rx Amplifier • Load Detection Function • Under-Voltage Detection • Over-Temperature Shutdown Excellent transmitter performance is achieved with the use of a high efficiency, low distortion line driver stage. Transmitter robustness is further enhanced with integrated load detection and over- temperature protection functions. • Temperature Range: −40°C to +85°C • Regulatory Approvals (pending): UL, CSA, IEC/EN/DIN EN 60747-5-2 Applications • Automatic Meter Reading (AMR) • Powerline Modem • Home Automation/Control The HCPL- 810J is designed to work with various transceiver ICs and significantly simplify the implementation of a powerline modem. • Security and Surveillance • General Purpose Isolated Transceiver • Internet Appliances Connection Diagram 1 TX-EN 2 TX 3 Powerline Transceiver IC (ENDEC) 4 5 6 RX STATUS VCC1 7 8 Tx-en GND2 Tx-in Tx-out Rx-PD-out Rx-Amp-in VCC2 Tx-PD-out Status Tx-LD-in Rx-out Cext VCC1 GND1 Rx-in Rref 16 GND2 15 14 VCC2 13 12 Filter 11 GND2 10 Filter L 9 HCPL-810J N GND1 GND2 GND2 CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. Block Diagram - --out Tx-PD - --in Tx-LD 13 1 Tx-en - Tx-in - 12 AGC 2 Tx LED Driver G T2 Tx TIA 15 Tx-out Shield V CC1 Tx-en Detection 7 Line Driver Control Over --Temp Detection GND1 8 14 16 Rx -out - 5 6 GND2 Control IC V CC2 UVD 11 Load Detection Status V CC2 Status Logic Status Detection Rx TIA Rx LED Driver Amp 9 10 C ext R ref Rx --in G R2 Shield 4 Rx --Amp-in - Line IC 3 Rx -PD - -out - Pin Descriptions Package Pin Out 2 Pin No. Symbol Description 1 Tx-en Transmit Enable Input 2 Tx-in Transmit Input Signal 3 Rx-PD-out Rx Photodetector Output 1 Tx -en GND2 2 Tx -in Tx -out 15 4 Rx-Amp-in Receiver Output Amplifier Input 3 Rx -PD -out V CC2 14 5 Status Signal indicating Line Condition 4 Rx -Amp -in Tx -PD -out 13 6 Rx-out Receiving Signal Output 7 Status VCC1 5 V Power Supply 5 8 GND1 VCC1 Power Supply Ground 6 Rx -out 9 Rref Sets Line Driver biasing current, typically 24 kΩ 7 V CC1 10 Rx-in Receiving Signal Input from Powerline 11 GND1 Cext External Capacitor 8 12 Tx-LD-in Tx Line Driver Input 13 Tx-PD-out Tx Photodetector Output 14 VCC2 5 V Power Supply 15 Tx-out Transmit Signal Output to Powerline 16 GND2 VCC2 Power Supply Ground 16 Tx -LD -in 12 C ext 11 Rx -in 10 R ref 9 Ordering Information Specify part number followed by option number (if desired). Example: HCPL-810J-XXX No option = 16-Lead, Surface Mt. package, 45 per tube. 500 = Tape and Reel Packaging Option, 850 per reel. Option data sheets available. Contact Agilent Technologies sales representative, authorized distributor, or visit our WEB site at www.agilent.com/view/optocouplers. Package Outline Drawings 16-Lead Surface Mount 0.018 (0.457) 0.050 (1.270) 16 15 14 13 12 11 10 A 810J YYWW 1 2 3 4 5 TYPE NUMBER DATE CODE 9 0.295 ± 0.010 (7.493 ± 0.254) 6 7 NOTES: 1. INITIAL AND CONTINUED VARIATION IN THE COLOR OF THE HCPL-810J’s WHITE MOLD COMPOUND IS NORMAL AND DOES NOT AFFECT DEVICE PERFORMANCE OR RELIABILITY. 2. FLOATING LEAD PROTRUSION IS 0.006 (0.15) MAX. 8 0.406 ± 0.10 (10.312 ± 0.254) 0.345 ± 0.010 (8.986 ± 0.254) 9˚ 0.018 (0.457) 0.138 ± 0.005 (3.505 ± 0.127) 0–8˚ 0.025 MIN. 0.408 ± 0.010 (10.160 ± 0.254) DIMENSIONS IN INCHES (MILLIMETERS). ALL LEADS TO BE COPLANAR ± 0.002 0.008 ± 0.003 (0.203 ± 0.076) STANDOFF Land Pattern Recommendation 0.458 (11.63) 0.085 (2.16) 0.025 (0.64) DIMENSIONS IN INCHES (MILLIMETERS) 3 Package Characteristics All specifications and figures are at the nominal (typical) operating conditions of VCC1 = 5 V, GND1 = 0 V, VCC2 = 5 V, GND2 = 0 V and TA = +25°C. Parameter Symbol Control IC − Line IC Momentary Withstand Voltage VISO Resistance (Control IC − Line IC) RI-O Capacitance (Control IC – Line IC) Min. Typ. Max. 3750 Units Test Conditions Note Vrms RH< 50%, t = 1 min., TA = 25°C 1, 2, 3 >109 Ω VI-O = 500 Vdc 3 CI-O 1.4 pF f = 1 MHz Control IC to Ambient Thermal Resistance θIA Line IC to Ambient Thermal Resistance θOA 83 °C/W 1 oz. trace, 2-layer 4 PCB, Still air, TA = 25°C 85 Notes: 1. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 4500 Vrms for 1 second (leakage detection current limit, II-O ≤ 5 µA). This test is performed before the 100% production test for partial discharge (method b) shown in IEC/EN/DIN EN 60747-5-2 Insulation Characteristics Table, if applicable. 2. The Control IC-Line IC Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as a Control IC-Line IC continuous voltage rating. For the continuous voltage rating refer to your equipment level safety specification or IEC/EN/DIN EN 60747-5-2 Insulation Characteristics Table. 3. Device is considered as a two terminal device: pins 1 - 8 shorted together and pins 9 - 16 shorted together. 4. Maximum power dissipation in Control side and Line side IC's needs to be limited to ensure that their respective junction temperature is less than 125°C. The maximum permissible power dissipation is dependent on the thermal impedance and the ambient temperature. Details on the typical thermal impedances are given in the Package Characteristics. Further details on applying this to an actual application can be found in the Application Information section under Thermal Considerations. Solder Reflow Temperature Profile 300 TEMPERATURE (˚C) PREHEATING RATE 3˚C + 1˚C/–0.5˚C/SEC. REFLOW HEATING RATE 2.5˚C ± 0.5˚C/SEC. PEAK TEMP. 245˚C PEAK TEMP. 240˚C PEAK TEMP. 230˚C 200 2.5˚C ± 0.5˚C/SEC. 30 SEC. 160˚C 150˚C 140˚C SOLDERING TIME 200˚C 30 SEC. 3˚C + 1˚C/–0.5˚C 100 PREHEATING TIME 150˚C, 90 + 30 SEC. 50 SEC. TIGHT TYPICAL LOOSE 0 0 ROOM TEMPERATURE 4 50 100 150 TIME (SECONDS) 200 250 Regulatory Information The HCPL-810J is pending for approval by the following organizations: IEC/EN/DIN EN 60747- 5- 2 CSA UL Approved under CSA Acceptance Notice #5, File CA 88324. Recognized under UL 1577, Approved under: component recognition program, IEC 60747-5-2:1997 + A1:2002 File E55361. EN 60747-5-2:2001 + A1:2002 DIN EN 60747-5-2 (VDE 0884 Teil 2):2003-01 with VIORM = 891 Vpeak. IEC/EN/DIN EN 60747-5-2 Insulation Characteristics (1) Description Symbol Characteristic Installation classification per DIN VDE 0110/1.89, Table 1 For rated mains voltage ≤ 150 Vrms For rated mains voltage ≤ 300 Vrms For rated mains voltage ≤ 600 Vrms I – IV I – III I – II Climatic Classification 55/100/21 Pollution Degree (DIN VDE 0110/1.89) 2 Maximum Working Insulation Voltage Unit VIORM 891 VPEAK VPR 1670 VPEAK VPR 1336 VPEAK Highest Allowable Over-voltage (2) (Transient Over-voltage tini = 10 sec) VIOTM 6000 VPEAK Safety-limiting values − maximum values allowed in the event of a failure Case Temperature Control Side Power (3) Line Side Power (3) TS PS, INPUT PS, OUTPUT 175 400 1500 °C mW mW Insulation Resistance at TS, VIO = 500 V RS >109 Ω Input to Output Test Voltage, Method b (2) VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec, Partial Discharge < 5 pC Input to Output Test Voltage, Method a (2) VIORM x 1.5 = VPR, Type and Sample Test, tm = 60 sec, Partial Discharge < 5 pC Notes: 1. Isolation characteristics are guaranteed only within the safety maximum ratings that must be ensured by protective circuits in application. Surface mount classification is class A in accordance with CECCOO802. 1600 2. Refer to the optocoupler section of the Isolation and Control Component Designer’s Catalog, under Product Safety Regulations section, (IEC/EN/DIN EN 60747-5-2) for a detailed description of Method a and Method b partial discharge test profiles. 1200 PS – POWER – mW 3. Refer to the following figure for dependence of PS, INPUT and PS, OUTPUT on case temperature. PS, OUTPUT 1400 PS, INPUT 1000 800 600 400 200 0 0 25 50 75 100 125 150 175 200 TS – CASE TEMPERATURE – °C ° 5 Insulation and Safety Related Specifications Parameter Symbol Value Unit Condition Minimum External Air Gap (Clearance) L(101) 8.3 mm Measured from input terminals to output terminals, shortest distance through air. Minimum External Tracking (Creepage) L(102) 8.3 mm Measured from input terminals to output terminals, shortest distance path along body. 0.5 mm Through insulation distance of conductor to conductor, usually the straight-line distance between the emitter and detector. >175 Volts DIN IEC 112/VDE 0303 Part 1 Minimum Internal Plastic Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) CTI Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1) Absolute Maximum Ratings Parameter Symbol Min. Max. Unit Storage Temperature TS −55 125 °C Ambient Operating Temperature TA −40 85 °C Junction Temperature TJ 125 °C Supply Voltage 1 VCC1 −0.5 5.5 V Supply Voltage 2 VCC2 −0.5 5.5 V Transmit Output Voltage VTx-out −0.5 VCC2 V Transmit Input Signal Voltage VTx-in −0.5 VCC1 V Transmit Enable Voltage VTx-en −0.5 VCC1 V Receiving Input Signal Voltage VRx-in −0.5 VCC2 V Control-Side Power Dissipation PI 200 mW Line-Side Power Dissipation PO 1000 mW Solder Reflow Temperature Profile (See Solder Reflow Temperature Profile Section) Note 1 Notes: 1. Maximum power dissipation in Control side and Line side IC's needs to be limited to ensure that their respective junction temperature is less than 125°C. The maximum permissible power dissipation is dependent on the thermal impedance and the ambient temperature. Details on the typical thermal impedances are given in the Package Characteristics. Further details on applying this to an actual application can be found in the Application Information section under Thermal Considerations. Recommended Operating Conditions Parameter Symbol Min. Ambient Operating Temperature TA −40 Input Supply Voltage VCC1 4.75 Output Supply Voltage VCC2 4.75 Tx-in Signal Current ITx-in Typ. Max. Unit 85 °C 5 5.25 V 5 5.25 V 250 µAPP Note 1 Notes: 1. The transmitter input impedance is very low, this is meant for signal current input. Transmitter performance is optimized at 250 µAPP input signal, an external series resistor with nominal value of 2 kΩ would be required if the input signal is 0.5 VPP. 6 Electrical Specifications Unless otherwise noted, for sinusoidal waveform input and reference resistor Rref = 24 kΩ, all typical values are at TA = 25°C, VCC1 = 5 V, VCC2 = 5 V; all Minimum/Maximum specifications are at Recommended Operating Conditions. General Parameter VCC1 Supply Current VCC2 Supply Current Symbol Min. Typ. Max. Unit Test Condition Fig. ICC1 6 20 mA VTx-en = 0 V 1 20 35 mA VTx-en = 5 V 1 22 30 mA VTx-en = 0 V 2 40 70 mA VTx-en = 5 V 2, 3, 4 V IOH = −4 mA 1 V VCC2 = 3.5 V, IOL = 4 mA 4.3 V 1 130 °C 2 0.6 APP VTx-en = 5 V, f = 132 kHz 5, 13 80 dB VTx-en = 0 V, f = 132 kHz 6, 14 ICC2 Status Logic High Output VOH Status Logic Low Output VOL VCC2 Under Voltage Detection VUVD Junction Over-Temperature Threshold VCC1−1 3.8 Tth Load Detection Threshold Isolation Mode Rejection Ratio IMRR 4 Note 3 Notes: 1. Threshold of falling VCC2 with hysteresis of 0.15 V (typ.). 2. Threshold of rising junction temperature with hysteresis of 15°C (typ.). 3. IMRR is defined as the ratio of the signal gain (measured at Rx-PD-out with signal applied to Rx-in) to the isolation mode gain (measured at Rx-PD-out with Rx-in connected to GND2 and the isolation mode voltage, VIM, applied between GND1 and GND2), expressed in dB. 7 Electrical Specifications (Cont.) Unless otherwise noted, for sinusoidal waveform input and reference resistor Rref = 24 kΩ, all typical values are at TA = 25°C, VCC1 = 5 V, VCC2 = 5 V; all Minimum/Maximum specifications are at Recommended Operating Conditions. Transmitter Parameter Symbol Transmit Enable Threshold Volt- Vth, Tx-en age Min. Typ. 0.8 Max. Unit Test Condition Fig. Note 2.4 V VTx-en = 5 V, ITx-in = 250 µAPP, f = 132 kHz, Tx-PDout no load 15 1 VPP VTx-en = 5 V, ITx-in = 250 µAPP, f = 132 kHz, TA = 25°C 7, 8, 9 Set-up Time (Tx-PD-out) ts, Tx 10 µs AGC Settling Time tAGC 180 µs Tx Photodetector Output Voltage (Tx-PD-out) Bandwidth (Tx-PD-out) 2.8 3.3 3.6 BWTxPD 1 MHz VTx-en = 5 V, ITx-in = 250 µAPP Tx Photodetector Output Imped- ZO, TxPD ance (Tx-PD-out) 1 Ω VTx-en = 5 V, f = 132 kHz 2 Line Driver (LD) Power Supply (VCC2) Rejection Ratio PSRR 55 dB 50 Hz ripple, Vripple = 200 mVPP Input Impedance ZI, LD 10 kΩ VTx-en = 5 V, f = 132 kHz DC Biased Voltage VBias, LD 2.27 V VTx-en = 5 V Gain GT2 V/V VTx-en = 5 V, f = 132 kHz, Tx-out no load, TA = 25°C 1.8 2 2.2 2nd Harmonic Distortion (Tx-out) HD2LD −60 dB 3rd Harmonic Distortion (Tx-out) HD3LD −65 dB VTx-en= 5 V, VTx-out= 3.6 VPP, f=132 kHz, Tx-out load 50Ω, TA=25°C Output Impedance (Tx-out) 0.5 Ω VTx-en = 5 V, f = 132 kHz 7.5 kΩ VTx-en = 0 V, f = 132 kHz 2 APP VTx-en = 5 V, VTx-LD-in = 1.8 VPP, f = 132 kHz, tP ≤ 50 µs Short-Circuit Output Current ZO, LD IOS 10 3, 4 Notes: 1. Time from transmit is enabled (VTx-en is set to logic high) until output (Tx-PD-out) is available. See Figure 18 in the Application Information section. 2. Time from output (Tx-PD-out) is available until Tx-PD-out signal reaches 66% of its steady state level. See Figure 18 in the Application Information section. 3. To keep the junction temperature as close to the ambient temperature as possible, pulse testing method is used. The device is transmit-enabled within the pulse duration time, tP. Thermal effects must be considered separately. 4. Maximum power dissipation in Control side and Line side IC's needs to be limited to ensure that their respective junction temperature is less than 125°C. The maximum permissible power dissipation is dependent on the thermal impedance and the ambient temperature. Details on the typical thermal impedances are given in the Package Characteristics. Further details on applying this to an actual application can be found in the Application Information section under Thermal Considerations. 8 Electrical Specifications (Cont.) Unless otherwise noted, for sinusoidal waveform input and reference resistor Rref = 24 kΩ, all typical values are at TA = 25°C, VCC1 = 5 V, VCC2 = 5 V; all Minimum/Maximum specifications are at Recommended Operating Conditions. Receiver Parameter Symbol Min. Typ. Max. Unit Test Condition Input Impedance ZI, Rx 4 kΩ VTx-en = 0 V, f = 132 kHz Output Impedance (Rx-PD-out) ZO, RxPD 30 Ω VTx-en = 0 V, f = 132 kHz Input Referred Noise Vnr 70 Bandwidth (Rx-PD-out) BWRxPD 500 Gain GR1 20 nV/ Hz VTx-en = 0 V, VRx-in = 0 VPP kHz VTx-en = 0 V dB VTx-en = 0 V, VRx-in = 0.05 VPP, f = 132 kHz Set-up Time (Rx-PD-out) ts, Rx 10 µs Fig. Note 11 VTx-en = 0 V, f = 132 kHz Receiver Output Amplifier (RxAMP) DC Biased Voltage VBias, Rx 2.27 V Output Impedance ZO, RxA 20 Ω VTx-en = 0 V, f = 132 kHz Gain Bandwidth Product GBWRxA 28 MHz VTx-en = 0 V, f = 132 kHz, 12 VRx-in = 0.1 VPP, GR2 = −20, feedback resistor 20 kΩ 9 Typical Performance Plots Unless otherwise noted, all typical plots are at TA = 25°C, VCC1 = 5 V, VCC2 = 5 V, sinusoidal waveform input, signal frequency f = 132 kHz, ITx-in = 250 µAPP, and Rref = 24 kΩ. 45 25 ICC2 – SUPPLY CURRENT – mA ICC1 – SUPPLY CURRENT – mA 40 20 15 10 5 35 30 25 20 15 10 Rx Tx 0 --50 -25 0 25 50 75 Rx 5 Tx 0 -50 100 TA – AMBIENT TEMPERATURE – °C Figure 1. VCC1 supply current vs. temperature. 0 25 50 75 100 Figure 2. VCC2 supply current vs. temperature. 300 100 90 VTx-en = 5 V 80 250 ICC2 – SUPPLY CURRENT – mA ICC2 – SUPPLY CURRENT – mA -25 TA – AMBIENT TEMPERATURE – °C 70 200 60 150 50 40 100 30 20 50 10 0 0 5 10 15 20 0 25 Figure 3. VCC2 supply current vs. reference resistor. ISOLATION MODE REJECTION RATIO – dB NORMALIZED AT 25°C 1.3 1.2 1.1 1 0.9 0.8 0.7 -25 0 25 50 75 100 TA – AMBIENT TEMPERATURE – °C Figure 5. Normalized load detection threshold vs. temperature. 10 0.4 0.6 0.8 1 1.2 1.4 Figure 4. VCC2 supply current vs. Tx output current. 1.4 0.6 -50 0.2 ITx-out – Tx-out OUTPUT CURRENT – APP Rref – REFERENCE RESISTOR – kÙ 90 85 80 75 70 65 60 55 50 0 0.5 1 1.5 f – FREQUENCY – MHz Figure 6. Isolation mode rejection ratio vs. frequency. 2 Typical Performance Plots (Cont.) Unless otherwise noted, all typical plots are at TA = 25°C, VCC1 = 5 V, VCC2 = 5 V, sinusoidal waveform input, signal frequency f = 132 kHz, ITx-in = 250 µAPP, and Rref = 24 kΩ. NORMALIZED AT 25°C 1.4 1.2 1 0.8 0.6 0.4 -50 4 VTx-PD-out – Tx-PD-out OUTPUT VOLTAGE – VPP 1.6 -25 0 25 50 75 3 2 1 0 100 0 TA – AMBIENT TEMPERATURE – °C 50 100 150 200 250 ITx-in – Tx INPUT CURRENT – µAPP Figure 7. Normalized Tx-PD-out output voltage vs. temperature. Figure 8. Tx-PD-out output voltage vs. Tx-in input current. 1.01 1.2 ITx-in = 65 µAPP 1.005 NORMALIZED AT 25°C NORMALIZED AT 132 kHz 1 0.8 0.6 0.4 1 0.995 0.2 100 k 1M 0.99 -50 10 M Figure 9. Normalized Tx-PD-out output voltage vs. frequency. 1.2 25 50 75 240 AOL – RxAMP VOLTAGE GAIN – dB 100 0.8 0.6 0.4 0.2 GAIN 220 PHASE 200 90 180 80 160 70 140 60 120 50 100 40 80 30 60 20 40 10 20 0 100 k 1M 100 Figure 10. Normalized line driver gain vs. temperature. 110 1 NORMALIZED AT 132 kHz 0 120 VRx-in = 50 mVPP 0 10 k -25 TA – AMBIENT TEMPERATURE – °C f – FREQUENCY – Hz 10 M f – FREQUENCY – Hz Figure 11. Normalized Rx-PD-out output voltage vs. frequency. 10 100 1k 10 k 100 k 1M PHASE – DEGREES 0 10 k 0 10 M f – FREQUENCY – Hz Figure 12. RxAMP gain and phase vs. frequency. 11 Test Circuit Diagrams Unless otherwise noted, all test circuits are at TA = 25°C, VCC1 = 5 V, VCC2 = 5 V, sinusoidal waveform input, and signal frequency f = 132 kHz. 1 VCC1 2 3 4 5 SCOPE 6 7 VCC1 8 100 nF Tx-en 16 GND2 Tx-in Tx-out Rx-PD-out 1 µF Rx-Amp-in 13 Tx-PD-out Status Tx-LD-in Rx-out Cext VCC1 12 VCC2 100 nF 100 µF 100 nF VIN = 1.5 VPP 11 GND2 1 µF 10 Rx-in GND1 RL 14 VCC2 GND2 2.5 Ω 15 100 nF 9 Rref Rref HCPL-810J 24 kΩ GND1 GND2 Figure 13. Load detection test circuit. 1 GND1 2 VOUT 3 SCOPE 100 nF 6 7 VCC1 Tx-in Tx-out 8 15 100 µF 13 5V 12 Status Tx-LD-in Rx-out Cext 11 1 µF 10 Rx-in GND1 100 nF 14 Tx-PD-out VCC1 100 nF 16 VCC2 Rx-Amp-in 5 GND1 GND2 Rx-PD-out 4 1 kΩ Tx-en 100 nF 9 Rref 24 kΩ Rref HCPL-810J VIM = 10 VPP GND1 GND2 Figure 14. Isolation mode rejection ratio test circuit. 1 VIN = 0.5 VPP Tx-en 2 100 nF 2 kΩ Tx-in 3 5 6 7 VCC1 VCC2 Rx-Amp-in PULSE GEN. GND1 Tx-out Rx-PD-out 4 VPULSE = 5 V, fPULSE ≤ 1 kHz GND2 Tx-PD-out Status Tx-LD-in Rx-out Cext VCC1 8 Rx-in GND1 100 nF Rref 16 GND2 15 100 nF 100 µF 14 VCC2 13 VOUT 12 11 1 µF 10 100 nF 9 Rref HCPL-810J 24 kΩ GND1 GND2 Figure 15. Tx-PD-out enable/disable time test circuit. VCC1 1 2 GND1 100 nF 2 kΩ 3 4 5 6 7 VCC1 8 100 nF Tx-en GND2 Tx-in Tx-out Rx-PD-out Rx-Amp-in VCC2 Tx-PD-out Status Tx-LD-in Rx-out Cext VCC1 GND1 HCPL-810J GND1 Figure 16. Line driver bandwidth test circuit. 12 Rx-in Rref 16 VOUT 15 50 Ω RL 14 1 µF 13 12 100 nF 100 nF 11 100 nF 9 Rref VCC2 100 µF GND2 VIN = 1 VPP f = 10 k ~ 10 MHz 1 µF 10 GND2 24 kΩ GND2 Applications Information 1 Tx-en Tx-in C1 100 nF R1 R3 2 kΩ 2 3 100 nF 4 5 kΩ Rx-out Status 5 R2 10 kΩ 6 7 VCC1 8 100 nF Tx-en GND2 Tx-in Tx-out Rx-PD-out Rx-Amp-in VCC2 Tx-PD-out Status Tx-LD-in Rx-out Cext VCC1 Rx-in GND1 Rref 16 GND2 15 R4 2Ω 14 VCC2 13 100 nF 12 Filter 11 10 GND2 1 µF 100 µF GND2 GND2 L2 C2 Filter L X2 1 µF 9 D1 Rref 24 kΩ HCPL-810J GND1 L1 330 µH N GND1 GND2 GND2 Figure 17. Schematic of HCPL-810J application for FSK modulation scheme. Typical application for FSK modulation scheme The HCPL- 810J is designed to work with various transceivers and can be used with a variety of modulation methods including ASK, FSK and BPSK. Figure 17 shows a typical application in a powerline modem using Frequency Shift Keying (FSK) modulation scheme. Transmitter The analogue Tx input pin is connected to the modulator via an external coupling capacitor C1 and a series resistor R3 (see Figure 17). Optimal performance is obtained with an input signal of 250 µAPP. E.g., for a modulator with an output signal of 0.5 VPP using a coupling capacitor of 100 nF, the optimal series resistor R3 would be 2 kΩ. This AGC circuit compensates for variations in the input signal level presented at Tx- in and variations in the optical channel over temperature and time. The Tx- PD- out output signal is effectively stabilized for input Tx- in signals of between 150 µAPP and 250 µAPP (see Figure 8). The AGC circuit starts to function 10 µs after the Tx- en signal is set to logic high. After a period of 180 µs the Tx- PDout signal typically reaches 66% of its steady state level (see Figure 18). To ensure correct operation of the internal circuitry, an external 1 µF capacitor needs to be connected from pin 11 to GND2. The optical signal coupling technology used in the HCPL810J transmit path achieves very good harmonic distortion, which is usually significantly better than the distortion performance of the modulated input signal. However to meet the requirements of some international EMC regulations it is often necessary to filter the modulated input signal. The optimal position for such a filter is between pins 13 and 12 as shown in Figure 17. A possible band- pass filter topology is shown in Figure 19, some typical values of the components in this filter are listed in Table 1. 5 0 µs/Div Tx-en 5 V/Div Tx AGC To ensure a stable and constant output voltage at Tx- PD- out, the HCPL- 810J includes an Automatic Gain Control (AGC) circuit in the isolated transmit signal path. Tx-PD-out 1 V/Div ts, Tx tAGC Figure 18. Tx-PD-out AGC response time. 13 R5 Filter input L2 Tx Filter output L Rx L3 C2 1µF C3 X2 L1 N GND2 GND2 Figure 19. An example of a band-pass filter for transmit. To compensate for the attenuation in the filter, the line driver stage has 6 dB gain. To prevent the line driver output from saturating, it is therefore important to achieve 6 dB of attenuation between Tx- PD- out (pin 13) and Tx- LD- in (pin 12) either by the inherent filter attenuation or by other means. Transmitter Line Driver The line driver is capable of driving powerline load impedances with output signals up to 4 VPP. The internal biasing of the line driver is controlled externally via a resistor Rref connected from pin 9 to GND2. The optimum biasing point value for modulation frequencies up to 150 kHz is 24 kΩ. For higher frequency operation with certain modulation schemes, it may be necessary to reduce the resistor value to enable compliance with international regulations. Figure 20. LC coupling network. The output of the line driver is coupled onto the powerline using a simple LC coupling circuit as shown in Figure 20. Refer to Table 1 for some typical component values. Capacitor C2 and inductor L1 attenuate the 50/60 Hz powerline transmission frequency. A suitable value for L1 can range in value from 200 µH to 1 mH. To reduce the series coupling impedance at the modulation frequency, L2 is included to compensate the reactive impedance of C2. This inductor should be a low resistive type capable of meeting the peak current requirements. To meet many regulatory requirements, capacitor C2 needs to be an X2 type. Since these types of capacitors typically have a very wide tolerance range of 20%, it is recommended to use as low Q factor as possible for the L2/C2 combination. Using a high Q coupling circuit will result in a Table 1. Typical component values for band-pass filter and LC coupling network. Carrier Frequency (kHz) Band-Pass Filter LC Coupling L3 (µH) C3 (nF) L2 (µH) C2 (nF) 110 680 3.3 15 150 120 680 2.7 10 220 132 680 2.2 6.8 220 150 680 1.8 6.8 220 14 wide tolerance on the overall coupling impedance, causing potential communication difficulties with low powerline impedances. Occasionally with other circuit configurations, a high Q coupling arrangement is recommended, e.g., C2 less than 100 nF. In this case it is normally used as a compromise to filter out of band harmonics originating from the line driver. This is not required with the HCPL- 810J. Although the series coupling impedance is minimized to reduce insertion loss, it has to be sufficiently large to limit the peak current to the desired level in the worst expected powerline load condition. The peak output current is effectively limited by the total series coupling resistance, which is made up of the series resistance of L2, the series resistance of the fuse and any other resistive element connected in the coupling network. To reduce power dissipation when not operating in transmit mode the line driver stage is shut down to a low power high impedance state by pulling the Tx- en input (pin 1) to logic low state. The high impedance condition helps minimize attenuation on received signals. Receiver The received signal from the powerline is often heavily attenuated and also includes high level out of band noise. Receiver performance can be improved by positioning a suitable filter prior to the Rx- in input (pin 10). To counter the inevitable attenuation on the powerline, the HCPL- 810J receiver circuit includes a fixed 20 dB front- end gain stage. If desired, this fixed gain can be reduced to unity gain by inserting an impedance of 33 kΩ in the receiver signal path. It is however recommended to maintain the fixed gain of 20 dB at this position and reduce the overall signal gain elsewhere if required. This configuration will result in the best SNR and IMRR. The optical isolated Rx signal appears at Rx- PD- out (pin 3). This signal is subsequently AC coupled to the final gain stage via a capacitor. The final gain stage consists of an op- amp configured in an inverting configuration and DC biased at 2.27 V. The actual gain of this gain stage is user programmable with external resistors R1 and R2 as shown in Figure 17. The signal output at Rx- out (pin 6) is buffered and may be directly connected to the demodulator or ADC, using AC coupling if required. The next feature is the overtemperature shutdown. This particular feature protects the line driver stage from overtemperature stress. Should the IC junction temperature reach a level above 130°C, the line driver circuit is shut down, simultaneously the output of Status (pin 5) is pulled to the logic low state. The final feature is load detection function. The powerline impedance is quite unpredictable and varies not just at different connection points but is also time variant. The HCPL- 810J includes a current sense feature, which may be utilized to feedback information on the instantaneous powerline load condition. Should the peak current reach a level greater than 0.6 APP, the output of Status pin is pulled to a logic low state for the entire period The first feature is the VCC2 Under Voltage Detection (UVD). In the event of VCC2 dropping to a voltage less than 4 V, the output status pin is switched to a logic low state. External Transient Voltage Protection To protect the HCPL- 810J from high voltage transients caused by power surges and disconnecting/connecting the modem, it is necessary to add an external 6.8 V bi- directional transient voltage protector (as component D1 shown in Figure 17). Additional protection from powerline voltage surges can be achieved by adding an appropriate Metal Oxide Varistor (MOV) across the powerline terminals after the fuse. Table 2. Status pin logic output. Mode Normal VCC2 < 4V Over-Temperature ITx-out < −0.3 A Receiver Mode High Low - - Transmitter Mode High Low Low Low (pulsed) 2 µs/Div Tx-out (pin 15) 0.5 A/Div Ith tth Internal Protection and Sensing The HCPL- 810J includes several sensing and protection functions to ensure robust operation under wide ranging environmental conditions. the peak current exceeds - 0.3 A, as shown in Figure 21. Using the period of the pulse together with the known coupling impedance, the actual powerline load can be calculated. Table 2 shows the logic output of the Status pin. Status (pin 5) 2 V/Div tth Figure 21. Transmit output load detection. 15 + 78L05 C* VOUT 5V 630 mA L GND X2 1.5 µF/3.3 µF - 100 nF 470 µH 120 mA VIN 1000 µF 9.1 V 1 W 220 kÙ VARISTOR N * 1.5µF X2 for 230V mains, 3.3µF X2 for 110V mains GND2 Figure 22. A simple low cost non-isolated power supply. VCC2 Power Supply Requirements Thermal Considerations The recommended voltage regulator to supply VCC2 is a low cost 78L05 or equivalent. To minimize harmonic distortion, it is recommended to connect a tantalum decoupling capacitor of at least 10 µF together with a 100 nF ceramic capacitor in parallel. The capacitors should be positioned as close as possible to the supply input pin. The supply voltage for the regulator can be supplied from the system level power supply transformer (powerline side winding). Alternatively, the supply can be derived directly from the powerline via a simple low cost circuit as shown in Figure 22. The high efficiency line driver used in the HCPL- 810J ensures minimum internal power dissipation, even for high peak output currents. Despite this, operating the line driver continuously with high output currents at elevated ambient temperatures can cause the peak junction temperature to exceed 125°C and/or resulting in the triggering of the thermal protection. To prevent this from happening, when operating the line driver continuously with high output currents, an ambient temperature derating factor needs to be applied. A typical derating curve is shown in Figure 23. In this case the assumption is that the transmitter is operating continuously in still air with a typical 2- layer Printed- Circuit Board (PCB). However, it should be noted that operating the transmitter discontinuously for short periods of time will allow lower derating or even no derating at all. Conversely operating the line driver continuously with a poor PCB layout and/or with restricted air convection could result in the requirement for a larger derating factor. MAXIMUM POWER DISSAPATION – W 1.4 1.2 1 0.8 0.6 0.4 0.2 0 --40 -15 - 10 35 60 TA – AMBIENT TEMPERATURE – °C Figure 23. Power derating vs. temperature. www.agilent.com/semiconductors For product information and a complete list of distributors, please go to our web site. Data subject to change. Copyright 2003 Agilent Technologies, Inc. March 18, 2004 5989-0717EN 85