[AKD4691-A] AKD4691-A Evaluation board Rev.0 for AK4691 GENERAL DESCRIPTION The AKD4691 is an evaluation board for the AK4691, 16bit 4ch ADC + 2ch DAC with built-in MIC/Headphone/Speaker Amplifier. The AKD4691 can evaluate A/D converter and D/A converter separately in addition to loop-back mode (A/D → D/A). The AKD4691 also has the digital audio interface and can achieve the interface with digital audio systems via opt-connector. Ordering guide AKD4691-A --- Evaluation board for AK4691 (Cable for connecting with printer port of IBM-AT compatible PC and control software are packed with this. This control software does not operate on Windows NT.) FUNCTION • DIT/DIR with optical input/output • 10pin Header for Digital Audio I/F • RCA connector for an external clock input • 10pin Header for Serial Control I/F GND TVDD DVDD MVDD AVDD SVDD 5V 3.0 V REG PORT2 Opt Out DIT Opt In AK4114 TVDD1 DVDD TVDD2 MVDD AVDD SVDD LVDD MIC1/BEEP MIC2 DIR LIN/RIN PORT1 LOUT Digital Audio I/F 10Pin Header ROUT AK4691 HP Jack PORT3 HPL HPR Control I/F 10Pin Header SPP PORT4 SPN SPK JACK Figure 1. AKD4691 Block Diagram * Circuit diagram and PCB layout are attached at the end of this manual. <KM089100> 2007/06 -1- [AKD4691-A] Operation sequence (1) Set up the power supply lines. (1-1) In case of using the regulator. Set up the jumper pins. JP2 JP3 JP REG SVDD-SEL State Short Short JP4 AVDD-SEL JP5 DVDD-SEL JP6 TVDD-SEL JP7 VCC-SEL JP8 MVDD-SEL Short Short Short Short Short Set up the power supply lines. [5V] (red) = 5.0V [D3V] (orange) [AGND] (black) [DGND] (black) : for LVDD of AK4691 (typ. 5.0V) for regulator (3.0V output : SVDD, MVDD, AVDD, DVDD, TVDD1 and TVDD2 of AK4691 and logic) = 2.7 ∼ 3.6V : for AK4114 and logic (typ. 3.3V) = 0V : for analog ground = 0V : for logic ground (1-2) In case of using the power supply connectors. Set up the jumper pins. JP2 JP3 JP REG SVDD-SEL State Open Open JP4 AVDD-SEL JP5 DVDD-SEL JP6 TVDD-SEL JP7 VCC-SEL JP8 MVDD-SEL Open Open Open Open Open Set up the power supply lines. [5V] (red) = 2.6 ~ 5.5V [SVDD] (orange) = 2.6 ~ 3.6V [MVDD] (orange) = 2.6 ~ 5.5V [AVDD] (orange) = 2.6 ~ 3.6V [DVDD] (orange) = 2.6 ~ 3.6V [TVDD] (orange) = 1.6 ~ 3.6V [VCC] (orange) = 1.6 ∼ 3.6V [D3V] (orange) = 2.7 ∼ 3.6V [AGND] (black) = 0V [DGND] (black) = 0V : for LVDD of AK4691 (typ. 3.0V) : for SVDD of AK4691 (typ. 3.0V) : for MVDD of AK4691 (typ. 3.0V) : for AVDD of AK4691 (typ. 3.0V) : for DVDD of AK4691 (typ. 3.0V) : for TVDD1, TVDD2 of AK4691 (typ. 3.0V) : for logic (typ. 3.0V: This voltage must be same as TVDD.) : for AK4114 and logic (typ. 3.3V) : for analog ground : for logic ground * Each supply line should be distributed from the power supply unit. (2) Set up the evaluation mode, jumper pins and DIP switch. (See the followings.) (3) Power on. The AK4691 and AK4114 should be resets once bringing SW1 (PDN) and SW2 (DIR) “L” upon power-up. <KM089100> 2007/06 -2- [AKD4691-A] Evaluation mode In case of the AK4691 evaluation using the AK4114, it is necessary to correspond to audio interface format for the AK4691 and AK4114. About the AK4691’s audio interface format, refer to datasheet of the AK4691. About the AK4114’s audio interface format, refer to Table 2. The AK4114 operates at fs of 32kHz or more. If the fs is slower than 32kHz, please use other mode. In addition, MCLK of AK4114 supports 256fs and 512fs. When evaluate it in a condition except this, please use other mode. About the setup of the AK4691’s register, refer to datasheet of the AK4691. Applicable Evaluation Mode (1) Evaluation of A/D using DIT of AK4114. (1-1) Setting with External Slave Mode (2) Evaluation of D/A using DIR of AK4114. (2-1) Setting with External Slave Mode (3) Evaluation of A/D, D/A using PORT3 (DSP). (3-1) Setting with PLL Master Mode (3-2) Setting with PLL Slave Mode (3-3) Setting with External Slave Mode (4) Evaluation of Loop-back. (4-1) Setting with PLL Master Mode (4-2) Setting with PLL Slave Mode (4-3) Setting with External Slave Mode <Default> <KM089100> 2007/06 -3- [AKD4691-A] (1) Evaluation of A/D using DIT of AK4114. (1-1) Setting with External Slave Mode X1 (X’tal) and PORT2 (DIT) are used. Nothing should be connected to PORT1 (DIR) and PORT3 (DSP). JP23 (M/S) should be set to “Slave”. In addition, the register of AK4691 should be set to “EXT Slave Mode”. MCKI, BICK and LRCK are supplied from AK4114, and SDTO1 or SDTO2 of the AK4691 is output to the AK4114. The jumper pins should be set as the following. JP15 MCLK XTL DIR EXT JP22 4114_MCKI JP18 BICK_SEL DIR JP19 PHASE THR 4040 JP31 XTE INV JP21 LRCK_SEL DIR 4040 JP106 SDTO SDTO1 SDTO2 * When SDTO2 data is output to PORT2 (DIT), JP106 should be set to “SDTO2”. TDM Mode is not supported in this mode. (2) Evaluation of D/A using DIR of AK4114. (2-1) Setting with External Slave Mode PORT1 (DIR) is used. Nothing should be connected to PORT2 (DIT) and PORT3 (DSP). JP23 (M/S) should be set to “Slave”. In addition, the register of AK4691 should be set to “EXT Slave Mode”. The jumper pins should be set as the following. JP15 MCLK XTL DIR EXT JP22 4114_MCKI JP18 BICK_SEL DIR 4040 JP24 SDTI_SEL DIR JP19 PHASE THR INV JP21 LRCK_SEL DIR 4040 JP31 XTE ADC <KM089100> 2007/06 -4- [AKD4691-A] (3) Evaluation of A/D, D/A using PORT3 (DSP). PORT3 (DSP) is used. Nothing should be connected to PORT1 (DIR) and PORT2 (DIT). (3-1) Setting with PLL Master Mode The master clock is input from MCKI of PORT3 (DSP). An internal PLL circuit generates MCKO, BICK, and LRCK. JP23 (M/S) should be set to “Master”. In addition, the register of AK4691 should be set to “PLL Master Mode”. SDTI, SDTO, LRCK and BICK of PORT3 are respectively connected with SDTO, SDTI, LRCK and BICK of DSP. When MCKO is supplied to DSP, test pin (MCKO) should be directly connected to DSP. Loop-filter of PLL should be properly selected. Because resistor and capacitor values are 10kΩ and 4.7uF respectively on this board. 11.2896MHz, 12MHz, 12.288MHz 13.5MHz, 24MHz, 27MHz AK4691 DSP or μP MCKI 256fs/128fs/64fs/32fs MCKO 32fs, 64fs BICK BCLK 1fs LRCK MCLK LRCK SDTO1/2 SDTI1/2 SDTI SDTO Figure 2. PLL Master Mode The jumper pins should be set as the following. JP15 MCLK XTL DIR EXT JP19 PHASE THR INV JP21 LRCK_SEL DIR 4040 JP24 SDTI_SEL DIR JP31 XTE ADC JP106 SDTO SDTO1 SDTO2 * When SDTO2 data is output to PORT3 (DSP), JP106 should be set to “SDTO2”. <KM089100> 2007/06 -5- [AKD4691-A] (3-2) Setting with PLL Slave Mode A reference clock of PLL is selected among the input clocks supplied from PORT3 (DSP) to MCKI, BICK or LRCK pin. The required clock to the AK4691 is generated by an internal PLL circuit. JP23 (M/S) should be set to “Slave”. (3-2-1) PLL Reference Clock: MCKI pin The register of AK4691 should be set to “PLL Slave Mode” (Reference Clock: MCKI). BICK and LRCK inputs should be synchronized with MCKO output. But the phase between MCKO and LRCK dose not matter. Loop-filter of PLL should be properly selected. Because resistor and capacitor values are 10kΩ and 4.7uF respectively on this board. 11.2896MHz, 12MHz, 12.288MHz 13.5MHz, 24MHz, 27MHz AK4691 DSP or μP MCKI 256fs/128fs/64fs/32fs MCKO ≥ 32fs BICK BCLK 1fs LRCK MCLK LRCK SDTO1/2 SDTI1/2 SDTI SDTO Figure 3. PLL Slave Mode 1 (PLL Reference Clock: MCKI pin) The jumper pins should be set as the following. JP15 MCLK XTL DIR EXT JP19 PHASE THR INV JP21 LRCK_SEL DIR 4040 JP24 SDTI_SEL DIR JP31 XTE ADC JP106 SDTO SDTO1 SDTO2 * When SDTO2 data is output to PORT3 (DSP), JP106 should be set to “SDTO2”. <KM089100> 2007/06 -6- [AKD4691-A] (3-2-2) PLL Reference Clock: BICK or LRCK pin The register of AK4691 should be set to “PLL Slave Mode” (Reference Clock = BICK or LRCK). Loop-filter of PLL should be properly selected. Because resistor and capacitor values are 10kΩ and 4.7uF respectively on this board. AK4691 DSP or μP MCKO MCKI 32fs, 64fs BICK 1fs LRCK BCLK LRCK SDTO1/2 SDTI1/2 SDTI SDTO Figure 4. PLL Slave Mode 2(PLL Reference Clock: BICK or LRCK pin) The jumper pins should be set as the following. JP14 EXT JP15 MCLK XTL DIR EXT JP19 PHASE THR INV JP21 LRCK_SEL DIR 4040 JP24 SDTI_SEL DIR JP31 XTE ADC JP106 SDTO SDTO1 SDTO2 * When SDTO2 data is output to PORT3 (DSP), JP106 should be set to “SDTO2”. <KM089100> 2007/06 -7- [AKD4691-A] (3-3) Setting with External Slave Mode MCLK, BICK, LRCK, and SDTI are input from PORT3 (DSP). JP23 (M/S) should be set to “Slave”. In addition, the register of AK4691 should be set to “EXT Slave Mode”. AK4691 DSP or μP MCKO 256fs, 512fs or 1024fs MCKI MCLK ≥ 32fs BICK BCLK 1fs LRCK LRCK SDTO1/2 SDTI1/2 SDTI SDTO Figure 5. EXT Slave Mode The jumper pins should be set as the following. JP15 JP19 JP21 MCLK PHASE LRCK_SEL THR XTL DIR EXT INV DIR 4040 JP24 SDTI_SEL DIR JP31 XTE ADC JP106 SDTO SDTO1 SDTO2 * When SDTO2 data is output to PORT3 (DSP), JP106 should be set to “SDTO2”. (4) Evaluation of Loop-back. (4-1) Setting with PLL Master Mode Nothing should be connected to PORT1 (DIR), PORT2 (DIT) and PORT3 (DSP). JP23 (M/S) should be set to “Master”. In addition, the register of AK4691 should be set to “PLL Master Mode”. (4-1-1) In case of supplying MCLK from J11 (EXT) Loop-filter of PLL should be properly selected. Because resistor and capacitor values are 10kΩ and 4.7uF respectively on this board. The jumper pins should be set as the following. JP14 EXT JP15 MCLK XTL DIR EXT JP19 PHASE THR INV <KM089100> JP21 LRCK_SEL DIR 4040 JP24 SDTI_SEL DIR JP31 XTE ADC 2007/06 -8- [AKD4691-A] JP106 SDTO SDTO1 SDTO2 * When a termination (51Ω) is not used, JP14 (EXT) should be open. When SDTO2 data is looped back to SDTI, JP106 should be set to “SDTO2”. (4-1-2) In case of supplying MCKI from X2 (11.2896MHz) The jumper pins should be set as the following. JP15 MCLK JP19 PHASE XTL DIR EXT THR JP21 LRCK_SEL INV DIR JP31 XTE JP24 SDTI_SEL DIR 4040 ADC JP106 SDTO SDTO1 SDTO2 * When SDTO2 data is looped back to SDTI, JP106 should be set to “SDTO2”. (4-2) Setting with PLL Slave Mode BICK and LRCK are generated from MCKO of AK4691 on board divider. The generated BICK and LRCK is input to the AK4691. JP23 (M/S) should be set to “Slave”. In addition, the register of AK4691 should be set to “PLL Master Mode” (Reference Clock: MCKI). Nothing should be connected to PORT1 (DIR), PORT2 (DIT) and PORT3 (DSP). (4-2-1) In case of supplying MCLK from J11 (EXT) The jumper pins should be set as the following. JP14 EXT JP15 MCLK JP16 MKFS JP17 BGFS XTL DIR EXT 256fs512fs1024fs MCKO JP21 LRCK_SEL DIR 4040 JP24 SDTI_SEL DIR JP31 XTE 32fs JP108 MCKO ADC JP18 BICK_SEL 64fs DIR 4040 JP19 PHASE THR INV JP106 SDTO SDTO1 SDTO2 *When a termination (51Ω) is not used, JP14 (EXT) should be open. When SDTO2 data is looped back to SDTI, JP106 should be set to “SDTO2”. <KM089100> 2007/06 -9- [AKD4691-A] (4-2-2) In case of supplying MCKI from X2 (11.2896MHz) The jumper pins should be set as the following. JP15 MCLK JP16 MKFS JP17 BGFS XTL DIR EXT 256fs512fs1024fs MCKO JP21 LRCK_SEL DIR 4040 64fs JP31 XTE JP24 SDTI_SEL DIR 32fs JP18 BICK_SEL DIR JP108 MCKO JP19 PHASE THR 4040 INV JP106 SDTO ADC SDTO1 SDTO2 * When SDTO2 data is looped back to SDTI, JP106 should be set to “SDTO2”. (4-3) Setting with External Slave Mode JP23 (M/S) should be set to “Slave”. In addition, the register of AK4691 should be set to “EXT Slave Mode”. Nothing should be connected to PORT1 (DIR), PORT2 (DIT) and PORT3 (DSP). (4-3-1) In case of using clocks from AK4114 X1 (12.288MHz) is used. The jumper pins should be set as the following. JP15 MCLK JP18 BICK_SEL XTL DIR EXT JP22 4114_MCKI DIR JP24 SDTI_SEL DIR JP19 PHASE 4040 THR JP31 XTE INV JP21 LRCK_SEL DIR 4040 JP106 SDTO SDTO1 SDTO2 ADC * When SDTO2 data is looped back to SDTI, JP106 should be set to “SDTO2”. <KM089100> 2007/06 - 10 - [AKD4691-A] (4-3-2) In case of using the clock divider on the board ① In case of supplying MCLK from J11 (EXT) (e.g. MCLK=256fs, BICK=64fs) The jumper pins should be set as the following. JP14 EXT JP15 MCLK JP16 MKFS JP17 BGFS 32fs XTL DIR EXT 256fs512fs1024fs MCKO JP19 PHASE THR INV JP21 LRCK_SEL DIR JP31 XTE 64fs JP18 BICK_SEL DIR JP24 SDTI_SEL DIR 4040 4040 JP106 SDTO ADC SDTO1 SDTO2 * When a termination (51Ω) is not used, JP14 (EXT) should be open. When SDTO2 data is looped back to SDTI, JP106 should be set to “SDTO2”. ② In case of supplying MCKI from X2 (11.2896MHz) The jumper pins should be set as the following. JP15 MCLK JP16 MKFS JP17 BGFS XTL DIR EXT 256fs512fs1024fs MCKO JP21 LRCK_SEL JP24 SDTI_SEL 32fs JP31 XTE JP18 BICK_SEL 64fs DIR 4040 JP19 PHASE THR INV JP106 SDTO DIR ADC DIR 4040 SDTO1 SDTO2 * When SDTO2 data is looped back to SDTI, JP106 should be set to “SDTO2”. <KM089100> 2007/06 - 11 - [AKD4691-A] DIP Switch set up [S1] (SW DIP-6): Mode setting for AK4691 and AK4114. No. 1 2 3 4 5 6 Name DIF2 DIF1 DIF0 OCKS1 CAD0 MUTE ON (“H”) OFF (“L”) AK4114 Audio Format Setting See Table 2 AK4114 Master Clock Setting : See Table 3 AK4691Control Mode Setting : See Table 4 MUTE Normal Operation Default ON OFF OFF OFF OFF OFF Table 1. Mode Setting for AK4691 and AK4114 Mode DIF2 DIF1 DIF0 0 1 2 3 4 5 6 7 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 DAUX SDTO 24bit, Left justified 24bit, Left justified 24bit, Left justified 24bit, Left justified 24bit, Left justified 24bit, I2S 24bit, Left justified 24bit, I2S 16bit, Right justified 18bit, Right justified 20bit, Right justified 24bit, Right justified 24bit, Left justified 24bit, I2S 24bit, Left justified 24bit, I2S LRCK I/O H/L O H/L O H/L O H/L O H/L O L/H O H/L I L/H I BICK 64fs 64fs 64fs 64fs 64fs 64fs 64 -128fs 64 -128fs I/O O O O O O O I I Default Table 2. Setting for AK4114 Audio Interface Format OCKS1 0 1 MCKO1 256fs 512fs X’tal 256fs 512fs Default Table 3. Setting for AK4114 Master Clock <KM089100> 2007/06 - 12 - [AKD4691-A] Jumper pins set up Main Board [JP1] (GND): Analog ground and Digital ground OPEN: Separated. SHORT: Common. (The connector “DGND” can be open.) <Default> [JP2] (REG): Selection of REG OPEN: REG is not used. SHORT: REG is used. <Default> [JP3] (SVDD-SEL): SVDD of the AK4691 OPEN: SVDD is supplied from “SVDD” jack. SHORT: SVDD is supplied from the regulator (“SVDD” jack should be open). <Default> [JP4] (AVDD-SEL): AVDD of the AK4691 OPEN: AVDD is supplied from “AVDD” jack. SHORT: AVDD is supplied from the regulator (“AVDD” jack should be open). <Default> [JP5] (DVDD-SEL): DVDD of the AK4691 OPEN: DVDD is supplied from “DVDD” jack. SHORT: DVDD is supplied from “AVDD” (“DVDD” jack should be open). <Default> [JP6] (TVDD-SEL): TVDD of the AK4691 OPEN: TVDD is supplied from “TVDD” jack. SHORT: TVDD is supplied from “DVDD” (“TVDD” jack should be open). <Default> [JP7] (VCC-SEL): VCC of the AK4691 OPEN: VCC is supplied from “VCC” jack. SHORT: VCC is supplied from “TVDD” (“VCC” jack should be open). <Default> [JP8] (MVDD-SEL): MVDD of the AK4691 OPEN: MVDD is supplied from “MVDD” jack. SHORT: MVDD is supplied from “AVDD” (“MVDD” jack should be open). <Default> [JP16] (MKFS): MCLK Frequency 256fs: 256fs. <Default> 512fs: 512fs. 1024fs: 1024fs. MCKO: MCKO is used. [JP17] (BCFS): BICK Frequency 32fs: 32fs. 64fs: 64fs. <Default> [JP22] (4114-MCKI): AK4114 Clock Source OPEN: X’tal of AK4114 is used. <Default> SHORT: MCKO of the AK4691 is supplied to the AK4114. <KM089100> 2007/06 - 13 - [AKD4691-A] Sub Board [JP106] (SDTO-SEL): Selection of SDTO output SDTO1: SDTO1 is output. <Default> SDTO2: SDTO2 is output. [JP107] (TVDD2): TVDD2 of the AK4691 SHORT: TVDD2 is supplied from TVDD. <Default> [JP108] (MCKO): Selection of MCKO output OPEN: MCKO is not used. <Default> SHORT: MCKO is used. <KM089100> 2007/06 - 14 - [AKD4691-A] The function of the toggle SW *Upper-side is “H” and lower-side is “L”. [SW1] (PDN): Power down of AK4691. Keep “H” during normal operation. [SW2] (DIR): Power down of AK4114. Keep “H” during normal operation. Keep “L” when AK4114 is not used. Indication for LED [LED1] (ERF): Monitor INT0 pin of the AK4114. LED turns on when some error has occurred to AK4114. Serial Control The AKD4691 can be connected via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT4 (CTRL) with PC by 10 wire flat cable packed with the AKD4691. Table 4 shows switch and jumper settings for serial control. 3-WIRE Mode should be selected in Table4. PORT4 CSN Connect CCLK/SCL CDTI/SDA AKD4691 SDA(ACK) PC 10 wire flat cable 10pin Connector 10pin Header Figure 6. Connect of 10 wire flat cable Mode 3-WIRE I2C S1 JP25 JP109 CAD0 CTRL-SEL I2C OFF 3-WIRE Open I2C Short CAD=0 OFF CAD=1 ON Default Table 4. Control Mode Setting <KM089100> 2007/06 - 15 - [AKD4691-A] Analog Input/Output Circuits (1) Input Circuits C12 1u + R23 20k BEEP JP27 BEEP INTL1 EXTL1 6 J1 MIC1/BEEP 4 3 INTL1 EXTL1 L1-SEL JP28 INTR1 EXTR1 INTR1 EXTR1 R1-SEL JP29 INTL2 EXTL2 6 J2 MIC2 4 3 INTL2 EXTL2 L2-SEL JP30 INTR2 EXTR2 INTR2 EXTR2 R2-SEL 6 C13 1u LIN + J3 LIN/RIN R2 (open) + R1 (short) 4 3 R4 (open) R3 (short) RIN C14 1u Figure 7. INTL1/INTR1, INTL2/INTR2, EXTL1/EXTR1, EXTL2/EXTR2, BEEP, LIN/RIN Input Circuits (1-1) INTL1/INTR1 Input Circuit INTL1/INTR1 is input from J1. JP27 and JP28 should be set as the following. When the Mic Power is not used, JP101 and JP103 should be set to open. JP27 L1-SEL BEEP INTL1 EXTL1 JP28 R1-SEL JP101 INTL1 JP103 INTR1 INTR1 EXTR1 <KM089100> 2007/06 - 16 - [AKD4691-A] (1-2) INTL2/INTR2 Input Circuit INTL2/INTR2 is input from J2. JP29 and JP30 should be set as the following. When the Mic Power is not used, JP102 and JP104 should be set to open. JP29 L2-SEL JP30 R2-SEL INTL2 EXTL2 JP102 INTL2 JP104 INTR2 INTR2 EXTR2 (1-3) EXTL1/EXTR1 Input Circuit EXTL1/EXTR1 is input from J1. JP27 and JP28 should be set as the following. JP27 L1-SEL BEEP JP28 R1-SEL INTR1 EXTR1 INTL1 EXTL1 (1-4) EXTL2/EXTR2 Input Circuit EXTL2/EXTR2 is input from J2. JP29 and JP30 should be set as the following. JP29 L2-SEL INTL2 EXTL2 JP30 R2-SEL INTR2 EXTR2 (1-5) BEEP Input Circuit BEEP is input from J1. JP27 should be set as the following. JP27 L1-SEL BEEP INTL1 EXTL1 (1-6) LIN/RIN Input Circuit LIN/RIN is input from J3. <KM089100> 2007/06 - 17 - [AKD4691-A] (2) Output Circuits (2-1) LOUT/ROUT Output Circuit + 3.5ST JP10 LOUT-SEL LOUT C33 1u RCA 1 220 R13 R14 20k J5 LOUT 2 3 4 5 ROUT + 3.5ST JP11 ROUT-SEL C34 1u RCA 1 220 R15 R16 20k 6 J6 ROUT 2 3 4 5 J9 HP/LINE 4 3 Figure 8. LOUT/ROUT Output Circuit (2-1-1) In case that LOUT/ROUT is output from J5 and J6. JP11 ROUT_SEL JP10 LOUT_SEL RCA 3.5ST RCA 3.5ST (2-1-2) In case that LOUT/ROUT is output from J9. JP11 ROUT-SEL JP10 LOUT-SEL RCA 3.5ST RCA 3.5ST * J9 is shared with HPL/HPR. When LOUT/ROUT is output from J9, JP12 and JP13 should be set to “RCA”. <KM089100> 2007/06 - 18 - [AKD4691-A] (2-2) HPL/HPR Output Circuit 1 + RCA HPL C15 0.22u R17 (short) R18 16 JP12 HPL C35 220u J7 HPL 2 3 4 5 HP R22 10 6 J9 HP/LINE 4 3 + HP HPR C16 0.22u R19 (short) JP13 HPR C36 220u RCA 1 R20 16 R21 10 J8 HPR 2 3 4 5 Figure 9. HPL/HPR Output Circuit (2-2-1) In case that HPL/HPR is output from J7 and J8. JP13 HPR JP12 HPL RCA HP RCA HP (2-2-2) In case that HPL/HPR is output from J9. JP13 HPR JP12 HPL RCA HP RCA HP * J9 is shared with LOUT/ROUT. When HPL/HPR is output from J9, JP10 and JP11 should be set to “RCA”. <KM089100> 2007/06 - 19 - [AKD4691-A] (2-3) SPP/SPN Output Circuit 6 SPP J10 SPK 4 3 SPN JP26 SPK Figure 10. SPP/SPN Output Circuit SPP/SPN is output from J10. JP26 should be set as the following. JP26 SPK * AKEMD assumes no responsibility for the trouble when using the above circuit examples. <KM089100> 2007/06 - 20 - [AKD4691-A] Control Software Manual Set-up of evaluation board and control software 1. Set up the AKD4691 according to previous term. 2. Connect IBM-AT compatible PC with AKD4691 by 10-line type flat cable (packed with AKD4691). Take care of the direction of 10pin header. (Please install the driver in the CD-ROM when this control software is used on Windows 2000/XP. Please refer “Installation Manual of Control Software Driver by AKM device control software”. In case of Windows95/98/ME, this installation is not needed. This control software does not operate on Windows NT.) 3. Insert the CD-ROM labeled “AK4691 Evaluation Kit” into the CD-ROM drive. 4. Access the CD-ROM drive and double-click the icon of “akd4691.exe” to set up the control program. 5. Then please evaluate according to the follows. Operation flow Keep the following flow. 1. Set up the control program according to explanation above. 2. Click “Port Reset” button. 3. Click “Write default” button Explanation of each buttons 1. 2. 3. 4. 5. 6. 7. 8. 9. [Port Reset] : [Write default] : [All Write] : [All Read] : [Function1] : [Function2] : [Function3] : [Function4] : [Function5] : 10. 11. 12. 13. 14. [SAVE] : [OPEN] : [Write] : [Read] : [Filter] : Set up the USB interface board (AKDUSBIF-A) when using the board. Initialize the register of AK4691. Write all registers that is currently displayed. Read all registers that is currently displayed. Dialog to write data by keyboard operation. Dialog to write data by keyboard operation. The sequence of register setting can be set and executed. The sequence that is created on [Function3] can be assigned to buttons and executed. The register setting that is created by [SAVE] function on main window can be assigned to buttons and executed. Save the current register setting. Write the saved values to all register. Dialog to write data by mouse operation. Dialog to read data by mouse operation. Set Programmable Filter (FIL1, FIL3, EQ) of AK4691 easily. Indication of data Input data is indicated on the register map. Red letter indicates “H” or “1” and blue one indicates “L” or “0”. Blank is the part that is not defined in the datasheet. <KM089100> 2007/06 - 21 - [AKD4691-A] Explanation of each dialog 1. [Write Dialog]: Dialog to write data by mouse operation There are dialogs corresponding to each register. Click the [Write] button corresponding to each register to set up the dialog. If you check the check box, data becomes “H” or “1”. If not, “L” or “0”. If you want to write the input data to AK4691, click [OK] button. If not, click [Cancel] button. 2. [Function1 Dialog] : Dialog to write data by keyboard operation Address Box: Data Box: Input registers address in 2 figures of hexadecimal. Input registers data in 2 figures of hexadecimal. If you want to write the input data to AK4691, click [OK] button. If not, click [Cancel] button. 3. [Function2 Dialog] : Dialog to evaluate Volume There are dialogs corresponding to register of 0Ah, 0Bh, 0Ch and 0Dh. Address Box: Input registers address in 2 figures of hexadecimal. Start Data Box: Input starts data in 2 figures of hexadecimal. End Data Box: Input end data in 2 figures of hexadecimal. Interval Box: Data is written to AK4691 by this interval. Step Box: Data changes by this step. Mode Select Box: If you check this check box, data reaches end data, and returns to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00 If you do not check this check box, data reaches end data, but does not return to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 If you want to write the input data to AK4691, click [OK] button. If not, click [Cancel] button. <KM089100> 2007/06 - 22 - [AKD4691-A] 4. [SAVE] and [OPEN] 4-1. [SAVE] All of current register setting values displayed on the main window are saved to the file. The extension of file name is “akr”. <Operation flow> (1) Click [SAVE] Button. (2) Set the file name and click [SAVE] Button. The extension of file name is “akr”. 4-2. [OPEN] The register setting values saved by [SAVE] are written to the AK4691. The file type is the same as [SAVE]. <Operation flow> (1) Click [OPEN] Button. (2) Select the file (*.akr) and Click [OPEN] Button. <KM089100> 2007/06 - 23 - [AKD4691-A] 5. [Function3 Dialog] The sequence of register setting can be set and executed. (1) Click [F3] Button. (2) Set the control sequence. Set the address, Data and Interval time. Set “-1” to the address of the step where the sequence should be paused. (3) Click [START] button. Then this sequence is executed. The sequence is paused at the step of Interval="-1". Click [START] button, the sequence restarts from the paused step. This sequence can be saved and opened by [SAVE] and [OPEN] button on the Function3 window. The extension of file name is “aks”. Figure 11. [F3] Window <KM089100> 2007/06 - 24 - [AKD4691-A] 6. [Function4 Dialog] The sequence file (*.aks) saved by [Function3] can be listed up to 10 files, assigned to buttons and then executed. When [F4] button is clicked, the window as shown in Figure 12 opens. Figure 12. [F4] window <KM089100> 2007/06 - 25 - [AKD4691-A] 6-1. [OPEN] buttons on left side and [START] buttons (1) Click [OPEN] button and select the sequence file (*.aks) saved by [Function3]. The sequence file name is displayed as shown in Figure 13. ( In case that the selected sequence file name is “DAC_Stereo_ON.aks”) Figure 13. [F4] window (2) (2) Click [START] button, then the sequence is executed. 6-2. [SAVE] and [OPEN] buttons on right side [SAVE] : The name assign of sequence file displayed on [Function4] window can be saved to the file. The file name is “*.ak4”. [OPEN] : The name assign of sequence file(*.ak4) saved by [SAVE] is loaded. 6-3. Note (1) This function doesn't support the pause function of sequence function. (2) All files used by [SAVE] and [OPEN] function on right side need to be in the same folder. (3) When the sequence is changed in [Function3], the sequence file (*.aks) should be loaded again in order to reflect the change. <KM089100> 2007/06 - 26 - [AKD4691-A] 7. [Function5 Dialog] The register setting file(*.akr) saved by [SAVE] function on main window can be listed up to 10 files, assigned to buttons and then executed. When [F5] button is clicked, the window as shown in Figure 14 opens. Figure 14. [F5] window 7-1. [OPEN] buttons on left side and [WRITE] button (1) Click [OPEN] button and select the register setting file (*.akr). The register setting file name is displayed as shown in Figure 15. (In case that the selected file name is “DAC_Output.akr”) (2) Click [WRITE] button, then the register setting is executed. <KM089100> 2007/06 - 27 - [AKD4691-A] Figure 15. [F5] window (2) 7-2. [SAVE] and [OPEN] buttons on right side [SAVE] : The name assign of register setting file displayed on [Function5] window can be saved to the file. The file name is “*.ak5”. [OPEN] : The name assign of register setting file(*.ak5) saved by [SAVE] is loaded. 7-3. Note (1) All files used by [SAVE] and [OPEN] function on right side need to be in the same folder. (2) When the register setting is changed by [SAVE] Button on the main window, the register setting file (*.akr) should be loaded again in order to reflect the change. <KM089100> 2007/06 - 28 - [AKD4691-A] 8. [Filter Dialog] This dialog can calculate of a coefficient of Digital Programmable Filter (FIL1, FIL3 and EQ), write to a register and check frequency response. Window as shown in Figure 16 opens when push a [Filter] button. Figure 16. [Filter] window 8-1. Setting of a parameter (1) Please set a parameter of each Filter. [Sampling Rate] Æ Input value of sampling frequency [unit: Hz] <Default: 48000> [FIL1A Cut Off Frequency] Æ Input value of cut off frequency of FIL1A [unit: Hz] <Default: 200> [FIL3A Cut Off Frequency] Æ Input value of cut off frequency of FIL3A [unit: Hz] <Default: 4000> [FIL3A GAIN] Æ Input value of gain of FIL3A (0~-10dB) [unit: dB] <Default: -6> [EQA Pole Frequency] Æ Input value of pole frequency of EQA [unit: Hz] <Default: 2000> [EQA Zero-point Frequency] Æ Input value of zero frequency of EQA [unit: Hz] <Default: 4000> [EQA GAIN] Æ Input value of gain of EQA (+12~0dB) [unit: dB] <Default: 6> [FIL1B Cut Off Frequency] Æ Input value of cut off frequency of FIL1B [unit: Hz] <Default: 200> [FIL3B Cut Off Frequency] Æ Input value of cut off frequency of FIL3B [unit: Hz] <Default: 4000> [FIL3B GAIN] Æ Input value of gain of FIL3B (0~-10dB) [unit: dB] <Default: -6> [EQB Pole Frequency] Æ Input value of pole frequency of EQB [unit: Hz] <Default: 2000> [EQB Zero-point Frequency] Æ Input value of zero frequency of EQB [unit: Hz] <Default: 4000> [EQB GAIN] Æ Input value of gain of EQB (+12~0dB) [unit: dB] <Default: 6> (2) Please set a filter type of FIL1 and FIL3. Select “LPF” or “HPF” from [Filter type] of FIL1A, FIL3A, FIL1B and FIL3B. (3) Please set ON/OFF of “FIL1A”, “FIL3A”, “EQA”, “FIL1B”, “FIL3B”, “EQB” with a check button. When checked it, the filter becomes ON. <KM089100> 2007/06 - 29 - [AKD4691-A] 8-2. A calculation of a register A register value is displayed when push a [Register Setting] button. When a value out of a setting range is set, error message is displayed, and, a calculation of register setting is not carried out. Figure 17. A register setting calculation result When it is as follows that a register value is updated. (1) When [Register Setting] button was pushed. (2) When [F Response] button was pushed. (3) When [UpDate] button on a frequency characteristic indication window was pushed. <KM089100> 2007/06 - 30 - [AKD4691-A] 8-3.Indication of a frequency characteristic A frequency characteristic is displayed after a [Frequency Response] button is pushed. A register value is also updated. After "Frequency Range" is changed and a [UpDate] button is pushed, indication of a frequency characteristic is updated. Figure 18. A frequency characteristic indication result When it is as follows that a register value is updated. (1) When [Register Setting] button was pushed. (2) When [F Response] button was pushed. (3) When [UpDate] button on a frequency characteristic indication window was pushed. <KM089100> 2007/06 - 31 - [AKD4691-A] Measurement Result [Measurement condition] ・ Measurement unit ・ MCKI ・ BICK ・ fs ・ Bit ・ Measurement Mode ・ Power Supply ・ Input Frequency ・ Measurement Frequency ・ Temperature : Audio Precision, System two Cascade : 256fs (12.288MHz) : 64fs : 48kHz : 16bit : EXT Slave Mode : AVDD=DVDD=MVDD=LVDD=SVDD=TVDD1=TVDD2=3.0V : 1kHz : 20 ~ 20kHz : Room [Measurement Results] 1. ADC1 Result ADC: LIN/RIN Æ ADC1, IVOL=0dB S/(N+D) (-1dBFS) DR (-60dBFS, A-Weighted) S/N (A-weighted) Lch Rch 89.8 94.5 94.6 90.2 94.5 94.6 Unit dB dB dB 2. ADC2 Result Lch Rch INTL2/INTR2 Æ ADC2, Pre-Amp Gain=+24dB, IVOL=+29.625dB S/(N+D) (-1dBFS) 87.5 86.5 DR IVOL=0dB, (-60dBFS, A-Weighted) 62.1 62.2 S/N (A-weighted) 62.1 62.2 Unit dB dB dB 3. DAC Result Unit Lch Rch DAC: DAC Æ LOUT/ROUT, IVOL=DVOL=LVOL=0dB, RL=10kΩ S/(N+D) (0dBFS) 86.2 86.1 dB DR (-60dBFS, A-Weighted) 89.5 89.6 dB S/N (A-weighted) 90.2 90.2 dB Headphone-Amp: DAC Æ HPL/HPR, IVOL=DVOL=0dB, RL=22.8Ω, HPG bit = “0” S/(N+D) (-3dBFS) 72.5 72.2 dB DR (-60dBFS, A-Weighted) 89.5 89.4 dB S/N (A-weighted) 90.3 90.3 dB Speaker-Amp: DAC Æ SPP/SPN, IVOL=DVOL=0dB, RL=8Ω S/(N+D) SPKG=+10.65dB, (-3dBFS) 61.3 dB S/N (A-Weighted) 89.7 dB <KM089100> 2007/06 - 32 - [AKD4691-A] [Plot Data] 1. ADC (LIN/RIN Æ ADC, IVOL=0dB) AKM AK4691 LIN/RIN => ADC THD+N vs. Input Level fs=48kHz, fin=1kHz -70 -75 -80 d B F S -85 -90 -95 -100 -120 -100 -80 -60 -40 -20 +0 dBr Figure 19. THD+N vs. Input Level AKM AK4691 LIN/RIN => ADC THD+N vs. Frequency fs=48kHz, -1dB Input -70 -75 -80 d B F S -85 -90 -95 -100 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 20. THD+N vs. Input Frequency <KM089100> 2007/06 - 33 - [AKD4691-A] AKM AK4691 LIN/RIN => ADC Linearity fs=48kHz, fin=1kHz +0 -20 -40 d B F S -60 -80 -100 -120 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 5k 10k 20k dBr Figure 21. Linearity AKM AK4691 LIN/RIN => ADC Frequency Response fs=48kHz, -1dB Input -0 -0.5 -1 d B F S -1.5 -2 -2.5 -3 20 50 100 200 500 1k 2k Hz Figure 22. Frequency Response <KM089100> 2007/06 - 34 - [AKD4691-A] AKM AK4691 LIN/RIN => ADC FFT fs=48kHz, fin=1kHz, -1dB Input +0 -20 -40 d B F S -60 -80 -100 -120 -140 20 50 100 200 500 1k 2k 5k 10k 20k 5k 10k 20k Hz Figure 23. FFT (1kHz, -1dBFS) AKM AK4691 LIN/RIN => ADC FFT fs=48kHz, fin=1kHz, -60dB Input +0 -20 -40 d B F S -60 -80 -100 -120 -140 20 50 100 200 500 1k 2k Hz Figure 24. FFT (1kHz, -60dBFS) <KM089100> 2007/06 - 35 - [AKD4691-A] AKM AK4691 LIN/RIN => ADC FFT fs=48kHz, No Signal +0 -20 -40 d B F S -60 -80 -100 -120 -140 20 50 100 200 500 1k 2k 5k 10k 20k 10k 20k Hz Figure 25. FFT (Noise Floor) AKM AK4691 LIN/RIN => ADC Crosstalk fs=48kHz, -1dB Input, Blue:Rch=>Lch, Red:Lch=>Rch -80 TTT TTTT T T -90 -100 d B -110 -120 -130 -140 20 50 100 200 500 1k 2k 5k Hz Figure 26. Crosstalk <KM089100> 2007/06 - 36 - [AKD4691-A] 2. ADC (INTL1/INTR1 Æ ADC, INTL2/INTR2 Æ ADC, Pre-Amp Gain=+24dB, IVOL=0dB) AKM AK4691 INTL1/R1 => ADC1, INTL2/R2 => ADC2 THD+N vs. Input Level fs=48kHz, fin=1kHz -70 -75 -80 d B F S -85 -90 -95 -100 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 10k 20k dBr Figure 27. THD+N vs. Input Level AKM AK4691 INTL1/R1 => ADC1, INTL2/R2 => ADC2 THD+N vs. Frequency fs=48kHz, -1dB Input -70 -75 -80 d B F S -85 -90 -95 -100 20 50 100 200 500 1k 2k 5k Hz Figure 28. THD+N vs. Input Frequency <KM089100> 2007/06 - 37 - [AKD4691-A] AKM AK4691 INTL1/R1 => ADC1, INTL2/R2 => ADC2 Linearity fs=48kHz, fin=1kHz +0 -20 -40 d B F S -60 -80 -100 -120 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 10k 20k dBr Figure 29. Linearity AKM AK4691 INTL1/R1 => ADC1, INTL2/R2 => ADC2 Frequency Response fs=48kHz, -1dB Input +0 -1 -2 -3 d B F S -4 -5 -6 -7 -8 20 50 100 200 500 1k 2k 5k Hz *Positive Input: C=1μF, Ri=100kΩ(Ext HPF: fc=1.6Hz); Negative Input: C=2.2μF, Rn=2.2kΩ(Ext HPF: fc=33Hz) Figure 30. Frequency Response <KM089100> 2007/06 - 38 - [AKD4691-A] AKM AK4691 INTL1/R1=>ADC1, INTL2/R2=>ADC2 FFT fs=48kHz, fin=1kHz, -1dB Input +0 -20 -40 d B F S -60 -80 -100 -120 -140 20 50 100 200 500 1k 2k 5k 10k 20k 5k 10k 20k Hz Figure 31. FFT (1kHz, -1dBFS) AKM AK4691 INTL1/R1=>ADC1, INTL2/R2=>ADC2 FFT fs=48kHz, fin=1kHz, -60dB Input +0 -20 -40 d B F S -60 -80 -100 -120 -140 20 50 100 200 500 1k 2k Hz Figure 32. FFT (1kHz, -60dBFS) <KM089100> 2007/06 - 39 - [AKD4691-A] AKM AK4691 INTL1/R1=>ADC1, INTL2/R2=>ADC2 FFT fs=48kHz, No Signal +0 -20 -40 -60 d B F S -80 -100 -120 -140 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 33. FFT (Noise Floor) AKM AK4691 INTL1/R1 => ADC1, INTL2/R2 => ADC2 Crosstalk fs=48kHz, -1dB Input, Blue:R1=>L1, Red:L1=>R1, Cyan:R2=>L2, Magenta:L2=>R2 -80 TTTTTTTTTTTTTTT T T T T -90 -100 d B -110 -120 -130 -140 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 34. Crosstalk <KM089100> 2007/06 - 40 - [AKD4691-A] 3. DAC (DAC Æ LOUT/ROUT) AKM AK4691 DAC=>LineOut THD+N vs. Input Level fs=48kHz, fin=1kHz -60 -65 -70 d B r -75 A -80 -85 -90 -120 -100 -80 -60 -40 -20 +0 dBFS Figure 35. THD+N vs. Input Level AKM AK4691 DAC=>LineOut THD+N vs. Input Frequency fs=48kHz, 0dBFS Input -60 -65 -70 d B r -75 A -80 -85 -90 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 36. THD+N vs. Input Frequency <KM089100> 2007/06 - 41 - [AKD4691-A] AKM AK4691 DAC=>LineOut Linearity fs=48kHz, fin=1kHz +0 -20 d B r -40 A -60 -80 -100 -120 -100 -80 -60 -40 -20 +0 dBFS Figure 37. Linearity AKM AK4691 DAC=>LineOut Fequency Response fs=48kHz, 0dBFS Input +1 +0.5 -0 d B r -0.5 A -1 -1.5 -2 20 50 100 200 500 1k 2k 5k 10k 20k Hz *Line Out: C=1μF, Rseries=220Ω, RL=20kΩ(Ext HPF: fc=7.9Hz) Figure 38. Frequency Response <KM089100> 2007/06 - 42 - [AKD4691-A] AKM AK4691 DAC=>LineOut FFT fs=48kHz, fin=1kHz, 0dBFS Input +0 -20 -40 d B r A -60 -80 -100 -120 -140 20 50 100 200 500 1k 2k 5k 10k 20k 5k 10k 20k Hz Figure 39. FFT (1kHz, 0dBFS) AKM AK4691 DAC=>LineOut FFT fs=48kHz, fin=1kHz, -60dBFS Input +0 -20 -40 d B r A -60 -80 -100 -120 -140 20 50 100 200 500 1k 2k Hz Figure 40. FFT (1kHz, -60dBFS) <KM089100> 2007/06 - 43 - [AKD4691-A] AKM AK4691 DAC=>LineOut FFT fs=48kHz, No Signal +0 -20 -40 d B r A -60 -80 -100 -120 -140 20 50 100 200 500 1k 2k 5k 10k 20k 5k 10k 20k Hz Figure 41. FFT (Noise Floor) AKM AK4691 DAC=>LineOut CrossTalk fs=48kHz, Blue:Rch=>Lch, Red:Lch=>Rch -70 T TTTTT T -80 -90 d B -100 -110 -120 20 50 100 200 500 1k 2k Hz Figure 42. Crosstalk <KM089100> 2007/06 - 44 - [AKD4691-A] 4. Headphone (DAC Æ HPL/HPR) AKM AK4691 DAC=>HP THD+N vs. Input Level fs=48kHz, fin=1kHz -60 -65 -70 d B r -75 A -80 -85 -90 -120 -100 -80 -60 -40 -20 +0 dBFS Figure 43. THD+N vs. Input Level AKM AK4691 DAC=>HP THD+N vs. Input Frequency fs=48kHz, -3dBFS Input -40 -50 d B r -60 A -70 -80 -90 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 44. THD+N vs. Input Frequency (Filter: 20kHz AES17) <KM089100> 2007/06 - 45 - [AKD4691-A] AKM AK4691 DAC=>HP Linearity fs=48kHz, fin=1kHz +0 -20 d B r -40 A -60 -80 -100 -120 -100 -80 -60 -40 -20 +0 dBFS Figure 45. Linearity AKM AK4691 DAC=>HP Fequency Response fs=48kHz, -3dBFS Input -2 -3 -4 d B r A -5 -6 -7 -8 -9 -10 20 50 100 200 500 1k 2k 5k 10k 20k Hz *Headphone Out: C=220μF, Rseries=6.8Ω, RL=16Ω(Ext HPF: fc=31.7Hz) Figure 46. Frequency Response <KM089100> 2007/06 - 46 - [AKD4691-A] AKM AK4691 DAC=>HP FFT fs=48kHz, fin=1kHz, -3dBFS Input +0 -20 -40 d B r A -60 -80 -100 -120 -140 20 50 100 200 500 1k 2k 5k 10k 20k 5k 10k 20k Hz Figure 47. FFT (1kHz, -3dBFS) AKM AK4691 DAC=>HP FFT fs=48kHz, fin=1kHz, -60dBFS Input +0 -20 -40 d B r A -60 -80 -100 -120 -140 20 50 100 200 500 1k 2k Hz Figure 48. FFT (1kHz, -60dBFS) <KM089100> 2007/06 - 47 - [AKD4691-A] AKM AK4691 DAC=>HP FFT fs=48kHz, No Signal +0 -20 -40 d B r A -60 -80 -100 -120 -140 20 50 100 200 500 1k 2k 5k 10k 20k 5k 10k 20k Hz Figure 49. FFT (Noise Floor) AKM AK4691 DAC=>HP CrossTalk fs=48kHz, Blue:Rch=>Lch, Red:Lch=>Rch -50 -60 -70 d B -80 -90 -100 20 50 100 200 500 1k 2k Hz Figure 50. Crosstalk <KM089100> 2007/06 - 48 - [AKD4691-A] 4. Speaker (DAC Æ SPP/SPN, SPKG=+10.65dB) AKM d B AK4691 DAC=>Speaker(SPKG=10.65dB) THD+N vs. Output Power fs=48kHz, fin=1kHz -10 600m -20 500m -30 400m -40 300m W -50 200m -60 100m -70 -40 -35 -30 -25 -20 -15 -10 -5 +0 0 dBFS Figure 51. THD+N vs. Output Power AKM AK4691 DAC=>Speaker(SPKG=10.65dB) THD+N vs. Input Frequency fs=48kHz, -3.75dBFS(Po=240mW) -50 -55 -60 d B r A -65 -70 -75 -80 -85 -90 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 52. THD+N vs. Input Frequency <KM089100> 2007/06 - 49 - [AKD4691-A] AKM AK4691 DAC=>Speaker(SPKG=10.65dB) Linearity fs=48kHz, fin=1kHz +0 -10 -20 -30 d B r -40 A -60 -50 -70 -80 -90 -100 -120 -100 -80 -60 -40 -20 +0 dBFS Figure 53. Linearity AKM AK4691 DAC=>Speaker(SPKG=10.65dB) Frequency Response fs=48kHz, -3.75dBFS Input -2.75 -3 -3.25 -3.5 d B r -3.75 A -4 -4.25 -4.5 -4.75 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 54. Frequency Response <KM089100> 2007/06 - 50 - [AKD4691-A] AKM AK4691 DAC=>Speaker(SPKG=10.65dB) FFT fs=48kHz, fin=1kHz, -3.75dBFS Input +0 -20 -40 d B r A -60 -80 -100 -120 -140 20 50 100 200 500 1k 2k 5k 10k 20k 5k 10k 20k Hz Figure 55. FFT (1kHz, -3.75dBFS) AKM AK4691 DAC=>Speaker(SPKG=10.65dB) FFT fs=48kHz, No Signal +0 -20 -40 d B r A -60 -80 -100 -120 -140 20 50 100 200 500 1k 2k Hz Figure 56. FFT (Noise Floor) <KM089100> 2007/06 - 51 - [AKD4691-A] Revision History Date (YY/MM/DD) 07/06/14 Manual Revision KM089100 Board Revision 0 Reason Contents First edition IMPORTANT NOTICE z These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei EMD Corporation (AKEMD) or authorized distributors as to current status of the products. z AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. z Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKEMD. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any and all claims arising from the use of said product in the absence of such notification. <KM089100> 2007/06 - 52 - 1 R117 10k 1 + C128 0.1u I2CN C2 TVDD1 C3 NC D1 B9 A1 NC A9 MRF A8 VCOM C9 C8 AVDD D9 LIN D8 RIN E9 LRCK BEEP E8 BICK LOUT F9 TP126 MCKI 1 31 JP106 SDTO-SEL SDTO2 E2 R106 SDTO2 F2 F1 32 0 1 33 R107 C115 0.1u + 9 8 TP116 LOUT 7 TP115 ROUT C 6 TP114 LVDD 5 TP113 GND G2 MCKO ROUT F8 4 G1 DVDD LVCM G9 VSS2 MUTET H9 LVDD G8 TP112 HPL 3 1 34 TP127 SDTO AK4691 C117 0.1u TP110 VCOM C116 2.2u C114 10u 1 SDTO1 10 TP117 RIN 1 E1 51 C118 1u 1 MCKI SDTO1 30 C TP118 LIN 1 VSS1 SDTI D2 11 1 NC TP109 MUTET H2 1 NC VSS4 C109 2.2u + 2 TP111 HPR C111 1u 1 B J9 J8 HPL H8 HPR J7 H7 C110 0.1u C112 2.2u C134 0.1u 1 C136 (open) 1 R110 (open) TP139 MCKO JP108 MCKO VSS3 SVDD C133 2.2u + H6 SPP J6 J5 SPN PDN H5 MUTE J4 CSN CDTI H4 J1 CCLK TVDD2 TVDD2 C113+ 0.1u 1 1 + H1 J3 C132 0.1u H3 51 C131 10u NC 36 B JP107 NC 1 TP129 51 BICK R109 C130 0.1u J2 1 35 C129 + 10u + TP128 51 LRCK R108 D 12 TP119 BEEP VCOC B8 PRELN1 B7 PRELN2 A7 PRERN1 PRERN2 A6 A5 B6 MVDD INTL1 MPWR B5 B4 EXTL1 B3 A4 INTL2 INTR1 EXTL2 B2 C135 4700p 1 TP125 SDTI R105 A3 INTR2 TP120 1 AVDD + C127 10u TP124 TVDD EXTR1 A2 C1 CN101 12pin C124 C123 C122 C121 2.2u 2.2u 2.2u 2.2u 1 C126 0.1u 1 JP101 INTL1 R101 1k 13 14 15 16 17 18 19 1u TP138 VCOC 1 29 B1 I2C 27 28 EXTR2 TP123 DVDD R118 47k 1 1u C101 C125 10u + 26 C102 E JP109 U100 1 JP102 INTL2 R102 1k 1u 25 + D 20 21 JP103 INTR1 R103 1k + TP122 1 GND C103 C104 1u + CN103 12pin + + JP104 INTR2 + 22 + R104 1k 1u E TP121 MVDD C105 C106 1u + 24 C107 1u + C108 1u + E D + CN102 12pin 23 C + B + A 1 TP131 TP132 TP133 TP134 TP130 CCLK CDTI MUTE PDN 1 1 1 1 CSN R111 R112 R113 R114 1 51 51 51 51 TP135 TP136 TP137 SPN SPP SVDD R115 51 48 47 46 45 44 43 42 41 40 39 CN104 12pin 38 A 37 A Title Size A3 Date: A B C D AKD4691-SUB-57BGA Document Number AK4691 Friday, April 13, 2007 Sheet E Rev 0 1 of 1 E 13 MVDD INTL1 14 EXTL1 15 16 17 EXTL2 INTL2 D 18 19 20 EXTR1 21 22 23 24 CN2 12pin INTR1 C INTR2 B EXTR2 A E E CN3 12pin D CN1 12pin 25 D 12 AVDD DVDD 26 11 27 10 28 9 29 8 30 7 31 6 32 5 33 4 34 3 35 2 36 1 BEEP TVDD LIN RIN SDTI LOUT C MCKI C ROUT LVDD SDTO HPL LRCK BICK B B HPR 48 47 46 45 44 43 42 41 40 39 CN4 12pin 38 A 37 A SVDD SPP SPN PDN MUTE CDTI CCLK CSN MCKO Title Size A3 Date: A B C D AKD4691-A Document Number AK4691 Monday, April 23, 2007 Sheet E Rev 0 1 of 1 A B 2 LVDD + 1 2 L1 (short) JP3 SVDD-SEL 1 T45-OR 2 + BEEP INTL1 EXTL1 4 1 1 T45-OR 2 + C25 47u 1 1 1 T45-OR 2 + 1 1 1 DVDD1 C10 47u T45-OR + 220 R15 AVDD 2 C26 47u 2 (short) L3 2 1 1 T45-OR 2 + C27 47u VCC1 1 JP5 DVDD-SEL R2-SEL INTR2 EXTR2 T45-OR 2 + D3V1 1 1 1 T45-OR + 2 DGND1 C28 47u C29 47u C35 220u R18 16 HP DVDD J3 LIN/RIN 4 R1 (short) R2 (open) C13 1u 6 3 R3 (short) R4 (open) 2 4 3 LIN C RIN C14 1u HP HPR TVDD C16 0.22u R19 (short) C36 220u JP13 HPR RCA 1 J8 HPR R20 16 R21 10 2 J9 HP/LINE 6 2 3 4 5 VCC B (short) L6 D 2 3 4 5 INTR2 EXTR2 (short) L5 R17 (short) JP12 HPL J7 HPL R22 10 JP30 JP7 VCC-SEL 1 1 C15 0.22u + L4 HPL INTL2 EXTL2 L2-SEL R9 10 (short) JP1 GND B 6 3 + 1 J2 MIC2 INTL2 EXTL2 1 MVDD JP6 TVDD-SEL TVDD1 RCA JP29 4 2 3 4 5 R16 20k R1-SEL 2 J6 ROUT INTR1 EXTR1 (short) L9 1 + C RCA JP28 JP8 MVDD-SEL MVDD1 JP11 ROUT-SEL C34 1u L2 E 2 3 4 5 R14 20k 3.5ST ROUT + AVDD1 1 D INTL1 EXTL1 C24 47u INTR1 EXTR1 J5 LOUT BEEP L1-SEL JP4 AVDD-SEL 1 220 R13 R23 20k JP27 6 3 SVDD 1 1 J1 MIC1/BEEP RCA + C12 1u C23 47u T45-BK SVDD1 JP10 LOUT-SEL C33 1u 1 C22 + 0.1u + AGND1 E 3.5ST OUT C21 0.1u C11 47u D LOUT 2 + 2 T45-RED IN GND E JP2 REG 1 1 C T1 TA48030F 1 5V1 L8 (short) SPP 4 SPN 6 3 J10 SPK JP26 SPK 2 D3V (short) 1 T45-BK A A Title Size A3 Date: A B C D Document Number AKD4691-A Rev Power Supply, I/O Monday, May 21, 2007 Sheet E 2 0 of 5 A B C D E 8 9 10 11 12 13 D3V E GND Vcc 7 1 2 3 4 5 6 1A 1Y 2A 2Y 3A 3Y 4Y 4A 5Y 5A 6Y 6A U5 74HCU04 14 C42 0.1u R5 1M X2 11.2896MHz1 2 C38 5p JP16 2 3 4 5 1 R24 51 EXT MCLK 1 2 3 4 5 6 14 Vcc 7 GND C39 0.1u JP14 EXT 13 12 11 10 9 8 1CLR 2CLR 1D 2D 1CK 2CK 1PR 2PR 1Q 2Q 1Q 2Q CLK 11 RST MKFS 16 EXT-MCKO 8 INV BGFS U6 74HC4040 DIR R8 10k D1 HSU119 1 LED1 ERF L SW1 PDN 1 2 3 4 5 6 1A 1Y 2A 2Y 3A 3Y 14 Vcc 4Y 4A 5Y 5A 6Y 6A R26 1k 8 9 10 11 12 13 4114-INT0 4114-PDN R25 10k C D2 HSU119 2 A C19 0.1u 3 4114-LRCK C JP19 PHASE JP21 LRCK-SEL 4040 fs D EXT-LRCK THR 4040 64fs 32fs A U3 74AC74 C40 0.1u Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 VD Q9 Q10 Q11 DGND Q12 9 7 6 5 3 2 4 13 12 14 15 1 JP18 BICK-SEL DIR JP17 10 A JP15 XTL DIR 256fs 512fs 1024fs MCKO K 4114-MCKO K D J11 EXT EXT-BICK 4114-BICK C43 0.1u 7 GND U7 74HC14 L 2 C44 0.1u 1 C37 5p 3 JP31 XTE EXT-MCLK K E H SW2 DIR PDNI B B A A Title Size Document Number AKD4691-A A3 Date: A B C D Monday, May 21, 2007 Rev CLOCK Sheet E 0 3 of 5 A B C D E D3V E PORT1 VCC 3 GND OUT 2 1 E L7 (short) 1 2 C45 0.1u TORX141 C46 0.1u R27 470 C54 10u + C55 0.1u ------OFF------ 1 IPS0 2 38 37 INT1 R VCOM AVDD 39 40 41 AVSS 42 RX0 43 NC 44 RX1 47 45 TEST1 S1 SW DIP-6 R28 18k D INT0 36 NC OCKS0 35 3 DIF0 OCKS1 34 4 TEST2 CM1 33 5 DIF1 CM0 32 6 NC PDN 31 4114-INT0 DIF2 DIF1 DIF0 OCKS1 CAD0 MUTE 1 2 3 4 5 6 L 1 2 3 4 5 6 RX2 H NC D RX3 12 11 10 9 8 7 48 U8 46 C56 0.47u CAD0 7 6 5 4 3 2 1 MUTEI 7 DIF2 XTI 30 8 IPS1 XTO 29 9 P/SN DAUX 28 C 4114-PDN C53 5p 1 AK4114 RP1 47k MCKO JP22 4114-MCKI X1 12.288MHz 2 C C52 5p 10 XTL0 MCKO2 27 11 XTL1 BICK 26 B B 4114-SDTO LRCK 25 4114-BICK R38 100k 24 MCKO1 23 22 DVSS DVDD 21 C50 10u C51 0.1u + VOUT 20 UOUT 19 COUT 18 DVSS BOUT 17 16 15 13 14 + C48 10u C49 0.1u TX1 SDTO TX0 VIN TVDD 12 DAUX R37 100k 4114-LRCK R39 100k 4114-MCKO PORT2 IN VCC 3 2 GND 1 A C47 0.1u A TOTX141 Title Size A3 Date: A B C D Document Number AKD4691-A Rev DIR/DIT Monday, May 21, 2007 Sheet E 0 4 of 5 A B C D E VCC D3V EXT-BICK A1 B1 21 EXT-LRCK 4 A2 B2 20 5 A3 B3 19 6 A4 B4 18 7 A5 B5 17 8 A6 B6 16 R29 10k R42 51 R43 51 7 6 5 4 3 2 1 PORT3 R45 51 MCLK BICK LRCK SDTI VCC 9 A7 B7 15 10 A8 B8 14 2 DIR OE 22 1 VCCA VCCB 24 VCCB 23 GND 13 BICK 7 6 5 4 3 2 1 RP3 47k Master R41 51 C57 0.1u JP23 M/S 11 GND 12 GND U10 C58 0.1u 3 74AVC8T245 EXT-MCKO DAUX C C59 0.1u JP24 ADC SDTI-SEL 4114-SDTO U11 DIR EXT-MCLK MUTEI CAD0 R30 10k PORT4 B 10 8 6 4 2 9 7 5 3 1 R31 10k CSN CCLK/SCI CDTI/SDA CDTO/SDA(ACK) I2C R32 10k R33 R34 R35 E LRCK RP2 47k DSP R44 51 D 2 GND 4 GND 6 8 10 SDTO 1 3 5 7 9 Slave E U9 3 JP25 CTRL-SEL 3-WIRE 470 470 470 R40 B1 21 A2 B2 20 A3 B3 19 6 A4 B4 18 7 A5 B5 17 8 A6 B6 16 9 A7 B7 15 10 A8 B8 14 2 DIR 1 VCCA 4 5 A1 11 GND 12 GND OE 22 VCCB 24 VCCB 23 GND 13 D MCKO SDTO C C60 0.1u 3 A1 B1 21 4 A2 B2 20 5 A3 B3 19 6 A4 B4 18 MCKI 7 A5 B5 17 SDTI 8 A6 B6 16 MUTE 9 A7 B7 15 CSN 10 A8 B8 14 CCLK 51 74AVC8T245 B PDN CTRL 2 DIR 1 VCCA C61 0.1u PDNI 11 GND 12 GND OE 22 VCCB 24 VCCB 23 GND 13 CDTI C62 0.1u 74AVC8T245 U12 A 1 3 5 9 11 13 1A 2A 3A 4A 5A 6A 14 Vcc 7 GND C63 0.1u 1Y 2Y 3Y 4Y 5Y 6Y 2 4 6 8 10 12 R36 1k A Title Size A3 74LVC07 A B Date: C D Document Number AKD4691-A Rev LOGIC Tuesday, May 29, 2007 Sheet E 0 5 of 5