xr XRK32510 3.3V PHASE-LOCK LOOP CLOCK DRIVER WITH 10 CLOCK OUTPUTS OCTOBER 2005 REV. 1.0.1 FEATURES GENERAL DESCRIPTION The XRK32510 is a high performance, low jitter, low skew clock driver. The XRK32510 uses phase-lock loop (PLL) tecnology to synthesize the CLK_IN signal into 10 output signals (QA), synchronized in both phase and frequency. XRK32510 features low skew, low jitter and 50% duty cycle making it a perfect fit in dual in line memory module (DIMM) board clocking, PC133 SDRAM designs and other server applications. The 10 outputs can be disabled using the Output Enable (OE) pin. By connecting the Feedback Output (FB_OUT) signal to the Feedback Input (FB_IN) signal, the propagation delay from CLK_IN to the 10 buffered Outputs is nearly zero. • Spread Spectrum Clock Compatible • Operating frequency range: 25MHz to 175MHz • Low noise • Low jitter internal PLL • No external RC filter components required • Meets or exceeds DPC133 registered DIMM specification 1.1 • Output Enable (OE) pin can be used to disable the CLCK_OUT pins • Operating supply of 3.3V VDD • Plastic 24 Pin TSSOP package FIGURE 1. BLOCK DIAGRAM OF THE XRK32510 FB_OUT QA0 QA1 QA2 QA3 CLK_IN 0 Ref QA4 PLL FB_IN 1 QA5 QA6 AVDD QA7 QA8 QA9 OE PRODUCT ORDERING INFORMATION PRODUCT NUMBER PACKAGE TYPE OPERATING TEMPERATURE RANGE XRK32510CG 24 Pin TSSOP 0°C to +70°C Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com XRK32510 3.3V PHASE-LOCK LOOP CLOCK DRIVER WITH 10 CLOCK OUTPUTS AGND VDD QA0 QA1 QA2 GND GND QA3 QA4 VDD OE FB_OUT 1 2 3 4 5 6 7 8 9 10 11 12 XRK32510 FIGURE 2. PIN OUT OF THE XRK32510 2 24 23 22 21 20 19 18 17 16 15 14 13 CLK_IN AVDD VDD QA9 QA8 GND GND QA7 QA6 QA5 VDD FB_IN xr REV. 1.0.1 xr XRK32510 3.3V PHASE-LOCK LOOP CLOCK DRIVER WITH 10 CLOCK OUTPUTS REV. 1.0.1 PIN DESCRIPTIONS PIN # PIN NAME TYPE PIN DESCRIPTION 1 AGND **** Analog Ground 2 10 14 VDD VDD VDD **** 3.3V Power Supply 11 OE INPUT 12 FB_OUT OUTPUT 13 FB_IN INPUT 3 4 5 8 9 15 16 17 20 21 QA0 QA1 QA2 QA3 QA4 QA5 QA6 QA7 QA8 QA9 OUTPUT(S) 22 VDD **** 3.3V Digital Power Supply 23 AVDD **** 3.3V Analog Supply: If this pin is connected to ground, the PLL is disabled and will be bypassed and the CLK_IN signal will be connected directly to the output buffers of the 10 QA pins. 24 CLK_IN INPUT Output Enable: "High" = Normal operation, Clock outputs (QA[0:9]) enabled "Low" = Clock outputs (QA[0:9]) disabled Feedback Output: When this pin is connected to FB_IN, the propagation delay from CLK_IN to any of the 10 QA pins will be nearly zero. Feedback Input Buffered Clock Outputs: These 10 outputs provide low-skew, low jitter, 50% duty cycle renditions of CLK_IN Reference Clock Input FUNCTIONAL OPERATION INPUTS OUTPUTS PLL OE AVDD QA[0:9] FB_OUT SOURCE CONDITION 0 3.3V 0 Driven PLL ON 1 3.3V Driven Driven PLL ON BUFFER MODE 0 0 0 Driven CLK_IN OFF 1 0 Driven Driven CLK_IN OFF 3 xr XRK32510 3.3V PHASE-LOCK LOOP CLOCK DRIVER WITH 10 CLOCK OUTPUTS REV. 1.0.1 ABSOLUTE MAXIMUM RATINGS Analog Supply Voltage (AVDD) AVDD < (VDD +0.7V) Supply Voltage (VDD) 4.3V Logic Inputs GND- 0.5V to VDD + 0.5V Ambient Operating Temperature Range 0°C to +70°C Storage Temperature Range -65°C to +150°C ELECTRICAL CHARACTERISTICS -OUTPUT TA = 0 - 70°C, VDD = AVDD = 3.3V +/- 10%, CL = 20 - 30pF, RL = 470Ω, (unless otherwise stated) SYMBOL PARAMETER RDSP Output Impedance RDSN Output Impedance VOH Output High Voltage VOL Output Low Voltage IOH Output High Current MIN 2.4 TYP MAX UNITS CONDITIONS 36 Ω VO = VDD/2 32 Ω VO = VDD/2 3.0 V IOH = -8mA 0.2 -33 -48 19 28 13 19 IOL = 8mA -13.6 -22 VOH = 2.4V mA VOH = 2.0V VOL = 0.8V IOL Output Low Current Tr Rise Time1 0.5 0.8 2.1 ns VOH = 2.0V, VOL = 0.8V Tf Fall Time1 0.5 0.9 2.7 ns VOL = 0.8V, VOH = 2.0V Dt Duty Cycle1 45 50 55 % VT = 1.5V, CL = 30pF 28.7 100 Tcyc-cyc Cycle to Cycle Jitter1 25 TjABS Absolute Jitter1 57 Tsk Skew1 29 Tpe Phase Error1 -150 Tpej Phase Error Jitter1 -50 DR1 Delay Input to Output1 mA 75 VOL =0.55V @66 - 100MHz, loaded outputs ps @133MHz, loaded outputs ps 10,000 cycles, CL = 30 pF 150 ps VT = 1.5V (Window) Output to Output 150 ps VT = VDD/2, CLK_IN to FB_IN 35 50 ps VT = VDD/2, CLK_IN to FB_IN, Delay Jitter 3.5 3.7 ns VT = 1.5V, PLL Disabled (AVDD = 0) NOTE: 1. Guaranteed by design, not 100% tested in production 4 xr XRK32510 3.3V PHASE-LOCK LOOP CLOCK DRIVER WITH 10 CLOCK OUTPUTS REV. 1.0.1 ELECTRICAL CHARACTERISTICS - INPUT AND SUPPLY TA = 0 - 70°C, VDD= AVDD = 3.3V +/- 10% (unless otherwise stated) SYMBOL PARAMETER MIN VIH Input High Voltage VIL Input Low Voltage IIH Input High Current IIL TYP MAX UNITS 2 VDD + 0.3 V GND 0.3 0.8 V 0.1 100 µA VIN = VDD Input Low Current 19 50 µA VIN = 0V IDD Operating Current 140 170 mA CL = 0pF, FIN = 66MHz CIN Input Capacitance 4 pF Logic Inputs CO Output Capacitance 8 pF Logic Outputs 5 CONDITIONS XRK32510 3.3V PHASE-LOCK LOOP CLOCK DRIVER WITH 10 CLOCK OUTPUTS FIGURE 3. PACKAGE OUTLINE DRAWING 6 xr REV. 1.0.1 xr XRK32510 3.3V PHASE-LOCK LOOP CLOCK DRIVER WITH 10 CLOCK OUTPUTS REV. 1.0.1 REVISIONS REV. # DATE DESCRIPTION OF CHANGES 1.0.0 9/23/05 Initial issue. 1.0.1 10/06/05 Product ordering information: Remove "F" product numbers and Lead Free column. NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2005 EXAR Corporation Datasheet October 2005. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. 7