HOLTEK HT45R36

HT45R36
C/R to F Type 8-Bit OTP MCU
Technical Document
· Tools Information
· FAQs
· Application Note
Features
· Operating voltage:
· Power Down and Wake-up function reduce power
fSYS=4MHz: 2.2V~5.5V
fSYS=8MHz: 3.3V~5.5V
consumption
· Up to 0.5ms instruction cycle with 8MHz system clock
· 25 bidirectional I/O lines
at VDD=5V
· Two external interrupt inputs shared with I/O lines
· All instructions executed in one or two machine cy-
· 8-bit programmable timer/event counter with over-
cles
· 14-bit table read instruction
flow interrupt and 7-stage prescaler
· External RC oscillation converter
· Four-level subroutine nesting
· On-chip crystal and RC oscillator
· Bit manipulation instruction
· Watchdog Timer
· 63 powerful instructions
· 16 capacitor/resistor sensor input
· Low voltage reset function
· 2048´14 program memory
· 44/52-pin QFP package
· 120´8 data memory RAM
General Description
wake-up functions, Watchdog Timer, enhance the versatility of these devices to suit a wide range of application possibilities such as industrial control, consumer
products, subsystem controllers, etc.
The HT45R36 is an 8-bit high performance, RISC architecture microcontroller device specifically designed for
cost-effective multiple I/O control product applications.
The advantages of low power consumption, I/O flexibility, timer functions, oscillator options, Power Down and
Rev. 1.00
1
September 28, 2006
HT45R36
Block Diagram
P A 0 /IN T 0
P A 1 /IN T 1
In te rru p t
C ir c u it
S T A C K 0
P ro g ra m
R O M
S T A C K 1
P ro g ra m
C o u n te r
T M R C
IN T C
M
T M R
U
M
M P
U
X
P A C
P A 0
P A 1
P A 2
P A 3
P O R T A
P A
M U X
In s tr u c tio n
D e c o d e r
P B C
P O R T B
S ta tu s
A L U
P O R T C
P C C
S h ifte r
O S C 2
O S
R E
V D
V D
V S
V S
S
D
P O R T D
M
T im e r A
D B
S
S C
T im e r B
C lo c k /4
/IN T 0
/IN T 1
/T M R
~ P A 7
R C
O S C
P D 0
P D
A C C
C 1
S y s te m
X
P C 0 ~ P C 7
P C
P D C
U
P B 0 ~ P B 7
P B
T im in g
G e n e ra to r
M
W D T
W D T P r e s c a le r
D a ta
M e m o ry
C lo c k
P A 2 /T M R
W D T S
In s tr u c tio n
R e g is te r
S y s te m
P r e s c a le r
X
U
S y s te m
S y s te m
X
C lo c k
C lo c k /4
R C O s c illa tio n O u tp u t
R C 1 ~ R C 1 6
R C O U T
A n a lo g
S w itc h
IN
R C
O s c illa tio n
R R E F
C R E F
Pin Assignment
4 0 3 9 3 8 3 7 3 6 3 5 3 4
R C 1
R C 1
R C 1
V S
V D
O S C
O S C
R E
P A 0 /IN T
P A 1 /IN T
P A 2 /T M
P A
P A
R E S
P A 0 /IN T 0
4 4 4 3 4 2 4 1
R C 1
V S
V D
O S C
O S C
P A 1 /IN T 1
P A 2 /T M R
P A 3
P A 4
D
S
2
2
1
D
R
S
S
4
5
6
3
4
2
3
4
5
H T 4 5 R 3 6
4 4 Q F P -B
6
7
8
9
1 0
1 1
1 2
1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2
3 3
3 2
3 1
3 0
2 9
2 8
2 7
2 6
2 5
2 4
2 3
R C
R C
R C
R C
R C
R C
R C
R C
R C
R C
R C
1 1
1 0
P A
P A
P A
P B
P B
P B
P B
V D D
P B
P B
P B
P B
P C
9
8
7
6
5
4
3
2
1
B
5
6
5 2 5 1 5 0 4 9 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0
1
7
0
1
2
3 8
3
3 7
4
3 6
5
3 5
H T 4 5 R 3 6
5 2 Q F P -A
3
7
8
5
9
6
1 0
7
1 1
0
3 9
2
6
4
2
1
1
0
1
P A 5
P A 6
P A 7
P B 0
P B 1
P B 2
P B 3
V D D B
P B 4
P B 5
P B 6
1 2
1 3
1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6
3 4
3 3
3 2
3 1
3 0
2 9
2 8
2 7
R C
R C
R C
R C
R C
R C
R C
R C
R C
R C
R C
R C
R C
1
2
3
4
5
6
7
8
9
1 3
1 2
1 1
1 0
R C
IN
R R
C R
P D
P C
P C
P C
P C
V S
P C
P C
P C
R C
IN
R R
C R
P C
V S
P C
P C
P C
P C
P B
2
E F
E F
0
7
6
5
4
S C
3
1
1
2
O U T
E F
E F
4
S C
3
0
2
O U T
7
Rev. 1.00
September 28, 2006
HT45R36
Pin Description
Pin Name
I/O
Options
Description
PA0/INT0
PA1/INT1
PA2/TMR
PA3~PA7
I/O
Pull-high*
Wake-up
Bidirectional 8-bit I/O port. Each pin can be configured as a wake-up input via configuration options. Software instructions determine if the pin is a CMOS output or
Schmitt trigger input. Pull-high resistors can be added to the whole port via a configuration option.
Pins PA0 and PA1 are pin-shared with external interrupt input pins INT0 and INT1,
respectively. Configuration options determine the interrupt enable/disable and the
interrupt low/high trigger type. Pins PA2 is pin-shared with the external timer input
pins TMR.
PB0~PB7
I/O
Pull-high
Bidirectional 8-bit input/output port. Software instructions determine if the pin is a
CMOS output or Schmitt trigger input. Pull-high resistors can be added to the
whole port via a configuration option.
PC0~PC7
I/O
Pull-high
Bidirectional 8-bit input/output port. Software instructions determine if the pin is a
CMOS output or Schmitt trigger input. Pull-high resistors can be added to the
whole port via a configuration option.
PD0
I/O
Pull-high
Bidirectional 1-bit input/output port. Software instructions determine if the pin is a
CMOS output or Schmitt trigger input. A pull-high resistor can be added via a configuration option.
RC1~RC16
I
¾
Capacitor or resistor connection pins
RCOUT
I
¾
Capacitor or resistor connection pin to RC OSC
IN
I
¾
Oscillation input pin
RREF
O
¾
Reference resistor connection pin
CREF
O
¾
Reference capacitor connection pin
RES
I
¾
Schmitt trigger reset input. Active low
VSS
¾
¾
Negative power supply, ground
VSSC
¾
¾
Negative power supply for PC, ground
VDD
¾
¾
Positive power supply
VDDB
¾
¾
Positive power supply PB
OSC1
OSC2
I
O
OSC1, OSC2 are connected to an RC network or Crystal determined by a configuCrystal or RC ration option, for the internal system clock. In the case of the RC oscillator, OSC2
can be used to monitor the system clock. Its frequency is 1/4 system clock.
Note: *All pull-high resistors are controlled by an option bit.
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V
Storage Temperature ............................-50°C to 125°C
Input Voltage..............................VSS-0.3V to VDD+0.3V
Operating Temperature...........................-40°C to 85°C
IOL Total ..............................................................300mA
IOH Total............................................................-200mA
Total Power Dissipation .....................................500mW
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Rev. 1.00
3
September 28, 2006
HT45R36
D.C. Characteristics
Symbol
VDD
IDD1
Parameter
Operating Voltage
Operating Current
(Crystal OSC, RC OSC)
IDD2
Operating Current
(Crystal OSC, RC OSC)
ISTB1
Standby Current (WDT Enabled)
Ta=25°C
Test Conditions
Min.
Typ.
Max.
Unit
fSYS=4MHz
2.2
¾
5.5
V
fSYS=8MHz
3.3
¾
5.5
V
¾
1
2
mA
¾
3
5
mA
¾
4
8
mA
¾
¾
5
mA
¾
¾
10
mA
¾
¾
1
mA
¾
¾
2
mA
Conditions
VDD
¾
3V
No load, fSYS=4MHz
5V
5V
No load, fSYS=8MHz
3V
No load, system HALT
5V
ISTB2
3V
Standby Current (WDT Disabled)
No load, system HALT
5V
VIL1
Input Low Voltage for I/O Ports, TMR,
¾
INT0 and INT1
¾
0
¾
0.3VDD
V
VIH1
Input High Voltage for I/O Ports, TMR,
INT0 and INT1
¾
¾
0.7VDD
¾
VDD
V
VIL2
Input Low Voltage (RES)
¾
¾
0
¾
0.4VDD
V
VIH2
Input High Voltage (RES)
¾
¾
0.9VDD
¾
VDD
V
VLVR
Low Voltage Reset
¾
LVR enabled
2.7
3.0
3.3
V
IOL1
PA, PB, PD0, RREF and CREF
Sink Current
3V
4
8
¾
mA
10
20
¾
mA
-2
-4
¾
mA
-5
-10
¾
mA
8
16
¾
mA
20
40
¾
mA
-4
-8
¾
mA
-10
-20
¾
mA
IOH1
IOL2
PA, PC, PD0, RREF and CREF
Source Current
VOL=0.1VDD
5V
3V
VOH=0.9VDD
5V
3V
PC Sink Current
VOL=0.1VDD
5V
IOH2
3V
PB Source Current
VOH=0.9VDD
5V
RPH
Rev. 1.00
3V
¾
20
60
100
kW
5V
¾
10
30
50
kW
Pull-high Resistance
4
September 28, 2006
HT45R36
A.C. Characteristics
Symbol
fSYS
fTIMER
tWDTOSC
Parameter
System Clock
(Crystal OSC, RC OSC)
Timer I/P Frequency
Ta=25°C
Test Conditions
Conditions
VDD
Min.
Typ.
Max.
Unit
¾
2.2V~5.5V
400
¾
4000
kHz
¾
3.3V~5.5V
400
¾
8000
kHz
¾
2.2V~5.5V
0
¾
4000
kHz
¾
3.3V~5.5V
0
¾
8000
kHz
3V
¾
45
90
180
ms
5V
¾
32
65
130
ms
11
23
46
ms
8
17
33
ms
¾
1024
¾
tSYS
1
¾
¾
ms
¾
1024
¾
tSYS
Watchdog Oscillator Period
3V
tWDT1
Watchdog Time-out Period
(WDT RC OSC)
5V
tWDT2
Watchdog Time-out Period
(System Clock/4)
¾
tRES
External Reset Low Pulse Width
¾
tSST
System Start-up Timer Period
¾
tINT
Interrupt Pulse Width
¾
¾
1
¾
¾
ms
tLVR
Low Voltage Reset Time
¾
¾
0.25
1
2
ms
Rev. 1.00
Without WDT prescaler
Without WDT prescaler
¾
Wake-up from HALT
5
September 28, 2006
HT45R36
Functional Description
Execution Flow
incremented by one. The program counter then points to
the memory word containing the next instruction code.
The system clock for the microcontroller is derived from
either a crystal or an RC oscillator. The system clock is
internally divided into four non-overlapping clocks. One
instruction cycle consists of four system clock cycles.
When executing a jump instruction, a conditional skip
execution, loading the PCL register, a subroutine call,
an initial reset, an internal interrupt, an external interrupt
or return from a subroutine, the PC manipulates the program transfer by loading the address corresponding to
each instruction.
Instruction fetching and execution are pipelined in such
a way that a fetch takes an instruction cycle while decoding and execution takes the next instruction cycle.
However, the pipelining scheme causes each instruction to effectively execute in a cycle. If an instruction
changes the program counter, two cycles are required to
complete the instruction.
Program Counter - PC
The conditional skip is activated by instructions. Once
the condition is met, the next instruction, fetched during
the current instruction execution, is discarded and a
dummy cycle replaces it to get the proper instruction.
Otherwise the program will proceed with the next instruction.
The program counter (PC) controls the sequence in
which the instructions stored in program ROM are executed and its contents specify full range of program
memory.
The lower byte of the program counter (PCL) is a readable and writable register (06H). Moving data into the
PCL performs a short jump. The destination must be
within the current Program Memory Page.
After accessing a program memory word to fetch an instruction code, the contents of the program counter are
When a control transfer takes place, an additional
dummy cycle is required.
S y s te m
C lo c k
O S C 2 (R C
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
o n ly )
P C
P C
P C + 1
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
P C + 2
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution Flow
Mode
Program Counter
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial Reset
0
0
0
0
0
0
0
0
0
0
0
External Interrupt 0
0
0
0
0
0
0
0
0
1
0
0
External Interrupt 1
0
0
0
0
0
0
0
1
0
0
0
Timer/Event Counter Overflow
0
0
0
0
0
0
0
1
1
0
0
External RC Oscillation Converter Interrupt
0
0
0
0
0
0
1
0
0
0
0
Skip
Program Counter+2
Loading PCL
*10
*9
*8
@7
@6
@5
@4
@3
@2
@1
@0
Jump, Call Branch
#10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return from Subroutine
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Program Counter
Note: *10~*0: Program Counter bits
S10~S0: Stack register bits
#10~#0: Instruction code bits
Rev. 1.00
@7~@0: PCL bits
6
September 28, 2006
HT45R36
· Location 010H
Program Memory - ROM
This location is reserved for the external RC oscillation converter interrupt service program. If an external
RC oscillation converter interrupt results from an external RC oscillation converter interrupt is activated,
and the interrupt is enabled and the stack is not full,
the program begins execution at this location.
The program memory is used to store the program instructions which are to be executed. It also contains
data, table, and interrupt entries, and is organized into
2048´14 bits, addressed by the program counter and table pointer.
Certain locations in the program memory are reserved
for special usage:
· Table location
Any location in the program memory can be used as a
look-up table. The instructions ²TABRDC [m]² (the
current page, 1 page=256 words) and ²TABRDL [m]²
transfer the contents of the lower-order byte to the
specified data memory, and the higher-order byte to
TBLH (08H). Only the destination of the lower-order
byte in the table is well-defined, the other bits of the table word are transferred to the lower portion of TBLH,
and the remaining 2 bits are read as ²0². The Table
Higher-order byte register (TBLH) is read only. The table pointer (TBLP) is a read/write register (07H),
which indicates the table location. Before accessing
the table, the location must be placed in TBLP. The
TBLH is read only and cannot be restored. If the main
routine and the ISR (Interrupt Service Routine) both
employ the table read instruction, the contents of the
TBLH in the main routine are likely to be changed by
the table read instruction used in the ISR. Errors may
therefore occur. In other words, using the table read
instruction in the main routine and also in the ISR
should be avoided. However, if the table read instruction has to be used in both the main routine and in the
ISR, the interrupt should be disabled prior to the table
read instruction execution. The interrupt should not be
re-enabled until the TBLH has been backed up. All table related instructions require two cycles to complete
the operation. These areas may function as normal
program memory depending upon the requirements.
· Location 000H
This area is reserved for program initialisation. After a
device reset, the program always begins execution at
location 000H.
· Location 004H
This location is reserved for the external interrupt 0
service program. If the INT0 input pin is activated, the
interrupt is enabled and the stack is not full, the program begins execution at this location.
· Location 008H
This location is reserved for the external interrupt 1
service program. If the INT1 input pin is activated, the
interrupt is enabled and the stack is not full, the program begins execution at this location.
· Location 00CH
This location is reserved for the Timer/Event Counter
interrupt service program. If a Timer interrupt results
from a Timer/Event Counter overflow, and the interrupt is enabled and the stack is not full, the program
begins execution at this location.
0 0 0 H
D e v ic e In itia liz a tio n P r o g r a m
0 0 4 H
E x te rn a l In te rru p t 0
0 0 8 H
E x te rn a l In te rru p t 1
0 0 C H
T im e r /E v e n t C o u n te r O v e r flo w
0 1 0 H E x te r n a l R C O s c illa tio n C o n v e r te r In te r r u p t
n 0 0 H
n F F H
L o o k - u p T a b le ( 2 5 6 w o r d s )
7 0 0 H
7 F F H
L o o k - u p T a b le ( 2 5 6 w o r d s )
P ro g ra m
M e m o ry
Stack Register - STACK
This is a special part of the memory which is used to save
the contents of the program counter only. The stack is
organised into 4-levels and is neither part of the data nor
part of the program space, and is neither readable nor
writable. The activated level is indexed by the stack
pointer (SP) and is neither readable nor writeable. At a
subroutine call or interrupt acknowledgment, the contents of the program counter are pushed onto the stack.
At the end of a subroutine or an interrupt routine, signaled
1 4 - B its
N o te : n ra n g e s fro m 0 to 7
Program Memory
Instruction
Table Location
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
P10
P9
P8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table Location
Note: *10~*0: Table location bits
P10~P8: Current program counter bits
@7~@0: Table pointer bits
Rev. 1.00
7
September 28, 2006
HT45R36
by a return instruction, RET or RETI, the program counter
is restored to its previous value from the stack. After a device reset, the SP will point to the top of the stack.
0 0 H
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledgment will be inhibited. When the stack
pointer is decremented, by RET or RETI, the interrupt
will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily.
In a similar case, if the stack is full and a ²CALL² is subsequently executed, stack overflow occurs and the first
entry will be lost as only the most recent 4 return addresses are stored.
In d ir e c t A d d r e s s in g R e g is te r 0
0 1 H
M P 0
0 2 H
In d ir e c t A d d r e s s in g R e g is te r 1
0 3 H
M P 1
0 4 H
B P
0 5 H
A C C
0 6 H
P C L
0 7 H
T B L P
0 8 H
T B L H
0 9 H
W D T S
0 A H
S T A T U S
0 B H
IN T C 0
0 C H
0 D H
T M R
Data Memory - RAM
0 E H
T M R C
The data memory has a capacity of 150´8 bits. The data
memory is divided into two functional groups: special
function registers and general purpose data memory
(120´8). Most are read/write, but some are read only.
The general purpose data memory, addressed from 28H
to 7FH at Bank 0 and from 40H to 5FH at Bank 1, is used
for data and control information under instruction commands.
1 0 H
0 F H
1 1 H
All of the data memory areas can handle arithmetic,
logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the
data memory can be set and reset by the ²SET [m].i²
and ²CLR [m].i² bit manipulation instructions. They are
also indirectly accessible through the memory pointer
registers (MP0;01H, MP1;02H).
1 2 H
P A
1 3 H
P A C
1 4 H
P B
1 5 H
P B C
1 6 H
P C
1 7 H
P C C
1 8 H
P D
1 9 H
P D C
1 A H
A S C R
1 B H
1 C H
1 D H
1 E H
IN T C 1
1 F H
Bank 1 must be addressed indirectly using the memory
pointer MP1 and the indirect addressing register IAR1.
Any direct addressing or any indirect addressing using
MP0 and IAR0 will always result in data from Bank 0 being accessed.
2 0 H
2 1 H
T M R A H
2 2 H
R C O C C R
2 3 H
T M R B H
T M R A L
2 4 H
T M R B L
2 5 H
R C O C R
Indirect Addressing Register
2 6 H
The method of indirect addressing allows data manipulation using memory pointers instead of the usual direct
memory addressing method where the actual memory
address is defined. Any action on the indirect addressing registers will result in corresponding read/write operations to the memory location specified by the
corresponding memory pointers. This device contains
two indirect addressing registers known as IAR0 and
IAR1 and two memory pointers MP0 and MP1. Note that
these indirect addressing registers are not physically
implemented and that reading the indirect addressing
registers indirectly will return a result of ²00H² and writing to the registers indirectly will result in no operation.
2 7 H
2 8 H
7 F H
4 0 H
5 F H
G e n e ra l P u rp o s e D a ta M e m o ry
(8 8 B y te s )
R A M
M a p p in g B a n k 0
: U n u s e d
R e a d a s "0 0 "
G e n e ra l P u rp o s e D a ta M e m o ry
(3 2 B y te s )
R A M
M a p p in g B a n k 1
When any operation to the relevant indirect addressing
registers is carried out, the actual address that the
microcontroller is directed to is the address specified by
the related memory pointer.
The two memory pointers, MP0 and MP1, are physically
implemented in the data memory and can be manipulated in the same way as normal registers providing a
convenient way with which to address and track data.
Rev. 1.00
S p e c ia l P u r p o s e
D a ta M e m o ry
Bit 7 of the memory pointers are not implemented. However, it must be noted that when the memory pointers in
this device is read, a value of ²1² will be read.
8
September 28, 2006
HT45R36
· Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
Bank Pointer - BP
· Logic operations (AND, OR, XOR, CPL)
When using instructions to access the general purpose
data memory in Bank 0 or Bank 1, it is necessary to ensure that the correct area is selected. The general purpose data memory is sub-divided into two banks, Bank 0
and Bank 1 for this device. Selecting the correct data
memory area is achieved by using the bank pointer. If
data in Bank 0 or Bank 1 is to be accessed, the BP must
be set to the values ²00H² or ²01H² respectively, however, it must be noted that data in Bank 1 can only be addressed indirectly using the MP1 memory pointer and
the IAR1 indirect addressing register.
· Rotation (RL, RR, RLC, RRC)
· Increment and Decrement (INC, DEC)
· Branch decision (SZ, SNZ, SIZ, SDZ ....)
The ALU not only saves the results of a data operation
but also changes the status register.
Status Register - STATUS
This 8-bit register (0AH) contains the zero flag (Z), carry
flag (C), auxiliary carry flag (AC), overflow flag (OV),
power down flag (PDF), and watchdog time-out flag
(TO). It also records the status information and controls
the operation sequence.
Any direct addressing or any indirect addressing using
MP0 and IAR0 will always result in data from Bank 0 being accessed. The data memory is initialized to Bank 0
after a reset, except for the WDT time-out reset in the
Power Down Mode, in which case, the data memory
bank remains unchanged.
With the exception of the TO and PDF flags, bits in the
status register can be altered by instructions like most
other registers. Any data written into the status register
will not change the TO or PDF flag. In addition operations related to the status register may give different results from those intended. The TO flag can be affected
only by a system power-up, a WDT time-out or executing the ²CLR WDT² or ²HALT² instruction.
It should be noted that the special function data memory
is not affected by the bank selection, which means that
the special function registers can be accessed from
within either Bank 0 or Bank 1.
The PDF flag can be affected only by executing a
²HALT² or ²CLR WDT² instruction or a system
power-up.
Accumulator
The accumulator is closely related to ALU operations. It
is also mapped to location ²05H² of the data memory
and can carry out immediate data operations. The data
movement between two data memory locations must
pass through the accumulator.
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
In addition, on entering the interrupt sequence or executing the subroutine call, the status register will not be
pushed onto the stack automatically. If the contents of
the status are important and if the subroutine can corrupt the status register, precautions must be taken to
save it properly.
Arithmetic and Logic Unit - ALU
This circuit performs 8-bit arithmetic and logic operations. The ALU provides the following functions:
Bit No.
Label
Function
0
C
C is set if the operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate
through carry instruction.
1
AC
AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
2
Z
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.
3
OV
OV is set if the operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
4
PDF
PDF is cleared by system power-up or executing the ²CLR WDT² instruction.
PDF is set by executing the ²HALT² instruction.
5
TO
TO is cleared by system power-up or executing the ²CLR WDT² or ²HALT² instruction.
TO is set by a WDT time-out.
6~7
¾
Unused bit, read as ²0²
Status (0AH) Register
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9
September 28, 2006
HT45R36
RCOCF bit is set, a subroutine call to location ²10H² will
occur. The related interrupt request flag, RCOCF, will be
reset and the EMI bit cleared to disable further interrupts.
Interrupt
The devices provides two external interrupts, one internal 8-bit timer/event counter interrupt and one external
RC oscillation converter interrupt. The interrupt control
register 0 (INTC0;0BH) and interrupt control register 1
(INTC1;1EH) both contain the interrupt control bits that
are used to set the enable/disable and interrupt request
flags.
During the execution of an interrupt subroutine, other interrupt acknowledgments are held until the ²RETI² instruction is executed or the EMI bit and the related
interrupt control bit are set to 1, if the stack is not full. To
return from the interrupt subroutine, a ²RET² or ²RETI²
instruction may be invoked. RETI will set the EMI bit to
enable an interrupt service, but RET will not.
Once an interrupt subroutine is serviced, all the other interrupts will be blocked, by clearing the EMI bit. This
scheme may prevent further interrupt nesting. Other interrupt requests may happen during this interval but only
the interrupt request flag is recorded. If a certain interrupt requires servicing within the service routine, the
EMI bit and the corresponding bit of the INTC0 and
INTC1 registers may be set to allow interrupt nesting.
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If immediate service is
desired, the stack must be prevented from becoming
full.
No.
All interrupts have a wake-up capability. As an interrupt
is serviced, a control transfer occurs by pushing the program counter onto the stack, followed by a branch to a
subroutine at a specified location in the program memory. Only the program counter is pushed onto the stack.
If the contents of the accumulator or status register are
altered by the interrupt service program, this may corrupt the desired control sequence, therefore their contents should be saved in advance.
Priority Vector
a
External Interrupt 0
1
04H
b
External Interrupt 1
2
08H
c
Timer/Event Counter Overflow
3
0CH
d
External RC Oscillation
Converter Interrupt
4
10H
Interrupt Priority
The Timer/Event Counter interrupt request flag, TF, external interrupt 1 request flag, EIF1, external interrupt 0
request flag, EIF0, enable Timer/Event Counter interrupt bit, ETI, enable external interrupt 1 bit, EEI1, enable
external interrupt 0 bit, EEI0, and enable master interrupt bit, EMI, form the interrupt control register 0,
INTC0, which is located at ²0BH² in the RAM.
External interrupts are triggered by an edge transition
on pins INT0 or INT1. A configuration option enables
these pins as interrupts and selects if they are active on
high to low or low to high transitions. If active their related interrupt request flag, EIF0; bit 4 in INTC0, and
EIF1; bit 5 in INTC0, will be set. After the interrupt is enabled, the stack is not full, and the external interrupt is
active, a subroutine call to location ²04H² or ²08H² will
occur. The interrupt request flags, EIF0 or EIF1, and the
EMI bit will all be cleared to disable other interrupts.
The external RC oscillation converter interrupt request
flag, RCOCF, enable external RC oscillation converter
interrupt bit, ERCOCI, form the interrupt control register
1 (INTC1) which is located at ²1EH² in the RAM.
EMI, EEI0, EEI1, ETI and ERCOCI are all used to control the enable/disable status of interrupts. These bits
prevent the requested interrupt from being serviced.
Once the interrupt request flags, TF, RCOCF, EIF1 and
EIF0, are all set, they remain in the INTC1 or INTC0 registers respectively until the interrupts are serviced or
cleared by a software instruction.
The internal Timer/Event Counter interrupt is initialised
by setting the Timer/Event Counter interrupt request
flag, TF; bit 6 in INTC0. A timer interrupt will be generated when the timer overflows. After the interrupt is enabled, and the stack is not full, and the TF bit is set, a
subroutine call to location ²0CH² will occur. The related
interrupt request flag, TF, is reset, and the EMI bit is
cleared to disable other interrupts.
It is recommended that a program does not use the
²CALL subroutine² within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to
be serviced immediately in some applications. If only
one stack is left and enabling the interrupt is not well
controlled, the original control sequence may be damaged once the ²CALL² is executed in the interrupt subroutine.
The external RC oscillation converter interrupt is initialized by setting the external RC oscillation converter interrupt request flag, RCOCF; bit 4 of INTC1. This is
caused by a Timer A or Timer B overflow. When the interrupt is enabled, and the stack is not full and the
Rev. 1.00
Interrupt Source
10
September 28, 2006
HT45R36
Bit No.
Label
0
EMI
Controls the master (global) interrupt (1= enabled; 0= disabled)
Function
1
EEI0
Controls the external interrupt 0 (1= enabled; 0= disabled)
2
EEI1
Controls the external interrupt 1 (1= enabled; 0= disabled)
3
ETI
Controls the Timer/Event Counter interrupt (1= enabled; 0= disabled)
4
EIF0
External interrupt 0 request flag (1= active; 0= inactive)
5
EIF1
External interrupt 1 request flag (1= active; 0= inactive)
6
TF
Internal Timer/Event Counter request flag (1= active; 0= inactive)
7
¾
Unused bit, read as ²0²
INTC0 (0BH) Register
Bit No.
Label
0
Function
ERCOCI Controls the external RC oscillation converter interrupt (1= enabled; 0= disabled)
¾
1~3, 5~7
4
Unused bit, read as ²0²
RCOCF External RC oscillation converter request flag (1= active; 0= inactive)
INTC1 (1EH) Register
also be connected between OSC1 and OSC2 to get a
frequency reference, but two external capacitors connected between OSC1, OSC2 and ground are required,
if the oscillator frequency is less than 1MHz.
Oscillator Configuration
There are two oscillator circuits in the microcontroller.
V
O S C 1
D D
O S C 1
4 7 0 p F
O S C 2
C r y s ta l O s c illa to r
fS Y S /4
N M O S O p e n D r a in
The WDT oscillator is a free running on-chip RC oscillator which requires no external components. Even if the
system enters the Power Down Mode, where the system clock is stopped, the WDT oscillator will continue to
operate with a period of approximately 65ms at 5V. The
WDT oscillator can be disabled by a configuration option
to conserve power.
O S C 2
R C
O s c illa to r
System Oscillator
Watchdog Timer - WDT
Both are designed for system clocks, namely the RC oscillator and the Crystal oscillator, the choice of which is
determined by a configuration option. When the device
enters the Power Down Mode, the system oscillator will
stop running and will ignore external signals to conserve
power.
The WDT clock can be sourced from its own dedicated
internal oscillator (WDT oscillator), or from the or instruction clock, which is the system clock divided by 4.
The choice is determined via a configuration option. The
WDT timer is designed to prevent a software malfunction or sequence from jumping to an unknown location
with unpredictable results. The Watchdog Timer can be
disabled by a configuration option. If the Watchdog
Timer is disabled, any executions related to the WDT result in no operation.
If an RC oscillator is used, an external resistor between
OSC1 and VDD is required to produce oscillation. The
resistance must range from 24kW to 1MW. The system
clock, divided by 4, is available on OSC2, which can be
used to synchronize external logic. The RC oscillator
provides the most cost effective solution, however, the
frequency of oscillation may vary with VDD, temperatures and the device itself due to process variations. It is,
therefore, not suitable for timing sensitive operations
where an accurate oscillator frequency is desired.
The WDT clock source is first divided by 256. If the internal WDT oscillator is used ,this gives a nominal time-out
period of approximately 17ms at 5V. This time-out period may vary with temperatures, VDD and process variations. By using the WDT prescaler, longer time-out
periods can be realised. Writing data to the WS2, WS1,
WS0 bits in the WDTS register, can give different
time-out periods. If WS2, WS1, and WS0 are all equal to
1, the division ratio will be 1:128, and the maximum
time-out period will be 2.1s at 5V. If the internal WDT os-
If the Crystal oscillator is used, a crystal across OSC1
and OSC2 is needed to provide the feedback and phase
shift required for the oscillator. No other external components are required. Instead of a crystal, a resonator can
Rev. 1.00
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September 28, 2006
HT45R36
Power Down Operation - HALT
cillator is disabled, the WDT clock may still come from
the instruction clock and operate in the same manner
except that in the Power Down state the WDT will stop
counting and lose its protecting purpose. In this situation
the logic can only be restarted by external logic. The
high nibble and bit 3 of the WDTS can be used for user
defined flags.
The Power Down mode is initialized by the ²HALT² instruction and results in the following...
· The system oscillator will be turned off but the WDT
oscillator keeps running, if the internal WDT oscillator
has been selected as the WDT source clock.
· The contents of the on chip RAM and registers remain
If the device operates in a noisy environment, using the
internal WDT oscillator is the recommended choice,
since the HALT instruction will stop the system clock.
WS2
WS1
WS0
Division Ratio
0
0
0
1:1
0
0
1
1:2
0
1
0
1:4
0
1
1
1:8
1
0
0
1:16
1
0
1
1:32
1
1
0
1:64
1
1
1
1:128
unchanged.
· The WDT and WDT prescaler will be cleared and will
resume counting, if the internal WDT oscillator has
been selected as the WDT source clock
· AlloftheI/Oportswillmaintaintheiroriginalstatus.
· The PDF flag is set and the TO flag is cleared.
The system can leave the Power Down mode by means
of an external reset, an interrupt, an external falling
edge signal on port A or a WDT overflow. An external reset causes a device initialisation and the WDT overflow
performs a ²warm reset². After the TO and PDF flags
are examined, the reason for chip reset can be determined. The PDF flag is cleared by a system power-up or
executing the ²CLR WDT² instruction and is set when
executing the ²HALT² instruction. The TO flag is set if a
WDT time-out occurs, and causes a wake-up that only
resets the program counter and SP; the other registers
maintain their their original status.
WDTS (09H) Register
The WDT overflow under normal operation will generate
a ²chip reset² and set the status bit ²TO². But in the
Power Down mode, the overflow will generate a ²warm
reset², where only the Program Counter and SP are reset to zero. To clear the contents of the WDT, including
the WDT prescaler, three methods can be used; an external reset (a low level to RES), a software instruction
and a ²HALT² instruction. The software instruction includes ²CLR WDT² instruction and the instruction pair ²CLR WDT1² and ²CLR WDT2². Of these two types of
instruction, only one can be active depending on the
configuration option - ²CLR WDT times selection op tion². If the ²CLR WDT² is selected, i.e. CLRWDT times
equal one, any execution of the ²CLR WDT² instruction
will clear the WDT. In the case that ²CLR WDT1² and
²CLR WDT2² are chosen, i.e. CLRWDT times equal
two, these two instructions must be executed to clear
the WDT; otherwise, the WDT may reset the chip as a
result of a time-out.
S y s te m
The port A and interrupt methods of wake-up can be
considered as a continuation of normal execution. Each
bit in port A can be independently selected by configuration options to wake-up the device. When awakened
from an I/O port stimulus, the program will resume execution at the next instruction. If it is awakened due to an
interrupt, two sequences may happen. If the related interrupt is disabled or the interrupt is enabled but the
stack is full, the program will resume execution at the
next instruction. If the interrupt is enabled and the stack
is not full, the regular interrupt response takes place. If
an interrupt request flag is set to ²1² before entering the
Power Down mode, the wake-up function of the related
interrupt will be disabled. Once a wake-up event occurs,
it takes 1024 tSYS (system clock periods) to resume normal operation. In other words, a dummy period will be inserted after wake-up. If the wake-up results from an
interrupt acknowledgment, the actual interrupt subrou-
C lo c k /4
W D T P r e s c a le r
O p tio n
S e le c t
8 - b it C o u n te r
W D T
O S C
7 - b it C o u n te r
8 -to -1 M U X
W S 0 ~ W S 2
W D T T im e - o u t
Watchdog Timer
Rev. 1.00
12
September 28, 2006
HT45R36
tine execution will be delayed by one or more cycles. If
the wake-up results in the next instruction execution,
this will be executed immediately after the dummy period is finished.
The functional unit device reset status are shown below.
Program Counter
000H
Interrupt
Disable
To minimise power consumption, all the I/O pins should
be carefully managed before entering the Power Down
mode.
Prescaler
Clear
WDT
Clear. After master reset,
WDT begins counting
Reset
Timer/Event Counter
Off
There are three ways in which a reset can occur:
Input/Output Ports
Input mode
· RES reset during normal operation
Stack Pointer
Points to the top of the stack
· RES reset during HALT
· WDT time-out reset during normal operation
V
A WDT time-out, when the device is in the Power Down
mode, is different from other device reset conditions, in
that it can perform a ²warm reset² that resets only the
Program Counter and the SP, leaving the other circuits
in their original state. Some registers remain unchanged
during other reset conditions. Most registers are reset to
their ²initial condition² when the reset conditions are
met. By examining the PDF and TO flags, the program
can distinguish between the different device reset types.
TO PDF
0 .0 1 m F *
1 0 0 k W
R E S
1 0 k W
0 .1 m F *
Reset Circuit
RESET Conditions
0
0
RES reset during power-up
u
u
RES reset during normal operation
0
1
RES wake-up HALT
1
u
WDT time-out during normal operation
1
1
WDT wake-up HALT
D D
Note:
²*² Make the length of the wiring, which is connected to the RES pin as short as possible, to
avoid noise interference.
V D D
R E S
tS
S T
S S T T im e - o u t
Note: ²u² means ²unchanged²
C h ip
To guarantee that the system oscillator is started and
stabilised, the SST or System Start-up Timer, provides
an extra-delay of 1024 system clock pulses when the
system is reset (power-up, WDT time-out or RES reset)
or when the system awakens from a Power Down state.
R e s e t
Reset Timing Chart
H A L T
W a rm
R e s e t
W D T
When a system reset occurs, the SST delay is added
during the reset period. Any wake-up from HALT will enable the SST delay.
R E S
An extra option load time delay is added during a system
reset (power-up, WDT time-out at normal mode or RES
reset).
O S C 1
C o ld
R e s e t
S S T
1 0 - b it R ip p le
C o u n te r
S y s te m
R e s e t
Reset Configuration
Rev. 1.00
13
September 28, 2006
HT45R36
The states of the registers is summarized in the table.
Reset
(Power-on)
WDT Time-out
(Normal Operation)
RES Reset
(Normal Operation)
RES Reset
(HALT)
WDT Time-out
(HALT)*
MP0
-xxx xxxx
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
MP1
-xxx xxxx
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
Register
BP
---- ---0
---- ---0
---- ---0
---- ---0
---- ---0
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
000H
000H
000H
000H
000H
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
--xx xxxx
--uu uuuu
--uu uuuu
--uu uuuu
--uu uuuu
WDTS
0000 0111
0000 0111
0000 0111
0000 0111
uuuu uuuu
STATUS
--00 xxxx
--1u uuuu
--uu uuuu
--01 uuuu
--11 uuuu
INTC0
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
TMR
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMRC
00-0 1000
00-0 1000
00-0 1000
00-0 1000
uu-u uuuu
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PB
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PBC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PCC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
---- ---1
---- ---1
---- ---1
---- ---1
---- ---u
ACC
Program
Counter
PD
PDC
---- ---1
---- ---1
---- ---1
---- ---1
---- ---u
ASCR
---1 1111
---1 1111
---1 1111
---1 1111
---u uuuu
INTC1
---0 ---0
---0 ---0
---0 ---0
---0 ---0
---u ---u
TMRAH
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMRAL
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
RCOCCR
0000 1---
0000 1---
0000 1---
0000 1---
uuuu u---
TMRBH
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMRBL
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
RCOCR
1xxx --00
1xxx --00
1xxx --00
1xxx --00
uuuu --uu
Note:
²*² means ²warm reset²
²u² means ²unchanged²
²x² means ²unknown²
Rev. 1.00
14
September 28, 2006
HT45R36
transient from low to high, or high to low if the bit is ²0², it
will start counting until the TMR pin returns to its original
level and resets the TON bit. The measured result will
remain in the Timer/Event Counter even if the activated
transient occurs again. In other words, only a single shot
measurement can be made. The TON bit must be set
again by software for further measurements to be made.
Note that, in this operating mode, the Timer/Event
Counter starts counting not according to the logic level
but according to the transient edges. In the case of
counter overflows, the counter is reloaded from the
Timer/Event Counter preload register and issues an interrupt request just like the other two modes.
Timer/Event Counter
An 8-bit timer/event counter, known as Timer/Event
Counter, is implemented in the microcontroller. The
Timer/Event Counter contains an 8-bit programmable
count-up counter whose clock may come from an external source or from the system clock. Using the external
clock input allows the user to count external events, measure time internals or pulse widths, or generate an accurate time base. Using the internal clock allows the user to
generate an accurate time base.
There are 2 registers related to the Timer/Event Counter, TMR (0DH) and TMRC (0EH). Two physical registers are mapped to TMR location; writing to TMR places
the start value be placed in the Timer/Event Counter
preload register while reading TMR retrieves the contents of the Timer/Event Counter. The TMRC is a
timer/event counter control register, which defines the
timer operating conditions.
To enable the counting operation, the Timer ON bit,
TON; bit 4 of TMRC, should be set to ²1². In the pulse
width measurement mode, the TON will be cleared automatically after the measurement cycle is completed.
But in the other two modes the RCOCON can only be reset by instructions. The overflow of the Timer/Event
Counter is one of the wake-up sources. No matter what
the operation mode is, writing a 0 to ETI can disable the
interrupt service.
The TM0, TM1 bits define the operating mode. The event
count mode is used to count external events, which
means the clock source comes from an external TMR
pin. The timer mode functions as a normal timer with the
clock source coming from the fINT clock. The pulse width
measurement mode can be used to measure the high or
low level duration of an external signal on the TMR pin.
The counting is based on the fINT clock source. In the
event counting or timer mode, once the timer/event counter starts counting, it will count from the current contents
in the Timer/Event Counter to FFH. Once overflow occurs, the counter is reloaded from the Timer/Event Counter preload register and generates an interrupt request
flag (TF; bit 5 of INTC0) at the same time.
In the case of a Timer/Event Counter OFF condition,
writing data to the Timer/Event Counter preload register
will also reload that data to the Timer/Event Counter. But
if the Timer/Event Counter is already running, data written to it will only be loaded into the Timer/Event Counter
preload register. The Timer/Event Counter will continue
to operate until an overflow occurs. When the
Timer/Event Counter is read, the clock will be blocked to
avoid errors. As clock blocking may results in a counting
error, this must be taken into consideration by the programmer. Bit0~Bit2 of the TMRC can be used to define
the pre-scaling stages of the internal clock sources of
Timer/Event Counter. The definitions are as shown.
In the pulse width measurement mode, with the TON
and bits equal to one, once the TMR has received a
Bit No.
Label
Function
0~2
TPSC0~TPSC2
To define the prescaler stages, TPSC2, TPSC1, TPSC0=
000: fINT=fSYS
001: fINT=fSYS/2
010: fINT=fSYS/4
011: fINT=fSYS/8
100: fINT=fSYS/16
101: fINT=fSYS/32
110: fINT=fSYS/64
111: fINT=fSYS/128
3
TE
To define the TMR active edge of the timer/event counter
(0=active on low to high; 1=active on high to low)
4
TON
5
¾
6
7
TM0
TM1
To enable or disable timer counting (0=disabled; 1=enabled)
Unused bit, read as ²0²
To define the operating mode, TM1, TM0=
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
TMRC (0EH) Register
Rev. 1.00
15
September 28, 2006
HT45R36
S y s te m
C lo c k
7 - S ta g e P r e s c a le r
f IN
8 -1 M U X
T P S C 2 ~ T P S C 0
D a ta B u s
T
T M 1
T M 0
T M R
8 - B it T im e r /E v e n t C o u n te r R e lo a d
P r e lo a d R e g is te r
T E
8 - B it T im e r /E v e n t
C o u n te r (T M R )
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
T M 1
T M 0
T O N
O v e r flo w
to In te rru p t
Timer/Event Counter
The RC oscillation converter is comprised of the
TMRAL, TMRAH, TMRBL, TMRBH registers when the
RCO bit, bit 1 of RCOCR register, is ²1². The RC oscillation converter Timer B clock source may come from an
external RC oscillator. The Timer A clock source comes
from the system clock or from the system clock/4, determined by the RCOCCR register.
External RC Oscillation Converter
An external RC oscillation mode is implemented in the
device. The RC oscillation converter contains two 16-bit
programmable count-up counters and the Timer A clock
source may come from the system clock or system
clock/4. The timer B clock source may come from the
external RC oscillator.
Bit No.
Label
Function
0~2
¾
Unused bit, read as ²0²
3
¾
Undefined bit, this bit can read/write
4
5
6
7
RCOCON To enable or disable external RC oscillation converter counting (0= disabled; 1= enabled)
To define the Timer A clock source, RCOM2, RCOM1, RCOM0=
000= System clock
001= System clock/4
RCOM0 010= Unused
RCOM1 011= Unused
RCOM2 100= Unused
101= Unused
110= Unused
111= Unused
RCOCCR (22H) Register
Bit No.
Label
Function
0
OVB
In the RC oscillation converter mode, this bit is used to define the timer/event counter interrupt,
which comes from Timer A overflow or Timer B overflow.
(0= Timer A overflow; 1= Timer B overflow)
1
RCO
Define RC oscillation converter mode.
(0= Disable RC oscillation converter mode; 1= Enable RC oscillation converter mode)
2~3
¾
4~7
RW
Unused bit, read as ²0²
4-bit read/write registers for user defined.
RCOCR (25H) Register
S y s te m
S y s te m
C lo c k
C lo c k /4
S 1
O V B = 0
S 2
T im e r A
E x te rn a l R C
O s c illa tio n C o n v e r te r In te r r u p t
R C O C O N
O V B = 1
T im e r B
R C
O S C
R e s e t R C O C O N
O u tp u t
External RC Oscillation Converter
Rev. 1.00
16
September 28, 2006
HT45R36
There are six registers related to the RC oscillation converter, i.e., TMRAH, TMRAL, RCOCCR, TMRBH,
TMRBL and RCOCR. The internal timer clock is the input to TMRAH and TMRAL, the external RC oscillation
is the input to TMRBH and TMRBL. The OVB bit, bit 0 of
RCOCR register, decides whether Timer A overflows or
Timer B overflows, then the RCOCF bit is set and an external RC oscillation converter interrupt occurs. When
the RC oscillation converter mode Timer A or Timer B
overflows, the RCOCON bit is reset to ²0² and stops
counting. Writing to TMRAH/TMRBH places the start
value in Timer A/Timer B while reading TMRAH/TMRBH
obtains the contents of Timer A/Timer B. Writing to
TMRAL/TMRBL only writes the data into a low byte
buffer. However writing to TMRAH/TMRBH will write the
data and the contents of the low byte buffer into the
Timer A/Timer B (16-bit) simultaneously. Timer A/Timer
B is changed by writing to TMRAH/TMRBH but writing to
TMRAL/TMRBL will keep the Timer A/Timer B unchanged.
R e a d i n g T M R A H / T M R B H w i l l a l so l a t ch t h e
TMRAL/TMRBL into the low byte buffer to avoid the
false timing problem. Reading TMRAL/TMRBL returns
the contents of the low byte buffer. In other word, the low
byte of Timer A/Timer B can not be read directly. It must
read the TMRAH/TMRBH first to ensure that the low
byte contents of Timer A/Timer B are latched into the
buffer.
The resistor and capacitor form an oscillation circuit and
input to TMRBH and TMRBL. The RCOM0, RCOM1
and RCOM2 bits of RCOCCR define the clock source of
Timer A. It is recommended that the clock source of
Timer A uses the system clock or the instruction clock.
If the RCOCON bit, bit 4 of RCOCCR, is set to ²1², Timer
A and Timer B will start counting until Timer A or Timer B
overflows, the timer/event counter will then generate an
interrupt request flag which is RCOCF; bit 4 of INTC1.
The Timer A and Timer B will stop counting and will reset
the RCOCON bit to ²0² at the same time. If the
RCOCON bit is ²1², TMRAH, TMRAL, TMRBH and
TMRBL cannot be read or written.
External RC oscillation converter mode example program - Timer A overflow:
clr RCOCCR
mov a, 00000010b
; Enable External RC oscillation mode and set Timer A overflow
mov RCOCR,a
clr intc1.4
; Clear External RC Oscillation Converter interrupt request flag
mov a, low (65536-1000)
; Give timer A initial value
mov tmral, a
; Timer A count 1000 time and then overflow
mov a, high (65536-1000)
mov tmrah, a
mov a, 00h
; Give timer B initial value
mov tmrbl, a
mov a, 00h
mov tmrbh, a
mov a, 00110000b
; Timer A clock source=fSYS/4 and timer on
mov RCOCCR, a
p10:
clr wdt
snz intc1.4
; Polling External RC Oscillation Converter interrupt request flag
jmp p10
clr intc1.4
; Clear External RC Oscillation Converter interrupt request flag
; Program continue
Rev. 1.00
17
September 28, 2006
HT45R36
Analog Switch
There are 16 analog switch lines in the microcontroller for RC1~RC16, and a corresponding Analog Switch control register, which is mapped to the data memory of ²1AH².
Bit No.
Label
0~4
ASON
5~7
¾
Function
Defines the analog switch for RC1~RC16 which is on. ASON=
00000b= Analog switch 1 on, other analog switch off
00001b= Analog switch 2 on, other analog switch off
00010b= Analog switch 3 on, other analog switch off
00011b= Analog switch 4 on, other analog switch off
00100b= Analog switch 5 on, other analog switch off
00101b= Analog switch 6 on, other analog switch off
00110b= Analog switch 7 on, other analog switch off
00111b= Analog switch 8 on, other analog switch off
01000b= Analog switch 9 on, other analog switch off
01001b= Analog switch 10 on, other analog switch off
01010b= Analog switch 11 on, other analog switch off
01011b= Analog switch 12 on, other analog switch off
01100b= Analog switch 13 on, other analog switch off
01101b= Analog switch 14 on, other analog switch off
01110b= Analog switch 15 on, other analog switch off
01111b= Analog switch 16 on, other analog switch off
1xxxxb= All analog switch off and RC OSC always off.
Unused bit, read as ²0²
ASCR (1AH) Register
A S O N
R C 1
T .G .1
R C 2
T .G .2
R C 3
T .G .3
R C 4
T .G .4
R C 5
T .G .5
R C 6
T .G .6
R C 7
T .G .7
R C 8
T .G .8
R C 9
T .G .9
R C 1 0
T .G .1 0
R C 1 1
T .G .1 1
R C 1 2
T .G .1 2
R C 1 3
T .G .1 3
R C 1 4
T .G .1 4
R C 1 5
T .G .1 5
R C 1 6
T .G .1 6
R C O U T
IN
R R E F
C R E F
T im e r B
Analog Switch
Rev. 1.00
18
September 28, 2006
HT45R36
configuration options have selected pull-high resistors,
otherwise they will be in a floating condition. Each bit of
these input/output latches can be set or cleared by ²SET
[m].i² and ²CLR [m].i² (m=12H, 14H, 16H or 18H) instructions.
Input/Output Ports
There are 25 bidirectional input/output lines in the
microcontroller, labeled from PA to PD, which are
mapped to data memory addresses,12H, 14H, 16H and
18H, respectively. All of these I/O ports can be used for
input and output operations. For input operation, these
ports are non-latching, that is, the inputs must be ready
at the T2 rising edge of the ²MOV A,[m]² instruction. For
output operation, all the data is latched and remains unchanged until the output latch is rewritten.
Some instructions first input data and then follow the
output operations. For example, ²SET [m].i², ²CLR
[m].i², ²CPL [m]², ²CPLA [m]² read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
Each I/O line has its own control register, known as
PAC, PBC, PCC, PDC, to control the input/output configuration. With this control register, the pin status as either a CMOS output or Schmitt trigger input, but can be
reconfigured dynamically, i.e. on-the-fly, under software
control. To function as an input, the corresponding bit in
the control register must write ²1². The input source also
depends on the control register. If the control register bit
is ²1², the input will read the pad state. If the control register bit is ²0², the contents of the latches will move to the
in t e rn a l bus . The l a t t e r i s pos s i b l e i n t h e
²read-modify-write² instruction.
Each line of port A has the capability of waking-up the device. The highest 7-bit of port D are not physically implemented; on reading them a ²0² is returned whereas writing
then results in a no-operation. See Application note.
There are 4 pull-high options available for PA, PB, PC
and PD individually. Once the pull-high option is selected, I/O lines have pull-high resistors. Otherwise, the
pull-high resistors are absent. It should be noted that a
non-pull-high I/O line operating in input mode will cause
a floating state.
The PA0, PA1 and PA2 are pin-shared with INT0, INT1
and TMR pins, respectively.
When setup as output the output types are CMOS.
These control registers are mapped to locations 13H,
15H, 17H and 19H.
It is recommended that unused or not bonded out I/O
lines should be set as output pins by software instruction
to avoid consuming power under input floating state.
After a device reset, the I/O ports will be initially all setup
as inputs, and will therefore be in a high state if the
V
D a ta B u s
W r ite C o n tr o l R e g is te r
C o n tr o l B it
P u ll- h ig h
Q
D
Q
C K
S
P A
P B
P C
P D
C h ip R e s e t
R e a d C o n tr o l R e g is te r
W r ite D a ta R e g is te r
D a ta B it
Q
D
C K
S
0 ~ P A 7
0 ~ P B 7
0 ~ P C 7
0
Q
M
R e a d D a ta R e g is te r
S y s te m W a k e -u p
( P A o n ly )
D D
U
X
O P 0 ~ O P 7
IN T 0 fo r P A 0 o n ly
IN T 1 fo r P A 1 o n ly
T M R fo r P A 2 o n ly
Input/Output Ports
Rev. 1.00
19
September 28, 2006
HT45R36
Low Voltage Reset - LVR
The relationship between VDD and VLVR is shown below.
The microcontroller provides low voltage reset circuit in
order to monitor the supply voltage of the device. If the
supply voltage of the device is within the range
0.9V~VLVR, such as when changing a battery, the LVR
will automatically reset the device internally.
V D D
5 .5 V
V
O P R
5 .5 V
V
The LVR includes the following specifications:
· The low voltage (0.9V~VLVR) has to remain in its origi-
2 .2 V
nal state for longer than tLVR. If the low voltage state
does not exceed tLVR, the LVR will ignore it and will not
perform a reset function.
0 .9 V
· The LVR uses an ²OR² function with the external RES
Note:
signal to perform a chip reset.
V
L V R
3 .0 V
VOPR is the voltage range for proper chip operation at 4MHz system clock.
D D
5 .5 V
V
L V R D e te c t V o lta g e
L V R
0 .9 V
0 V
R e s e t S ig n a l
N o r m a l O p e r a tio n
R e s e t
R e s e t
*1
*2
Low Voltage Reset
Note:
*1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system
clock pulses before starting the normal operation.
*2: Since low voltage has to be maintained its original state for longer than tLVR, therefore a tLVR delay enters
the reset mode.
Options
The following table shows all kinds of options in the microcontroller. All of the options must be defined to ensure proper
system functioning.
No.
Function
Description
1
Wake-up PA0~PA7 (bit option)
None wake-up or wake-up
2
Pull-high PA0~PA7 (port option)
None pull-high or pull-high
3
Pull-high PB0~PB7 (port option)
None pull-high or pull-high
4
Pull-high PC0~PC7 (port option)
None pull-high or pull-high
5
Pull-high PD0 (bit option)
None pull-high or pull-high
6
WDT clock source
WDTOSC or fSYS/4
7
WDT
Enable or disable
8
CLRWDT
1 or 2 instruction
9
LVR
Disable or enable
10
OSC: X¢tal mode or RC mode
X¢tal mode or RC mode
11
INT0 trigger edge
Disable, rising edge, falling edge or double edge
12
INT1 trigger edge
Disable, rising edge, falling edge or double edge
Rev. 1.00
20
September 28, 2006
HT45R36
Application Circuits
R to F Application Circuit
V
D D
0 .0 1 m F *
P B 0 ~ P B 7
P C 0 ~ P C 7
V D D
P A 0
P A 1
P A 2
P A 3
1 0 0 k W
R E S
0 .1 m F
1 0 k W
0 .1 m F *
L E D D is p la y
/IN T 0
/IN T 1
/T M R
~ P A 7
V
P D 0
V S S
s e n s o r
1
R
s e n s o r
2
R C 1
R
R C 2
O S C
C ir c u it
R
O S C
1 6
s e n s o r
R C 1 6
S e e R ig h t S id e
R
4 7 0 p F
O S C 1
O S C 2
D D
fS
Y S
/4
C 1
*R
R R E F
R C O U T
IN
O S C 1
*C
O S C 2
O S C 1
C 2
C R E F
R C S y s te m O s c illa to r
2 4 k W < R O S C < 1 M W
O S C 2
R 1
H T 4 5 R 3 6
O S C
C ry s ta l S y s te m
F o r th e v a lu e s ,
s e e ta b le b e lo w
O s c illa to r
C ir c u it
C to F Application Circuit 1
V
D D
0 .0 1 m F *
V D D
1 0 0 k W
0 .1 m F
R E S
1 0 k W
P B 0 ~ P B 7
P C 0 ~ P C 7
P A 0
P A 1
P A 2
P A 3
0 .1 m F *
L E D D is p la y
/IN T 0
/IN T 1
/T M R
~ P A 7
V
P D 0
V S S
R C 1
R C 2
O S C
C ir c u it
O S C 1
O S C 2
R C 1 6
S e e R ig h t S id e
C R E F
R C O U T
IN
R R E F
C
s e n s o r
1
C
s e n s o r
2
R
O S C
C
4 7 0 p F
s e n s o
r1 6
O S C 1
fS
C 1
*C
*R
Y S
/4
R 1
O S C 2
O S C 2
O S C
21
R C S y s te m O s c illa to r
2 4 k W < R O S C < 1 M W
O S C 1
C 2
H T 4 5 R 3 6
Rev. 1.00
D D
C ry s ta l S y s te m
F o r th e v a lu e s ,
s e e ta b le b e lo w
O s c illa to r
C ir c u it
September 28, 2006
HT45R36
C to F Application Circuit 2
V
D D
0 .0 1 m F *
V D D
1 0 0 k W
0 .1 m F
R E S
1 0 k W
P B 0 ~ P B 7
P C 0 ~ P C 7
P A
P A
P A
P A
0 /IN
1 /IN
2 /T
3 ~ P
L E D D is p la y
T 0
T 1
M R
A 7
P D 0
0 .1 m F *
V S S
C
s e n s o r
1
C
s e n s o r
2
R C 1
R C 2
O S C 1
O S C
C ir c u it
V
D D
R
O S C
4 7 0 p F
O S C 2
S e e R ig h t S id e
R C 1 6
R C O U T
IN
R R E F
C
s e n s o r
1 6
fS
C 1
*R
R 1
*C
Y S
/4
R C S y s te m O s c illa to r
2 4 k W < R O S C < 1 M W
O S C 2
O S C 1
C 2
C R E F
H T 4 5 R 3 6
O S C 1
O S C 2
C ry s ta l S y s te m
F o r th e v a lu e s ,
s e e ta b le b e lo w
O s c illa to r
O S C C ir c u it
The following table shows the C1, C2 and R1 values corresponding to the different crystal values. (For reference only)
Crystal or Resonator
C1, C2
R1
4MHz Crystal
10pF
12kW
8MHz Crystal
10pF
4.3kW
4MHz Resonator
10pF
10kW
8MHz Resonator
10pF
4.7kW
3.58MHz Crystal
10pF
12kW
3.58MHz Resonator
25pF
10kW
2MHz Crystal
25pF
15kW
2MHz Resonator
35pF
15kW
1MHz Crystal
68pF
15kW
480kHz Resonator
300pF
12kW
455kHz Resonator
300pF
12kW
429kHz Resonator
300pF
12kW
400kHz Resonator
300pF
12kW
The function of the resistor R1 is to ensure that the oscillator will switch off should low voltage conditions occur.
Such a low voltage, as mentioned here, is one which is less than the lowest value of the MCU operating voltage. Note however that if the LVR is enabled then R1 can be removed.
Note:
The resistance and capacitance for the reset circuit should be designed in such a way as to ensure that the
VDD is stable and remains within a valid operating voltage range before bringing RES high.
²*² Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise
interference.
The ²*R² resistance and ²*C² capacitance should be consideration for the frequency of RC OSC.
Rsensor1~Rsensor16 are the resistance sensors.
Csensor1~Csensor16 are the capacitance sensors.
Rev. 1.00
22
September 28, 2006
HT45R36
Instruction Set Summary
Description
Instruction
Cycle
Flag
Affected
Add data memory to ACC
Add ACC to data memory
Add immediate data to ACC
Add data memory to ACC with carry
Add ACC to data memory with carry
Subtract immediate data from ACC
Subtract data memory from ACC
Subtract data memory from ACC with result in data memory
Subtract data memory from ACC with carry
Subtract data memory from ACC with carry and result in data memory
Decimal adjust ACC for addition with result in data memory
1
1(1)
1
1
1(1)
1
1
1(1)
1
1(1)
1(1)
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
C
1
1
1
1(1)
1(1)
1(1)
1
1
1
1(1)
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Increment data memory with result in ACC
Increment data memory
Decrement data memory with result in ACC
Decrement data memory
1
1(1)
1
1(1)
Z
Z
Z
Z
Rotate data memory right with result in ACC
Rotate data memory right
Rotate data memory right through carry with result in ACC
Rotate data memory right through carry
Rotate data memory left with result in ACC
Rotate data memory left
Rotate data memory left through carry with result in ACC
Rotate data memory left through carry
1
1(1)
1
1(1)
1
1(1)
1
1(1)
None
None
C
C
None
None
C
C
Move data memory to ACC
Move ACC to data memory
Move immediate data to ACC
1
1(1)
1
None
None
None
Clear bit of data memory
Set bit of data memory
1(1)
1(1)
None
None
Mnemonic
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
AND data memory to ACC
OR data memory to ACC
Exclusive-OR data memory to ACC
AND ACC to data memory
OR ACC to data memory
Exclusive-OR ACC to data memory
AND immediate data to ACC
OR immediate data to ACC
Exclusive-OR immediate data to ACC
Complement data memory
Complement data memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Rev. 1.00
23
September 28, 2006
HT45R36
Instruction
Cycle
Flag
Affected
Jump unconditionally
Skip if data memory is zero
Skip if data memory is zero with data movement to ACC
Skip if bit i of data memory is zero
Skip if bit i of data memory is not zero
Skip if increment data memory is zero
Skip if decrement data memory is zero
Skip if increment data memory is zero with result in ACC
Skip if decrement data memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1(2)
1(2)
1(2)
1(2)
1(3)
1(3)
1(2)
1(2)
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read ROM code (current page) to data memory and TBLH
Read ROM code (last page) to data memory and TBLH
2(1)
2(1)
None
None
No operation
Clear data memory
Set data memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of data memory
Swap nibbles of data memory with result in ACC
Enter Power Down Mode
1
1(1)
1(1)
1
1
1
1(1)
1
1
None
None
None
TO,PDF
TO(4),PDF(4)
TO(4),PDF(4)
None
None
TO,PDF
Mnemonic
Description
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note:
x: Immediate data
m: Data memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Ö: Flag is affected
-: Flag is not affected
(1)
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle
(four system clocks).
(2)
: If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more
cycle (four system clocks). Otherwise the original instruction cycle is unchanged.
(3) (1)
:
(4)
Rev. 1.00
and (2)
: The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the
²CLR WDT1² or ²CLR WDT2² instruction, the TO and PDF are cleared.
Otherwise the TO and PDF flags remain unchanged.
24
September 28, 2006
HT45R36
Instruction Definition
ADC A,[m]
Add data memory and carry to the accumulator
Description
The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADCM A,[m]
Add the accumulator and carry to data memory
Description
The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADD A,[m]
Add data memory to the accumulator
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the accumulator.
Operation
ACC ¬ ACC+[m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADD A,x
Add immediate data to the accumulator
Description
The contents of the accumulator and the specified data are added, leaving the result in the
accumulator.
Operation
ACC ¬ ACC+x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADDM A,[m]
Add the accumulator to the data memory
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the data memory.
Operation
[m] ¬ ACC+[m]
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
25
September 28, 2006
HT45R36
AND A,[m]
Logical AND accumulator with data memory
Description
Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
AND A,x
Logical AND immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_AND operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
ANDM A,[m]
Logical AND data memory with the accumulator
Description
Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
CALL addr
Subroutine call
Description
The instruction unconditionally calls a subroutine located at the indicated address. The
program counter increments once to obtain the address of the next instruction, and pushes
this onto the stack. The indicated address is then loaded. Program execution continues
with the instruction at this address.
Operation
Stack ¬ Program Counter+1
Program Counter ¬ addr
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR [m]
Clear data memory
Description
The contents of the specified data memory are cleared to 0.
Operation
[m] ¬ 00H
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
26
September 28, 2006
HT45R36
CLR [m].i
Clear bit of data memory
Description
The bit i of the specified data memory is cleared to 0.
Operation
[m].i ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR WDT
Clear Watchdog Timer
Description
The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are
cleared.
Operation
WDT ¬ 00H
PDF and TO ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
0
0
¾
¾
¾
¾
CLR WDT1
Preclear Watchdog Timer
Description
Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation
WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO
PDF
OV
Z
AC
C
0*
0*
¾
¾
¾
¾
CLR WDT2
Preclear Watchdog Timer
Description
Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation
WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO
PDF
OV
Z
AC
C
0*
0*
¾
¾
¾
¾
CPL [m]
Complement data memory
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa.
Operation
[m] ¬ [m]
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
27
September 28, 2006
HT45R36
CPLA [m]
Complement data memory and place result in the accumulator
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa. The complemented result
is stored in the accumulator and the contents of the data memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
DAA [m]
Decimal-Adjust accumulator for addition
Description
The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal
carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a
carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored
in the data memory and only the carry flag (C) may be affected.
Operation
If ACC.3~ACC.0 >9 or AC=1
then [m].3~[m].0 ¬ (ACC.3~ACC.0)+6, AC1=AC
else [m].3~[m].0 ¬ (ACC.3~ACC.0), AC1=0
and
If ACC.7~ACC.4+AC1 >9 or C=1
then [m].7~[m].4 ¬ ACC.7~ACC.4+6+AC1,C=1
else [m].7~[m].4 ¬ ACC.7~ACC.4+AC1,C=C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
DEC [m]
Decrement data memory
Description
Data in the specified data memory is decremented by 1.
Operation
[m] ¬ [m]-1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
DECA [m]
Decrement data memory and place result in the accumulator
Description
Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]-1
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
28
September 28, 2006
HT45R36
HALT
Enter Power Down Mode
Description
This instruction stops program execution and turns off the system clock. The contents of
the RAM and registers are retained. The WDT and prescaler are cleared. The power down
bit (PDF) is set and the WDT time-out bit (TO) is cleared.
Operation
Program Counter ¬ Program Counter+1
PDF ¬ 1
TO ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
0
1
¾
¾
¾
¾
INC [m]
Increment data memory
Description
Data in the specified data memory is incremented by 1
Operation
[m] ¬ [m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
INCA [m]
Increment data memory and place result in the accumulator
Description
Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
JMP addr
Directly jump
Description
The program counter are replaced with the directly-specified address unconditionally, and
control is passed to this destination.
Operation
Program Counter ¬addr
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
MOV A,[m]
Move data memory to the accumulator
Description
The contents of the specified data memory are copied to the accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
29
September 28, 2006
HT45R36
MOV A,x
Move immediate data to the accumulator
Description
The 8-bit data specified by the code is loaded into the accumulator.
Operation
ACC ¬ x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
MOV [m],A
Move the accumulator to data memory
Description
The contents of the accumulator are copied to the specified data memory (one of the data
memories).
Operation
[m] ¬ACC
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
Program Counter ¬ Program Counter+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
OR A,[m]
Logical OR accumulator with data memory
Description
Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
OR A,x
Logical OR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_OR operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
ORM A,[m]
Logical OR data memory with the accumulator
Description
Data in the data memory (one of the data memories) and the accumulator perform a
bitwise logical_OR operation. The result is stored in the data memory.
Operation
[m] ¬ACC ²OR² [m]
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
30
September 28, 2006
HT45R36
RET
Return from subroutine
Description
The program counter is restored from the stack. This is a 2-cycle instruction.
Operation
Program Counter ¬ Stack
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RET A,x
Return and place immediate data in the accumulator
Description
The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data.
Operation
Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RETI
Return from interrupt
Description
The program counter is restored from the stack, and interrupts are enabled by setting the
EMI bit. EMI is the enable master (global) interrupt bit.
Operation
Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RL [m]
Rotate data memory left
Description
The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RLA [m]
Rotate data memory left and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the
rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ [m].7
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
31
September 28, 2006
HT45R36
RLC [m]
Rotate data memory left through carry
Description
The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
RLCA [m]
Rotate left through carry and place result in the accumulator
Description
Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the
carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored
in the accumulator but the contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
RR [m]
Rotate data memory right
Description
The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RRA [m]
Rotate right and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving
the rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i) ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RRC [m]
Rotate data memory right through carry
Description
The contents of the specified data memory and the carry flag are together rotated 1 bit
right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
32
September 28, 2006
HT45R36
RRCA [m]
Rotate right through carry and place result in the accumulator
Description
Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces
the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is
stored in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
SBC A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SBCM A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SDZ [m]
Skip if decrement data memory is 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. If the result is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, [m] ¬ ([m]-1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SDZA [m]
Decrement data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. The result is stored in the accumulator but the data memory remains
unchanged. If the result is 0, the following instruction, fetched during the current instruction
execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, ACC ¬ ([m]-1)
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
33
September 28, 2006
HT45R36
SET [m]
Set data memory
Description
Each bit of the specified data memory is set to 1.
Operation
[m] ¬ FFH
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SET [m]. i
Set bit of data memory
Description
Bit i of the specified data memory is set to 1.
Operation
[m].i ¬ 1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SIZ [m]
Skip if increment data memory is 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a
dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with
the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, [m] ¬ ([m]+1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SIZA [m]
Increment data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the next
instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper
instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, ACC ¬ ([m]+1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SNZ [m].i
Skip if bit i of the data memory is not 0
Description
If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data
memory is not 0, the following instruction, fetched during the current instruction execution,
is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i¹0
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
34
September 28, 2006
HT45R36
SUB A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the accumulator.
Operation
ACC ¬ ACC+[m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SUBM A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the data memory.
Operation
[m] ¬ ACC+[m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SUB A,x
Subtract immediate data from the accumulator
Description
The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+x+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SWAP [m]
Swap nibbles within the data memory
Description
The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged.
Operation
[m].3~[m].0 « [m].7~[m].4
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SWAPA [m]
Swap data memory and place result in the accumulator
Description
The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.3~ACC.0 ¬ [m].7~[m].4
ACC.7~ACC.4 ¬ [m].3~[m].0
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
35
September 28, 2006
HT45R36
SZ [m]
Skip if data memory is 0
Description
If the contents of the specified data memory are 0, the following instruction, fetched during
the current instruction execution, is discarded and a dummy cycle is replaced to get the
proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SZA [m]
Move data memory to ACC, skip if 0
Description
The contents of the specified data memory are copied to the accumulator. If the contents is
0, the following instruction, fetched during the current instruction execution, is discarded
and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed
with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SZ [m].i
Skip if bit i of the data memory is 0
Description
If bit i of the specified data memory is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
TABRDC [m]
Move the ROM code (current page) to TBLH and data memory
Description
The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved
to the specified data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
TABRDL [m]
Move the ROM code (last page) to TBLH and data memory
Description
The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to
the data memory and the high byte transferred to TBLH directly.
Note that this instruction is not valid for HT48R07A-1/HT48C07
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
36
September 28, 2006
HT45R36
XOR A,[m]
Logical XOR accumulator with data memory
Description
Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
XORM A,[m]
Logical XOR data memory with the accumulator
Description
Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
XOR A,x
Logical XOR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
37
September 28, 2006
HT45R36
Package Information
44-pin QFP (10´10) Outline Dimensions
H
C
D
G
2 3
3 3
I
3 4
2 2
L
F
A
B
E
1 2
4 4
K
a
J
1
Symbol
Rev. 1.00
1 1
Dimensions in mm
Min.
Nom.
Max.
A
13
¾
13.4
B
9.9
¾
10.1
C
13
¾
13.4
D
9.9
¾
10.1
E
¾
0.8
¾
F
¾
0.3
¾
G
1.9
¾
2.2
H
¾
¾
2.7
I
0.25
¾
0.5
J
0.73
¾
0.93
K
0.1
¾
0.2
L
¾
0.1
¾
a
0°
¾
7°
38
September 28, 2006
HT45R36
52-pin QFP (14´14) Outline Dimensions
C
H
D
3 9
G
2 7
I
2 6
4 0
F
A
B
E
1 4
5 2
K
J
1
Symbol
Rev. 1.00
1 3
Dimensions in mm
Min.
Nom.
Max.
A
17.3
¾
17.5
B
13.9
¾
14.1
C
17.3
¾
17.5
D
13.9
¾
14.1
E
¾
1
¾
F
¾
0.4
¾
G
2.5
¾
3.1
H
¾
¾
3.4
I
¾
0.1
¾
J
0.73
¾
1.03
K
0.1
¾
0.2
a
0°
¾
7°
39
September 28, 2006
HT45R36
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Copyright Ó 2006 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this handbook is believed to be accurate at the time of publication. However, Holtek assumes
no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for
the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without
further modification, nor recommends the use of its products for application that may present a risk to human life due to
malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please
visit our web site at http://www.holtek.com.tw.
Rev. 1.00
40
September 28, 2006