HOLTEK HT49RA0

HT49RA0/HT49CA0
Remote Type 8-Bit MCU with LCD
Technical Document
· Tools Information
· FAQs
· Application Note
- HA0075E MCU Reset and Oscillator Circuits Application Note
Features
· Operating voltage: 2.0V~3.6V
· Watchdog Timer
· 8 bidirectional I/O lines and 8 input lines
· HALT function and wake-up feature reduce power
consumption
· Two external interrupt input
· One 8-bit programmable timer/event counter
· 4-level subroutine nesting
· LCD driver with 21´2, 21´3 or 20´4 segments
· Bit manipulation instruction
· 14-bit table read instruction
· 2K´14 program memory
· Up to 1ms instruction cycle with 4MHz system clock
· 96´8 data memory RAM
· 63 powerful instructions
· Real Time Clock (RTC)
· All instructions in 1 or 2 machine cycles
· 8-bit prescaler for RTC
· Low voltage reset/detector function
· One carrier output (1/2 or 1/3 duty)
· 52-pin QFP package
· Software LCD, RTC control
· On-chip RC and 32768Hz crystal oscillator
General Description
The HT49RA0/HT49CA0 are 8-bit high performance,
RISC architecture microcontroller devices specifically
designed for multiple I/O control product applications.
The mask version HT49CA0 is fully pin and functionally
compatible with the OTP version HT49RA0 device.
enhance the versatility of this device to suit a wide range
of application possibilities such as industrial control,
consumer products, and particularly suitable for use in
products such as infrared LCD remote controllers and
various subsystem controllers.
The advantages of low power consumption, I/O
flexibility, timer functions, oscillator options, watchdog
timer, HALT and wake-up functions, as well as low cost,
The HT49CA0 is under development and will be available soon.
Rev. 1.20
1
October 24, 2007
HT49RA0/HT49CA0
Block Diagram
In te rru p t
C ir c u it
S T A C K
P ro g ra m
C o u n te r
P ro g ra m
m e m o ry
M
T M R C
T M R
U
fS
fS
IN T C
M
U
D A T A
M e m o ry
X
S Y S C L K /4
M U X
M
W D T
S T A T U S
A L U
T im in g
G e n e r a tio n
P C 0 /R E M
P C 0 C o n tro l
R T C
In s tr u c tio n
D e c o d e r
/4
C a r r ie r C o n tr o l
F r e q u e n c y D iv id e r
M P
Y S
L e v e l o r C a r r ie r
S Y S C L K /4
In s tr u c tio n
R e g is te r
Y S
R T C In te rru p t
P B 2 /T M R
X
U
R T C
X
T im e B a s e
O S C
O S C 3
O S C 4
W D T O S C
S h ifte r
P O R T A
P A
P A 0 ~ P A 7
B P
O S C 4
O S
R E
V D
V S
O S
S
A C C
C 1
S B
D
P O R T B
L C D
M e m o ry
C 3
P B 0 /IN T 0
P B 1 /IN T 1
P B 2 /T M R
P B
P B 3 ~ P B 7
L C D D r iv e r
E N /D IS
H A L T
C O M 0 ~
C O M 2
C O M 3 /
S E G 2 0
S E G 0 ~
S E G 1 9
L V D /L V R
Pin Assignment
O
O
O
S
S
S
E G
E G
E G
S C
S C
V D
S C
R E
P A
P A
P A
P A
P A
D
S
4
3
1
4
3
2
1
0
0
1
2
P B 0
P B 1
P B 2
P C 0
P A 5
P A 6
P A 7
/IN T 0
/IN T 1
/T M R
P B 3
P B 4
P B 5
V S S
/R E M
P B 6
P B 7
5 2 5 1 5 0 4 9 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0
1
3 9
3 8
2
3 7
3
3 6
4
5
3 5
6
H T 4 9 R A 0 /H T 4 9 C A 0
5 2 Q F P -A
7
8
9
1 0
1 1
1 2
1 3
1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6
3 4
3 3
3 2
3 1
3 0
2 9
2 8
2 7
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
S E G
S E G
S E G
S E G
C O M
C O M
C O M
C O M
C 2
C 1
V 2
V 1
V L C
D
1 6
1 7
1 8
1 9
3 /S E G 2 0
2
1
0
Rev. 1.20
2
October 24, 2007
HT49RA0/HT49CA0
Pin Description
Pin Name
I/O
Options
Description
PA0~PA7
I/O
¾
Bidirectional 8-bit input/output port with pull-high resistors. Each bit can
be determined as NMOS output or Schmitt trigger input by software instructions.
PB0/INT0
PB1/INT1
PB2/TMR
PB3~PB7
I
Wake-up
8-bit Schmitt trigger input port with pull-high resistors. Eash bit can be
configured as a wake-up input by code option.
Pins PB0, PB1 and PB2 are pin-shared with INT0, INT1 and TMR respectively.
PC0/REM
I/O
V1, V2, C1, C2
Level or Carrier Level or carrier output pin
Pull-high
PC0 can be set as CMOS output pin or carrier output pin by code option.
¾
I
Voltage pump
LCD power supply
VLCD should be larger than VDD for correct operation i.e. VLCD ³ VDD.
VLCD
COM0~COM2
COM3/SEG20
O
1/2, 1/3 or 1/4
Duty
SEG0~SEG11
O
¾
SEG12~SEG19
O
OSC1
I
OSC3
OSC4
COM3/SEG20 can be set as a segment or as a common output driver for
LCD panel by options. COM0~COM2 are output for LCD panel plate.
LCD driver outputs for LCD panel segments.
SEG12~SEG19 LCD driver outputs for LCD panel segments.
CMOS output SEG12~SEG19 can be optioned as logical outputs.
RC
OSC1 connect a resistor to GND for internal system clock.
I
O
¾
Real time clock oscillator. OSC3 and OSC4 are connected to a 32768Hz
crystal oscillator for timing purpose. It can¢t be used as a system clock. No
capacitor is built-in. If RTC is not selected as fs. OSC3,OSC4 should be
left floating.
RES
I
¾
Schmitt trigger reset input, active low.
VSS
¾
¾
Negative power supply, ground
VDD
¾
¾
Positive power supply
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V
Storage Temperature ............................-50°C to 125°C
Input Voltage..............................VSS-0.3V to VDD+0.3V
IOL Total ..............................................................150mA
Total Power Dissipation .....................................500mW
Operating Temperature...........................-40°C to 85°C
IOH Total............................................................-100mA
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
VDD
Conditions
¾
Min.
Typ.
Max.
Unit
2.0
¾
3.6
V
VDD
Operating Voltage
¾
IDD
Operating Current
(RC OSC)
3V
No load, fSYS=4MHz
¾
0.7
1.5
mA
ISTB1
Standby Current
(*fS=T1)
3V
No load, system HALT,
LCD off at HALT
¾
0.1
1
mA
ISTB2
Standby Current
(*fS=32.768kHz OSC)
3V
No load, system HALT,
LCD On at HALT, C type
¾
2.5
5
mA
Rev. 1.20
3
October 24, 2007
HT49RA0/HT49CA0
Test Conditions
Symbol
Parameter
VDD
Conditions
Min.
Typ.
Max.
Unit
ISTB3
Standby Current
(*fS=WDT RC OSC)
3V
No load, system HALT
LCD On at HALT, C type
¾
2
5
mA
VIL1
Input Low Voltage for I/O
Ports, TMR, INT0 and INT1
3V
¾
0
¾
0.3VDD
V
VIH1
Input High Voltage for I/O
Ports, TMR, INT0 and INT1
3V
¾
0.7VDD
¾
VDD
V
VIL2
Input Low Voltage (RES)
3V
¾
0
¾
0.4VDD
V
VIH2
Input High Voltage (RES)
3V
¾
0.9VDD
¾
VDD
V
IOL1
I/O Port & REM Sink Current
3V
VOL=0.1VDD
4
8
¾
mA
IOH1
I/O Port & REM Source Current
3V
VOH=0.9VDD
-5
-7
¾
mA
IOL2
LCD Common and Segment
Current
3V
VOL=0.1VDD
210
420
¾
mA
IOH2
LCD Common and Segment
Current
3V
VOH=0.9VDD
-80
-160
¾
mA
RPH
Pull-high Resistance of I/O Ports
3V
¾
100
150
200
kW
VLVR
Low Voltage Reset Voltage
¾
¾
2.0
2.1
2.2
V
VLVD
Low Voltage Detector Voltage
¾
¾
2.2
2.3
2.4
V
VPOR
VDD Start Voltage to Ensure
Power-on Reset
¾
¾
¾
¾
100
mV
RPOR
VDD Rise Rate to Ensure
Power-on Reset
¾
¾
0.035
¾
¾
V/ms
Note:
²*² for the value of VA refer to the LCD driver section.
tSYS=1/fSYS
²*fS² please refer to WDT clock option
A.C. Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
VDD
Conditions
Min.
Typ.
Max.
Unit
fSYS
System Clock
¾
2.0V~3.6V, 4MHz ± 3%,
Temp.= 0°C ~ 50°C
¾
4000
¾
kHz
fRTCOSC
RTC Frequency
¾
¾
¾
32768
¾
Hz
fTIMER
Timer I/P Frequency (TMR)
3V
¾
0
¾
4000
kHz
tWDTOSC Watchdog Oscillator Period
3V
¾
45
90
180
ms
tRES
External Reset Low Pulse Width
¾
¾
1
¾
¾
ms
tLVR
Low Voltage Width to Reset
¾
¾
0.25
1
2
ms
tSST
System Start-up Timer Period
¾
Wake-up from HALT
¾
1024
¾
*tSYS
tINT
Interrupt Pulse Width
¾
¾
1
¾
¾
ms
Note:
*tSYS=1/fSYS
Rev. 1.20
4
October 24, 2007
HT49RA0/HT49CA0
Functional Description
After accessing a program memory word to fetch an instruction code, the value of the PC is incremented by
one. The PC then points to the memory word containing
the next instruction code.
Execution Flow
The system clock is derived from RC oscillator. It is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles.
When executing a jump instruction, conditional skip execution, loading a PCL register, a subroutine call, an initial reset, an internal interrupt, an external interrupt, or
returning from a subroutine, the PC manipulates the
program transfer by loading the address corresponding
to each instruction.
Instruction fetching and execution are pipelined in such
a way that a fetch takes one instruction cycle while decoding and execution takes the next instruction cycle.
The pipelining scheme causes each instruction to effectively execute in a cycle. If an instruction changes the
value of the program counter, two cycles are required to
complete the instruction.
The conditional skip is activated by instructions. Once
the condition is met, the next instruction, fetched during
the current instruction execution, is discarded and a
dummy cycle replaces it to get a proper instruction; otherwise proceed with the next instruction.
Program Counter - PC
The program counter (PC) is of 11 bits wide and controls
the sequence in which the instructions stored in the program ROM are executed. The contents of the PC can
specify a maximum of 2048 addresses.
S y s te m
O S C 2 (R C
C lo c k
T 1
T 2
T 3
T 4
The lower byte of the PC (PCL) is a readable and
writeable register (06H). Moving data into the PCL performs a short jump. The destination is within 256 locations.
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
o n ly )
P C
P C
P C + 1
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
P C + 2
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution Flow
Program Counter
Mode
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial Reset
0
0
0
0
0
0
0
0
0
0
0
External Interrupt 0
0
0
0
0
0
0
0
0
1
0
0
External Interrupt 1
0
0
0
0
0
0
0
1
0
0
0
Timer/Event Counter overflow
0
0
0
0
0
0
0
1
1
0
0
Time Base Interrupt
0
0
0
0
0
0
1
0
0
0
0
RTC Interrupt
0
0
0
0
0
0
1
0
1
0
0
Skip
Program Counter + 2
Loading PCL
*10
*9
*8
@7
@6
@5
@4
@3
@2
@1
@0
Jump, Call Branch
#10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return From Subroutine
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Program Counter
Note:
*10~*0: Program counter bits
#10~#0: Instruction code bits
Rev. 1.20
S10~S0: Stack register bits
@7~@0: PCL bits
5
October 24, 2007
HT49RA0/HT49CA0
· Location 014H
When a control transfer takes place, an additional
dummy cycle is required.
Location 014H is reserved for the real time clock interrupt service program. If a real time clock interrupt occurs, and the interrupt is enabled, and the stack is not
full, the program begins execution at location 014H.
Program Memory - ROM
The program memory (ROM) is used to store the program instructions which are to be executed. It also contains data, table, and interrupt entries, and is organized
into 2048 ´ 14 bits which are addressed by the program
counter and table pointer.
· Table location
Any location in the ROM can be used as a look-up table. The instructions ²TABRDC [m]² (the current page,
1 page=256 words) and ²TABRDL [m]² (the last page)
transfer the contents of the lower-order byte to the
specified data memory, and the contents of the
higher-order byte to TBLH (Table Higher-order byte
register) (08H). Only the destination of the lower-order
byte in the table is well-defined; the other bits of the table word are all transferred to the lower portion of
TBLH, and the remaining 2 bit is read as ²0². The
TBLH is read only, and the table pointer (TBLP) is a
read/write register (07H), indicating the table location.
Before accessing the table, the location should be
placed in TBLP. All the table related instructions require 2 cycles to complete the operation. These areas
may function as a normal ROM depending upon the
user¢s requirements.
Certain locations in the ROM are reserved for special
usage:
· Location 000H
Location 000H is reserved for program initialization.
After chip reset, the program always begins execution
at this location.
· Location 004H
Location 004H is reserved for the external interrupt
service program. If the INT0 input pin is activated, and
the interrupt is enabled, and the stack is not full, the
program begins execution at location 004H.
· Location 008H
0 0 0 H
Location 008H is reserved for the external interrupt
service program also. If the INT1 input pin is activated,
and the interrupt is enabled, and the stack is not full,
the program begins execution at location 008H.
D e v ic e in itia liz a tio n p r o g r a m
0 0 4 H
E x te r n a l in te r r u p t 0 s u b r o u tin e
0 0 8 H
· Location 00CH
E x te r n a l in te r r u p t 1 s u b r o u tin e
0 0 C H
Location 00CH is reserved for the Timer/Event Counter interrupt service program. If a timer interrupt results from a Timer/Event Counter overflow, and if the
interrupt is enabled and the stack is not full, the program begins execution at location 00CH.
T im e r /e v e n t c o u n te r 0 in te r r u p t s u b r o u tin e
0 1 0 H
T im e B a s e In te r r u p t
0 1 4 H
· Location 010H
1 0 0 H
L o o k - u p ta b le ( 2 5 6 w o r d s )
1 F F H
Location 010H is reserved for the Time Base interrupt
service program. If a Time Base interrupt occurs, and
the interrupt is enabled, and the stack is not full, the
program begins execution at location 010H.
P ro g ra m
R O M
R T C In te rru p t
n F F H
7 0 0 H
L o o k - u p ta b le ( 2 5 6 w o r d s )
7 F F H
1 4 b its
N o te : n ra n g e s fro m
0 to 6
Program Memory
Table Location
Instruction(s)
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
P10
P9
P8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table Location
Note:
*10~*0: Table location bits
@7~@0: Table pointer bits
Rev. 1.20
P10~P8: Current program Counter bits
6
October 24, 2007
HT49RA0/HT49CA0
Stack Register - STACK
0 0 H
0 1 H
The stack register is a special part of the memory used
to save the contents of the program counter. The stack
is organized into 4 levels and is neither part of the data
nor part of the program, and is neither readable nor
writeable. Its activated level is indexed by a stack
pointer (SP) and is neither readable nor writeable. At a
commencement of a subroutine call or an interrupt acknowledgment, the contents of the program counter is
pushed onto the stack. At the end of the subroutine or interrupt routine, signaled by a return instruction (RET or
RETI), the contents of the program counter is restored
to its previous value from the stack. After chip reset, the
SP will point to the top of the stack.
0 2 H
0 3 H
M P 0
In d ir e c t A d d r e s s in g R e g is te r 1
M P 1
0 4 H
B P
0 5 H
A C C
0 6 H
P C L
0 7 H
T B L P
0 8 H
T B L H
0 9 H
R T C C
0 A H
S T A T U S
0 B H
0 C H
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag is recorded but the acknowledgment is still inhibited. Once the SP is decremented (by RET or RETI), the interrupt is serviced. This
feature prevents stack overflow, allowing the programmer to use the structure easily. Likewise, if the stack is
full, and a ²CALL² is subsequently executed, a stack
overflow occurs and the first entry is lost (only the most
recent 4 return addresses are stored).
In d ir e c t A d d r e s s in g R e g is te r 0
IN T C 0
0 D H
T M R
0 E H
T M R C
0 F H
1 0 H
S p e c ia l P u r p o s e
D a ta M e m o ry
1 1 H
1 2 H
P A
1 3 H
1 4 H
P B
1 5 H
1 6 H
P C
1 7 H
P C C
1 8 H
Data Memory - RAM
1 9 H
1 A H
The data memory is divided into two functional group :
special function registers (20´8) and general purpose
data memory (96´8). Most of them are read/write, but
some are read only.
1 B H
1 C H
1 D H
1 E H
1 F H
2 0 H
The unused space before 20H is reserved for future expanded usage and reading these locations will return
the result 00H. The general purpose data memory, addressed from 20H to 7FH, is used for data and control
information under instruction command. The areas in
the RAM can directly handle arithmetic, logic, increment, decrement, and rotate operations. Except some
dedicated bits, each bit in the RAM can be set and reset
by ²SET [m].i² and ²CLR [m].i². They are also indirectly
accessible through the Memory pointer register 0
(MP0;01H) or the Memory pointer register 1 (MP1;03H).
L C D C
R e a d a s ² 0 0 ²
G e n e ra l P u rp o s e
D a ta M e m o ry
(9 6 B y te s )
7 F H
RAM Mapping
Accumulator - ACC
The accumulator (ACC) is related to the ALU operations. It is also mapped to location 05H of the RAM and
is capable of operating with immediate data. The data
movement between two data memory locations must
pass through the ACC.
Indirect Addressing Register
Location 00H and 02H are indirect addressing registers
that are not physically implemented. Any read/write operation of [00H] and [02H] accesses the RAM pointed to
by MP0 (01H) and MP1(03H) respectively. Reading location 00H or 02H indirectly returns the result 00H.
While, writing it indirectly leads to no operation.
Arithmetic and Logic Unit - ALU
This circuit performs 8-bit arithmetic and logic operations and provides the following functions:
· Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
The function of data movement between two indirect addressing registers is not supported. The memory pointer
registers, MP0 and MP1, are both 7-bit registers used to
access the RAM by combining corresponding indirect
addressing registers. MP0 can only be applied to data
memory, while MP1 can be applied to data memory and
LCD display memory.
Rev. 1.20
: U n u s e d .
IN T C 1
· Logic operations (AND, OR, XOR, CPL)
· Rotation (RL, RR, RLC, RRC)
· Increment and Decrement (INC, DEC)
· Branch decision (SZ, SNZ, SIZ, SDZ etc.)
The ALU not only saves the results of a data operation but
also changes the status register.
7
October 24, 2007
HT49RA0/HT49CA0
Status Register - STATUS
Once an interrupt subroutine is serviced, other interrupts are all blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other
interrupt requests may take place during this interval,
but only the interrupt request flag will be recorded. If a
certain interrupt requires servicing within the service
routine, the EMI bit and the corresponding bit of the
INTC0 or of INTC1 may be set in order to allow interrupt
nesting. Once the stack is full, the interrupt request will
not be acknowledged, even if the related interrupt is enabled, until the Stack Pointer is decremented. If immediate service is desired, the stack should be prevented
from becoming full.
The status register (0AH) is of 8 bits wide and contains,
a carry flag (C), an auxiliary carry flag (AC), a zero flag
(Z), an overflow flag (OV), a power down flag (PDF), and
a watchdog time-out flag (TO). It also records the status
information and controls the operation sequence.
Except the TO and PDF flags, bits in the status register
can be altered by instructions similar to other registers.
Data written into the status register does not alter the TO
or PDF flags. Operations related to the status register,
however, may yield different results from those intended. The TO and PDF flags can only be changed by
a Watchdog Timer overflow, chip power-up, or clearing
the Watchdog Timer and executing the ²HALT² instruction. The Z, OV, AC, and C flags reflect the status of the
latest operations.
All these interrupts can support a wake-up function. As
an interrupt is serviced, a control transfer occurs by
pushing the contents of the program counter onto the
stack followed by a branch to a subroutine at the specified location in the ROM. Only the contents of the program counter is pushed onto the stack. If the contents of
the register or of the status register (STATUS) is altered
by the interrupt service program which corrupts the desired control sequence, the contents should be saved in
advance.
On entering the interrupt sequence or executing the
subroutine call, the status register will not be automatically pushed onto the stack. If the contents of the status
is important, and if the subroutine is likely to corrupt the
status register, the programmer should take precautions
and save it properly.
External interrupts are triggered by a high to low or low
to high or both transition of INT0 or INT1, and the related
interrupt request flag (EIF0;bit 4 of INTC0, EIF1;bit 5 of
INTC0) is set as well. After the interrupt is enabled, the
stack is not full, and the external interrupt is active, a
subroutine call to location 04H or 08H occurs. The interrupt request flag (EIF0 or EIF1) and EMI bits are all
cleared to disable other interrupts.
Interrupts
The devices provides two external interrupts, one internal timer/event counter interrupts, an internal time base
interrupt, and an internal real time clock interrupt. The
interrupt control register 0 (INTC0;0BH) and interrupt
control register 1 (INTC1;1EH) both contain the interrupt
control bits that are used to set the enable/disable status
and interrupt request flags.
Bit No.
Label
Function
0
C
C is set if the operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction.
1
AC
AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
2
Z
3
OV
OV is set if the operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
4
PDF
PDF is cleared by either a system power-up or executing the ²CLR WDT² instruction. PDF is
set by executing the ²HALT² instruction.
5
TO
TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO
is set by a WDT time-out.
6, 7
¾
Unused bit, read as ²0²
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.
Status (0AH) Register
Rev. 1.20
8
October 24, 2007
HT49RA0/HT49CA0
The internal Timer/Event Counter interrupt is initialized
by setting the Timer/Event Counter interrupt request flag
(TF;bit 6 of INTC0), which is normally caused by a timer
overflow. After the interrupt is enabled, and the stack is
not full, and the TF bit is set, a subroutine call to location
0CH occurs. The related interrupt request flag (TF) is reset, and the EMI bit is cleared to disable further interrupts.
Interrupts occurring in the interval between the rising
edges of two consecutive T2 pulses are serviced on the
latter of the two T2 pulses if the corresponding interrupts
are enabled. In the case of simultaneous requests, the
priorities in the following table apply. These can be
masked by resetting the EMI bit.
Interrupt Source
The time base interrupt is initialized by setting the time
base interrupt request flag (TBF;bit 4 of INTC1), that is
caused by a regular time base signal. After the interrupt
is enabled, and the stack is not full, and the TBF bit is
set, a subroutine call to location 10H occurs. The related
interrupt request flag (TBF) is reset and the EMI bit is
cleared to disable further interrupts.
The real time clock interrupt is initialized by setting the
real time clock interrupt request flag (RTF; bit 5 of
INTC1), that is caused by a regular real time clock signal.
After the interrupt is enabled, and the stack is not full, and
the RTF bit is set, a subroutine call to location 14H occurs. The related interrupt request flag (RTF) is reset and
the EMI bit is cleared to disable further interrupts.
Priority
Vector
External interrupt 0
1
04H
External interrupt 1
2
08H
Timer/Event Counter overflow
3
0CH
Time base interrupt
4
10H
Real time clock interrupt
5
14H
The EMI, EEI0, EEI1, ETI, ETBI and ERTI are all used to
control the enable/disable status of interrupts. These
bits prevent the requested interrupt from being serviced.
Once the interrupt request flags (RTF, TBF, TF, EIF1,
EIF0) are all set, they remain in the INTC1 or INTC0 respectively until the interrupts are serviced or cleared by
a software instruction.
During the execution of an interrupt subroutine, other interrupt acknowledgments are all held until the ²RETI² instruction is executed or the EMI bit and the related
interrupt control bit are set both to 1 (if the stack is not
full). To return from the interrupt subroutine, ²RET² or
²RETI² may be invoked. RETI sets the EMI bit and enables an interrupt service, but RET does not.
Bit No.
Label
Function
0
EMI
Controls the master (global) interrupt (1=enabled; 0=disabled)
1
EEI0
Controls the external interrupt 0 (1=enabled; 0=disabled)
2
EEI1
Controls the external interrupt 1 (1=enabled; 0=disabled)
3
ETI
Controls the Timer/Event Counter interrupt (1=enabled; 0=disabled)
4
EIF0
External interrupt 0 request flag (1=active; 0=inactive)
5
EIF1
External interrupt 1 request flag (1=active; 0=inactive)
6
TF
Internal Timer/Event Counter request flag (1=active; 0=inactive)
7
¾
Unused bit, read as ²0²
INTC0 (0BH) Register
Bit No.
Label
Function
0
ETBI
Controls the time base interrupt (1=enabled; 0:disabled)
1
ERTI
Controls the real time clock interrupt (1=enabled; 0:disabled)
2, 3
¾
Unused bit, read as ²0²
4
TBF
Time base request flag (1=active; 0=inactive)
5
RTF
Real time clock request flag (1=active; 0=inactive)
6, 7
¾
Unused bit, read as ²0²
INTC1 (1EH) Register
Rev. 1.20
9
October 24, 2007
HT49RA0/HT49CA0
It is recommended that a program not use the ²CALL
subroutine² within the interrupt subroutine. It¢s because
interrupts often occur in an unpredictable manner or require to be serviced immediately in some applications.
At this time, if only one stack is left, and enabling the interrupt is not well controlled, operation of the ²call² in the
interrupt subroutine may damage the original control sequence.
Oscillator Configuration
An external resistor between OSC1 and VSS in needed
and the resistance is about 12kW. The RC oscillator
provides a ±3% accuracy, the conditions are:
· VDD=2.0V~3.6V
· Temp.= 0°C ~ 50°C
· fSYS=4MHz
O S C 1
R C
O s c illa to r
System Oscillator
LCD/RTC OSC Control Register
Two bit in (1FH) are for controlling LCD and RTC OSC.
Bit No.
Label
Function
0
RTCEN
Controls RTC OSC enable (1=enabled; 0=disabled)
1
LCDEN
Controls LCD enable (1=enabled; 0=disabled)
2~7
¾
Unused bit, read as ²0²
LCDC (1FH) Register
LCDEN and RTCEN may decide LCD and RTC On/Off condition on normal operation.
fS Clock
Source
LCD/WDT Control Bits
LCDEN, RTCEN=0, 0
LCDEN, RTCEN=0, 1
LCDEN, RTCEN=1, 0
LCDEN, RTCEN=1, 1
fSYS/4
LCD off, RTC off
LCD off, RTC off
LCD on, RTC off
LCD on, RTC off
WDT OSC
LCD off, RTC off
LCD off, RTC off
LCD on, RTC off
LCD on, RTC off
RTC OSC
(WDT enable)
LCD off, RTC on
LCD off, RTC on
LCD on, RTC on
LCD on, RTC on
RTC OSC
(WDT disable)
LCD off, RTC off
LCD off, RTC on
LCD on, RTC on
LCD on, RTC on
Rev. 1.20
10
October 24, 2007
HT49RA0/HT49CA0
Watchdog Timer - WDT
(TBF; bit 4 of INTC1) is set. But if the interrupt is enabled, and the stack is not full, a subroutine call to location 10H occurs.
The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator) or an instruction clock
(system clock/4) or a real time clock oscillator (RTC oscillator). The timer is designed to prevent a software
malfunction or sequence from jumping to an unknown
location with unpredictable results. The WDT can be
disabled by option. But if the WDT is disabled, all executions related to the WDT lead to no operation.
fS
O p tio n
L C D
The WDT time-out period is as fS/216~fS/215.
2
D r iv e r ( fS /2
B u z z e r (fS /2
If the WDT clock source chooses the internal WDT oscillator, the time-out period may vary with temperature, VDD,
and process variations. On the other hand, if the clock
source selects the instruction clock and the ²HALT² instruction is executed, WDT may stop counting and lose its
protecting purpose, and the logic can only be restarted by
an external logic.
2
O p tio n
~ fS /2
~ fS /2
9
8
T im e B a s e In te r r u p t
)
(fS /2
)
1 2
~ fS /2
1 5
)
Time Base
Real Time Clock - RTC
The real time clock (RTC) is operated in the same manner as the time base that is used to supply a regular internal interrupt. Its time-out period ranges from fS/28 to
fS/215 by software programming . Writing data to RT2,
RT1 and RT0 (bit2, 1, 0 of RTCC;09H) yields various
time-out periods. If the RTC time-out occurs, the related
interrupt request flag (RTF; bit 5 of INTC1) is set. But if
the interrupt is enabled, and the stack is not full, a subroutine call to location 14H occurs. The real time clock
time-out signal also can be applied to be a clock source of
Timer/Event Counter for getting a longer time-out period.
When the device operates in a noisy environment, using
the on-chip RC oscillator (WDT OSC) is strongly recommended, since the HALT can stop the system clock.
The WDT overflow under normal operation initializes a
²chip reset² and sets the status bit ²TO². In the HALT
mode, the overflow initializes a ²warm reset², and only
the program counter and stack pointer are reset to zero.
To clear the contents of the WDT, there are three methods to be adopted, i.e., external reset (a low level to
RES), software instruction, and a ²HALT² instruction.
There are two types of software instructions; ²CLR
WDT² and the other set - ²CLR WDT1² and ²CLR
WDT2². Of these two types of instruction, only one type
of instruction can be active at a time depending on the
options - ²CLR WDT² times selection option. If the ²CLR
WDT² is selected (i.e., CLR WDT times equal one), any
execution of the ²CLR WDT² instruction clears the WDT.
In the case that ²CLR WDT1² and ²CLR WDT2² are
chosen (i.e., CLR WDT times equal two), these two instructions have to be executed to clear the WDT; otherwise, the WDT may reset the chip due to time-out.
RT2
RT1
RT0
RTC Clock Divided Factor
0
0
0
28*
0
0
1
29*
0
1
0
210*
0
1
1
211*
1
0
0
212
1
0
1
213
1
1
0
214
1
1
1
215
Note: ²*² not recommended to be used
fS
D iv id e r
Time Base
P r e s c a le r
R T 2
R T 1
R T 0
The time base offers a periodic time-out period to generate a regular internal interrupt. Its time-out period
ranges from fS/212 to fS/215 selected by options. If time
base time-out occurs, the related interrupt request flag
S y s te m
P r e s c a le r
D iv id e r
8
8 to 1
M u x .
1 5
fS /2 ~ fS /2
R T C In te rru p t
Real Time Clock
C lo c k /4
R T C
3 2 7 6 8 H z
O S C
O p tio n
S e le c t
fS
D iv id e r
P r e s c a le r
C K
W D T
1 2 k H z
O S C
T
R
C K
T
R
T im e - o u t R e s e t
fS /2 16 ~ fS /2 15
W D T C le a r
Watchdog Timer
Rev. 1.20
11
October 24, 2007
HT49RA0/HT49CA0
Power Down Operation - HALT
Reset
The HALT mode is initialized by the ²HALT² instruction
and results in the following.
There are three ways in which reset may occur.
· The system oscillator turns off but the WDT OSC
· RES is reset during HALT
· RES is reset during normal operation
keeps running (if the WDT oscillator or the real time
clock is selected).
· WDT time-out is reset during normal operation
The WDT time-out during HALT differs from other chip
reset conditions, for it can perform a ²warm reset² that
resets only the program counter and stack pointer and
leaves the other circuits at their original state. Some registers remain unaffected during any other reset conditions. Most registers are reset to the ²initial condition²
once the reset conditions are met. Examining the PDF
and TO flags, the program can distinguish between different ²chip resets².
· The contents of the on-chip RAM and of the registers
remain unchanged.
· The WDT is cleared and start recounting (if the WDT
clock source is from the WDT oscillator or the real time
clock oscillator).
· All I/O ports maintain their original status.
· The PDF flag is set but the TO flag is cleared.
The system quits the HALT mode by an external reset,
an interrupt, an external falling edge signal on port B, or
a WDT overflow. An external reset causes device initialization, and the WDT overflow performs a ²warm reset².
After examining the TO and PDF flags, the reason for
chip reset can be determined. The PDF flag is cleared by
system power-up or by executing the ²CLR WDT² instruction, and is set by executing the ²HALT² instruction.
On the other hand, the TO flag is set if WDT time-out occurs, and causes a wake-up that only resets the program
counter and Stack Pointer, and leaves the others at their
original state.
Note:
The port B wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit
in port B can be independently selected to wake-up the
device by option. Awakening from an I/O port stimulus,
the program resumes execution of the next instruction.
On the other hand, awakening from an interrupt, two sequences may occur. If the related interrupt is disabled or
the interrupt is enabled but the stack is full, the program
resumes execution at the next instruction. But if the interrupt is enabled, and the stack is not full, the regular interrupt response takes place.
²*² Make the length of the wiring, which is connected to the RES pin as short as possible, to
avoid noise interference.
TO
PDF
0
0
RES reset during power-up
u
u
RES reset during normal operation
0
1
RES Wake-up HALT
1
u
WDT time-out during normal operation
1
1
WDT Wake-up HALT
Note:
RESET Conditions
²u² means unchanged
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses when the system awakes from the HALT state. Awaking from the
HALT state, the SST delay is added.
An extra SST delay is added during the power-up period
and any wakeup from the HALT may enable only the
SST delay.
When an interrupt request flag is set before entering the
²HALT² status, the system cannot be awaken using that
interrupt.
The functional unit chip reset status is shown below.
Program Counter
If wake-up events occur, it takes 1024 tSYS (system
clock period) to resume normal operation. In other
words, a dummy period is inserted after the wake-up. If
the wake-up results from an interrupt acknowledgment,
the actual interrupt subroutine execution is delayed by
more than one cycle. However, if the Wake-up results in
the next instruction execution, the execution will be performed immediately after the dummy period is finished.
000H
Interrupt
Disabled
Prescaler, Divider
Cleared
WDT, RTC,
Time base
Cleared. After master reset,
WDT starts counting
Timer/Event Counter Off
Input/output ports
Input mode
Stack Pointer
Points to the top of the stack
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
When at HALT state and fS=fSYS/4, LCD and RTC will be
turned off no matter the bit value of (LCDEN, RTCEN).
Rev. 1.20
12
October 24, 2007
HT49RA0/HT49CA0
V
V D D
V
D D
0 .0 1 m F
R E S
tS
S T
1 0 0 k W
1 0 0 k W
S S T T im e - o u t
C h ip
R E S
R e s e t
0 .1 m F
Reset Timing Chart
H A L T
B a s ic
R e s e t
C ir c u it
W a rm
W D T
R e s e t
R E S
1 0 k W
0 .1 m F
H i-n o is e
R e s e t
C ir c u it
Reset Circuit
W D T
T im e - o u t
R e s e t
Note: Most applications can use the Basic Reset Circuit
as shown, however for applications with extensive noise,
it is recommended to use the Hi-noise Reset Circuit.
E x te rn a l
R E S
C o ld
R e s e t
S S T
1 0 - b it R ip p le
C o u n te r
O S C 1
D D
P o w e r - o n D e te c tio n
Reset Configuration
The states of the registers are summarized below:
Register
Reset
(Power-on)
WDT Time-out
RES Reset
(Normal Operation) (Normal Operation)
RES Reset
(HALT)
WDT Time-out
(HALT)*
MP0
-xxx xxxx
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
MP1
-xxx xxxx
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
BP
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
000H
000H
000H
000H
000H
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
--xx xxxx
--uu uuuu
--uu uuuu
--uu uuuu
--uu uuuu
RTCC
--00 0111
--00 0111
--00 0111
--00 0111
--uu uuuu
STATUS
--00 xxxx
--1u uuuu
--uu uuuu
--01 uuuu
--11 uuuu
INTC0
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
TMR
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMRC
0000 1---
0000 1---
0000 1---
0000 1---
uuuu u---
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PB
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PC
---- ---1
---- ---1
---- ---1
---- ---1
---- ---u
PCC
---- ---1
---- ---1
---- ---1
---- ---1
---- ---u
INTC1
--00 --00
--00 --00
--00 --00
--00 --00
--uu --uu
LCDC
---- --11
---- --11
---- --11
---- --11
---- --uu
Program Counter
Note:
²*² refers to warm reset
²u² means unchanged
²x² means unknown
²-² means unimplemented
Rev. 1.20
13
October 24, 2007
HT49RA0/HT49CA0
Timer/Event Counter
mode can be used to count the high or low level duration
of the external signal (TMR), and the counting is based
on the internal selected clock source.
One timer/event counters are implemented in the devices.
It contains an 8-bit programmable count-up counter.
In the event count or timer mode, the timer/event counter starts counting at the current contents in the
timer/event counter and ends at FFH. Once an overflow
occurs, the counter is reloaded from the timer/event
counter preload register, and generates an interrupt request flag (TF;bit 6 of INTC0).
The timer/event counter clock source may come from
the system clock or system clock/4 or RTC time-out signal or external source. System clock source or system
clock/4 is selected by option.
Using external clock input allows the user to count external events, measure time internals or pulse widths, or
generate an accurate time base. While using the internal clock allows the user to generate an accurate time
base.
In the pulse width measurement mode with the values of the TON and TE bit equal to one, after the TMR
has received a transient from low to high (or high to
low if the TE bit is ²0²), it will start counting until the
TMR returns to the original level and resets the TON.
The measured result remains in the timer/event
counter even if the activated transient occurs again.
In other words, only one cycle measurement can be
made until the TON is set. The cycle measurement will
re-function as long as it receives further transient pulse.
In this operation mode, the timer/event counter begins
counting according not to the logic level but to the transient edges. In the case of counter overflows, the counter
is reloaded from the timer/event counter preload register
and issues an interrupt request, as in the other two
modes, i.e., event and timer modes.
There are two registers related to the timer/event counter, i.e., TMR (0DH) and TMRC (0EH). There are also
two physical registers are mapped to TMR location; writing TMR places the starting value in the timer/event
counter preload register, while reading it yields the contents of the timer/event counter. TMRC is timer/event
counter control register used to define some options.
The TM0 and TM1 bits define the operation mode. The
event count mode is used to count external events,
which means that the clock source is from an external
(TMR) pin. The timer mode functions as a normal timer
with the clock source coming from the internal selected
clock source. Finally, the pulse width measurement
Bit No.
Label
0~2
¾
Unused bit, read as ²0²
Function
3
TE
To define the TMR active edge of timer/event counter
(0=active on low to high; 1=active on high to low)
4
TON
5
TS
6
7
TM0
TM1
To enable/disable timer counting
(0=disabled; 1=enabled)
2 to 1 multiplexer control inputs to select the timer/event counter clock source
(0=RTC outputs; 1= system clock or system clock/4)
To define the operating mode (TM1, TM0)
01=Event count mode (External clock)
10=Timer mode (Internal clock)
11=Pulse Width measurement mode (External clock)
00=Unused
TMRC (0EH) Register
S y s te m
S y s te m
C lo c k
C lo c k /4
O p tio n
S e le c t
M
U
X
D a ta b u s
R T C In te rru p t
T M 1
T M 0
T S
T M R
T im e r /E v e n t C o u n te r
P r e lo a d R e g is te r
R e lo a d
T E
T M 1
T M 0
T O N
T im e r /E v e n t
C o u n te r
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
O v e r flo w
T o In te rru p t
Timer/Event Counter
Rev. 1.20
14
October 24, 2007
HT49RA0/HT49CA0
Carrier Generator
To enable the counting operation, the Timer ON bit
(TON: bit 4 of TMRC) should be set to 1. In the pulse
width measurement mode, the TON is automatically
cleared after the measurement cycle is completed. But
in the other two modes, the TON can only be reset by instructions. The overflow of the timer/event counter is
one of the wake-up sources. No matter what the operation mode is, writing a 0 to ETI disables the related interrupt service.
The HT49RA0/HT49CA0 provides a carrier output
which shares the pin with PC0. It can be selected to be a
carrier output (REM) or level output pin (PC0) by code
option. If the carrier output option is selected, setting
PC0=²1² to enable carrier output and setting PC0=²0² to
disable it at low level output.
The clock source of the carrier is implemented by instruction clock (system clock divided by 4) and processed by a frequency divider to yield various carry
frequency.
In the case of timer/event counter OFF condition, writing
data to the timer/event counter preload register also reloads that data to the timer/event counter. But if the
timer/event counter is turn on, data written to the
timer/event counter is kept only in the timer/event counter preload register. The timer/event counter still continues its operation until an overflow occurs.
Carry Frequency=
Clock Source
m ´ 2n
where m=2 or 3 and n=0~3, both are selected by code
option. If m=2, the duty cycle of the carrier output is 1/2
duty. If m=3, the duty cycle of the carrier output can be
1/2 duty or 1/3 duty also determined by code option (with
the exception of n=0).
When the timer/event counter (reading TMR) is read,
the clock is blocked to avoid errors. As this may results
in a counting error, blocking of the clock should be taken
into account by the programmer.
Detailed selection of the carrier duty is shown below:
It is strongly recommended to load a desired value into
the TMR register first, then turn on the related
timer/event counter for proper operation. Because the
initial value of TMR is unknown.
m´2n
Due to the timer/event scheme, the programmer should
pay special attention on the instruction to enable then
disable the timer for the first time, whenever there is a
need to use the timer/event function, to avoid
unpredicatable result. After this procedure, the
timer/event function can be operated normally.
Duty Cycle
2, 4, 8, 16
1/2
3
1/3
6, 12, 24
1/2 or 1/3
The following table shows examples of carrier frequency selection.
fSYS
fCARRIER
Duty
m´2n
37.92kHz
1/3 only
3
56.9kHz
1/2 only
2
455kHz
F r e q u e n c y D iv id e r
C lo c k S o u r c e
( S y s te m C lo c k /4 )
3 - b it C o u n te r
1 /2 o r 1 /3 d u ty
1 /2
C o d e O p tio n
1 /3
C a r r ie r D u ty
S e le c t
R E M 1
Carrier/Level Output
Rev. 1.20
15
October 24, 2007
HT49RA0/HT49CA0
Input/Output Ports
executed first to disable related NMOS device, and then
²MOV A, [m]² to get stable data.
There are an 8-bit bidirectional input/output port, a 8-bit input port and one-bit input/output port in the
HT49RA0/HT49CA0, labeled as PA, PB and PC which
are mapped to [12H], [14H], [16H] of the RAM respectively. Each bit of PA can be selected as NMOS output or
Schmitt trigger with pull-high resistor by software instruction. PB0~PB7 can only be used for input operation
(Schmitt trigger with pull-high resistors). PC is only one-bit
input/output port shares the pin with carrier output.
After chip reset, PA, PB and PC remain at a high level input line.
Each bit of PA and PC output latches can be set or
cleared by the ²SET [m].i² and ²CLR [m].i² (m=12H or
16H) instructions respectively.
Some instructions first input data and then follow the
output operations. For example, ²SET [m].i², ²CLR [m]²,
²CPL [m]², ²CPLA [m]² read the entire port states into
the CPU, execute the defined operations (bit-operation),
and then write the results back to the latches or to the
accumulator.
When PA, PB and PC for the input operation, these
ports are non-latched, that is, the inputs should be ready
at the T2 rising edge of the instruction ²MOV A, [m]²
(m=12H or 14H). For PA and PC output operation, all
data are latched and remain unchanged until the output
latch is rewritten.
Each line of PB has a wake-up capability to the device
by code option. The highest seven bits of PC are not
physically implemented, on reading them a ²0² is returned and writing results in a no-operation.
When the PA is used for input operation, it should be
noted that before reading data from pads, a ²1² should
be written to the related bits to disable the NMOS device. That is, the instruction ²SET [m].i² (i=0~7 for PA) is
V
D D
W e a k
P u ll- u p
D a ta B u s
W r ite
D
P A 0 ~ P A 7
Q
C K
S
Q
C h ip R e s e t
R e a d I/O
PA Input/Output Ports
V
D D
W e a k
P u ll- u p
D a ta B u s
P B 0 ~ P B 7
R e a d I/O
S y s te m
W a k e -u p
W a k e - u p O p tio n
IN T 0 fo r P B 0
IN T 1 fo r P B 1
T M R fo r P B 2
PB Input Ports
Rev. 1.20
16
October 24, 2007
HT49RA0/HT49CA0
V
P u ll- H ig h
O p tio n
C o n tr o l B it
D a ta B u s
Q
D
W r ite C o n tr o l R e g is te r
C K
D D
S
Q
C h ip R e s e t
P C 0 /R E M
R e a d C o n tr o l R e g is te r
D a ta B it
Q
D
W r ite D a ta R e g is te r
Q
C K
S
M
R E M 1
M
R e a d D a ta R e g is te r
U
U
X
P C 0 /R E M
S e le c t
X
PC Input/Output Ports
LCD Display Memory
LCD Driver Output
The devices provides an area of embedded data memory for LCD display. This area is located from 40H to
54H of the RAM at Bank 1. Bank pointer (BP; located at
04H of the RAM) is the switch between the RAM and the
LCD display memory. When the BP is set as ²1², any
data written into 40H~54H will effect the LCD display.
When the BP is cleared to ²0², any data written into
40H~54H means to access the general purpose data
memory.
The output number of the LCD driver device can be
21´2, 21´3 or 20´4 by option. The bias type LCD driver
can be ²C² type only. A capacitor mounted between C1
and C2 pins is needed. If 1/2 bias is selected, a capacitor mounted between V2 pin and ground is required. If
1/3 bias is selected, two capacitors are needed for V1
and V2 pins. All the capacitance of capacitors used for
LCD bias generator is suggested to use the 0.1mF. The
relationships between LCD bias types, bias levels and
V1 and V2 connection are listed in the table.
The LCD display memory can be read and written to
only by indirect addressing mode using MP1. When
data is written into the display data area, it is automatically read by the LCD driver which then generates the
corresponding LCD driving signals. To turn the display
on or off, a ²1² or a ²0² is written to the corresponding bit
of the display memory, respectively. The figure illustrates the mapping between the display memory and
LCD pattern for the devices.
C O M
4 0 H
4 1 H
4 2 H
4 3 H
5 2 H
5 3 H
5 4 H
B it
1
2
2
3
3
0
1
2
3
1 8
1 9
V1
V2
VLCD
1/2
C
0.1mF
x
0.1mF
VLCD
1/3
C
0.1mF
0.1mF
0.1mF
VLCD
fS Clock Source
2 0
Display Memory
Rev. 1.20
C1/C2
The options of LCD clock frequency are listed in the following table.
1
S E G M E N T
Bias
Type
There is a clock source needed for LCD driver. The LCD
clock source comes from the general purpose prescaler
and is decided by code options. The LCD clock frequency should be selected as near to 4kHz either from
32768 RTC or WDT or fSYS/4 clock source.
0
0
Bias
Level
17
LCD Clock Selection
WDT Oscillator
WDT/22
RTC Oscillator
RTC/23
fSYS/4
fSYS/24~fSYS/210
October 24, 2007
HT49RA0/HT49CA0
D u r in g a R e s e t P u ls e
V A
C O M 0 ,C O M 1 ,C O M 2
A ll L C D
V B
V S S
V A
V B
V S S
d r iv e r o u tp u ts
N o r m a l O p e r a tio n M o d e
V A
V B
V S
V A
V B
V S
V A
V B
V S
V A
V B
V S
V A
V B
V S
V A
V B
V S
V A
V B
V S
V A
V B
V S
V A
V B
V S
V A
V B
V S
V A
V B
V S
C O M 0
C O M 1
C O M 2
L C D s e g m e n ts O N
C O M 0 ,1 ,2 s id e s a r e u n lig h te d
O n ly L C D s e g m e n ts O N
C O M 0 s id e a r e lig h te d
O n ly L C D s e g m e n ts O N
C O M 1 s id e a r e lig h te d
O n ly L C D s e g m e n ts O N
C O M 2 s id e a r e lig h te d
L C D s e g m e n ts O N
C O M 0 ,1 s id e s a r e lig h te d
L C D s e g m e n ts O N
C O M 0 ,2 s id e s a r e lig h te d
L C D s e g m e n ts O N
C O M 1 ,2 s id e s a r e lig h te d
L C D s e g m e n ts O N
C O M 0 ,1 ,2 s id e s a r e lig h te d
H A L T M o d e
S
S
S
S
S
S
S
S
S
S
S
V A
C O M 0 ,C O M 1 ,C O M 2
V B
V S S
V A
V B
V S S
A ll L C D d r iv e r o u tp u ts
N o te : " * " O m it th e C O M 2 s ig n a l, if th e 1 /2 d u ty L C D
V A = V L C D , V B = V L C D x 1 /2
is u s e d .
LCD Driver Output (1/3 Duty, 1/2 Bias, C Type)
Rev. 1.20
18
October 24, 2007
HT49RA0/HT49CA0
V A
V B
C O M 0
V C
V S S
V A
V B
C O M 1
V C
V S S
V A
V B
C O M 2
V C
V S S
V A
V B
C O M 3
V C
V S S
V A
V B
L C D s e g m e n ts O N
C O M 2 s id e lig h te d
V C
V S S
N o te : V A = V L C D x 1 .5 , V B = V L C D , V C = V L C D x 1 /2
LCD Driver Output (1/4 Duty, 1/3 Bias, C Type)
Rev. 1.20
19
October 24, 2007
HT49RA0/HT49CA0
Low Voltage Reset/Detector Functions
There is a low voltage detector (LVD) and a low voltage reset circuit (LVR) implemented in the microcontroller. These
two functions can be enabled/disabled by options. Once the LVD options is enabled, the user can use the RTCC.3 to
enable/disable (1/0) the LVD circuit and read the LVD detector status (0/1) from RTCC.5; otherwise, the LVD function is
disabled.
The RTCC register definitions are listed below.
Bit No.
Label
Function
0~2
RT0~RT2
3
LVDC*
LVD enable/disable (1/0)
4
QOSC
32768Hz OSC quick start-up oscillating
0/1: quickly/slowly start
5
LVDO
LVD detection output (1/0)
1: low voltage detected, read only
6, 7
¾
8 to 1 multiplexer control inputs to select the real clock prescaler output
Unused bit, read as ²0²
RTCC (09H) Register
Once the LVD function is enabled the reference generator should be enabled; otherwise the reference generator is
controlled by LVR code option. The relationship among LVR and LVD options and LVDC are as shown.
LVDC can read/write, LVDO is read only.
LVD
LVR
LVDC
VREF Generator
LVR Comparator
Enable
Enable
On
Enable
Enable
Enable
Enable
Enable
Off
Enable
Enable
Disable
Enable
Disable
On
Enable
Disable
Enable
Enable
Disable
Off
Disable
Disable
Disable
Disable
Enable
X
Enable
Enable
Disable
Disable
Disable
X
Disable
Disable
Disable
Rev. 1.20
20
LVD Comparator
October 24, 2007
HT49RA0/HT49CA0
The microcontroller provides a low voltage reset circuit
in order to monitor the supply voltage of the device. If the
supply voltage of the device is within the range
0.9V~VLVR, such as might happen when changing a battery, the LVR will automatically reset the device internally. During a HALT state, LVR is disabled.
The relationship between VDD and VLVR is shown below.
V D D
3 .6 V
The LVR includes the following specifications:
V
· The low voltage (0.9V~VLVR) state must exists for
L V R
2 .0 V
more than 1ms, while the other circuits remain in their
original state. If the low voltage state does not exceed
1ms, the LVR will ignore it and do not perform a reset
function.
0 .9 V
· The LVR uses the ²OR² function with the power-on re-
set signal to perform a chip reset.
V
Note: VOPR is the voltage range for proper chip
operation at 4MHz system clock.
D D
3 .6 V
V
L V R D e te c t V o lta g e
L V R
0 .9 V
0 V
R e s e t S ig n a l
N o r m a l O p e r a tio n
R e s e t
*1
R e s e t
*2
Low Voltage Reset
Note:
²*1² To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system
clock pulses before entering the normal operation.
²*2² Low voltage state has to be maintained for over 1ms, then after a 1ms delay the device enters the reset
mode.
Rev. 1.20
21
October 24, 2007
HT49RA0/HT49CA0
Options
The following shows the options in the devices. All these options should be defined in order to ensure proper system
functioning.
Item
Options
I/O Options
1
PB0~PB7: wake-up enable or disable (bit option)
2
PC0: CMOS output or carrier output (bit option)
3
PC0: Pull-high enable or disable (bit option)
LCD Options
4
LCD clock: fS/22, fS/23, fS/24, fS/25, fS/26, fS/27, fS/28
5
LCD duty: 1/2, 1/3, 1/4
6
LCD bias: 1/2, 1/3
7
LCD segment 12~15 output or CMOS output(Nibble Option)
8
LCD segment 16~19 output or CMOS output(Nibble Option)
Interrupt Options
9
INT0 function: enable or disable
10
Triggering edge: rising, falling or both
11
INT1 function: enable or disable
12
Triggering edge: rising, falling or both
Oscillator Options
13
fS internal clock source: RTC oscillator, WDT oscillator or fSYS/4
Timer Options
14
Timer/Event Counter clock source: fSYS or fSYS/4
Time Base Options
15
Time Base division ratio: fS/212, fS/213, fS/214, fS/215
Watchdog Options
16
WDT enable or disable
17
CLRWDT instructions: 1 or 2 instructions
LVD/LVR Options
18
Low Voltage Detect: enable or disable
19
LVR function: enable or disable
Carrier Options
20
Carrier duty: 1/2 duty or 1/3 duty
21
Carrier frequency: fSYS/8, fSYS/16, fSYS/32, fSYS/64 for 1/2 duty cycle
22
Carrier frequency: fSYS/12, 1/3 duty cycle
23
Carrier frequency: fSYS/24, fSYS/48, fSYS/96 for 1/2 duty or 1/3 duty cycle
Rev. 1.20
22
October 24, 2007
HT49RA0/HT49CA0
Application Circuits
V
D D
V D D
R e s e t
C ir c u it
1 0 0 k W
0 .1 m F
R E S
P A 0 ~ P A 7
0 .1 m F
P B 0 /IN T 0
V
P B 1 /IN T 1
V S S
P B 2 /T M R
4 7 0 p F
P B 3 ~ P B 7
O S C
C ir c u it
D D
O S C 1
R
O S C 1
S y s te m
= 1 2 k W
O s c illa to r
S C
O S C
P C 0 /R E M
O S C 1
O S C 3
3 2 7 6 8 H z C ry s ta l
S y s te m O s c illa to r
O S C 1 L e ft U n c o n n e c te d
O S C 4
H T 4 9 R A 0 /H T 4 9 C A 0
Note:
R C
R O
O S C
C ir c u it
1. Reset circuit
The reset circuit resistance and capacitance values should be chosen to ensure that VDD is stable and remains within its operating voltage range before the RES pin reaches a high level. Ensure that the length of
the wiring connected to the RES pin is kept as short as possible, to avoid noise interference.
2. For applications where noise may interfere with the reset circuit and for details on the oscillator external
components, refer to Application Note HA0075E for more information.
Rev. 1.20
23
October 24, 2007
HT49RA0/HT49CA0
Example
P A 2
P A 1
P A 3
P A 0
P B 3
P A 4
P B 2
P A 5
P B 1
P B 7
P B 0
V
P B 6
D D
P B 5
V D D
P B 4
R e s e t
C ir c u it
1 0 0 k W
0 .1 m F
V L C D
L C D
P o w e r S u p p ly
R E S
0 .1 m F
C O M 0 ~ C O M 2
C O M 3 /S E G 2 0
S E G 0 ~ S E G 1 9
V S S
3 3 W
1 W
L C D
P A N E L
C 1
V D D
0 .1 m F
1 0 0 m F
C 2
V b a t
2 2 0 W ~ 1 k W
V 1
0 .1 m F
P C 0 /R E M
V 2
O S C
C ir c u it
0 .1 m F
O S C 1
H T 4 9 R A 0 /H T 4 9 C A 0
Rev. 1.20
24
October 24, 2007
HT49RA0/HT49CA0
Instruction Set
subtract instruction mnemonics to enable the necessary
arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for
subtraction. The increment and decrement instructions
INC, INCA, DEC and DECA provide a simple means of
increasing or decreasing by a value of one of the values
in the destination specified.
Introduction
Central to the successful operation of any
microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to
perform certain operations. In the case of Holtek
microcontrollers, a comprehensive and flexible set of
over 60 instructions is provided to enable programmers
to implement their application with the minimum of programming overheads.
Logical and Rotate Operations
For easier understanding of the various instruction
codes, they have been subdivided into several functional groupings.
The standard logical operations such as AND, OR, XOR
and CPL all have their own instruction within the Holtek
microcontroller instruction set. As with the case of most
instructions involving data manipulation, data must pass
through the Accumulator which may involve additional
programming steps. In all logical data operations, the
zero flag may be set if the result of the operation is zero.
Another form of logical data manipulation comes from
the rotate instructions such as RR, RL, RRC and RLC
which provide a simple means of rotating one bit right or
left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for
serial port programming applications where data can be
rotated from an internal register into the Carry bit from
where it can be examined and the necessary serial bit
set high or low. Another application where rotate data
operations are used is to implement multiplication and
division calculations.
Instruction Timing
Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are
required. One instruction cycle is equal to 4 system
clock cycles, therefore in the case of an 8MHz system
oscillator, most instructions would be implemented
within 0.5ms and branch or call instructions would be implemented within 1ms. Although instructions which require one more cycle to implement are generally limited
to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions
which involve manipulation of the Program Counter Low
register or PCL will also take one more cycle to implement. As instructions which change the contents of the
PCL will imply a direct jump to that new address, one
more cycle will be required. Examples of such instructions would be ²CLR PCL² or ²MOV PCL, A². For the
case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then
this will also take one more cycle, if no skip is involved
then only one cycle is required.
Branches and Control Transfer
Program branching takes the form of either jumps to
specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the
sense that in the case of a subroutine call, the program
must return to the instruction immediately when the subroutine has been carried out. This is done by placing a
return instruction RET in the subroutine which will cause
the program to jump back to the address right after the
CALL instruction. In the case of a JMP instruction, the
program simply jumps to the desired location. There is
no requirement to jump back to the original jumping off
point as in the case of the CALL instruction. One special
and extremely useful set of branch instructions are the
conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program
will continue with the next instruction or skip over it and
jump to the following instruction. These instructions are
the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits.
Moving and Transferring Data
The transfer of data within the microcontroller program
is one of the most frequently used operations. Making
use of three kinds of MOV instructions, data can be
transferred from registers to the Accumulator and
vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most
important data transfer applications is to receive data
from the input ports and transfer data to the output ports.
Arithmetic Operations
The ability to perform certain arithmetic operations and
data manipulation is a necessary feature of most
microcontroller applications. Within the Holtek
microcontroller instruction set are a range of add and
Rev. 1.20
25
October 24, 2007
HT49RA0/HT49CA0
Bit Operations
Other Operations
The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek
microcontrollers. This feature is especially useful for
output port bit programming where individual bits or port
pins can be directly set high or low using either the ²SET
[m].i² or ²CLR [m].i² instructions respectively. The feature removes the need for programmers to first read the
8-bit output port, manipulate the input data to ensure
that other bits are not changed and then output the port
with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used.
In addition to the above functional instructions, a range
of other instructions also exist such as the ²HALT² instruction for Power-down operations and instructions to
control the operation of the Watchdog Timer for reliable
program operations under extreme electric or electromagnetic environments. For their relevant operations,
refer to the functional related sections.
Instruction Set Summary
The following table depicts a summary of the instruction
set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions.
Table Read Operations
Table conventions:
Data storage is normally implemented by using registers. However, when working with large amounts of
fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an
area of Program Memory to be setup as a table where
data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be
referenced and retrieved from the Program Memory.
Mnemonic
x: Bits immediate data
m: Data Memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Description
Cycles
Flag Affected
1
1Note
1
1
1Note
1
1
1Note
1
1Note
1Note
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
C
1
1
1
1Note
1Note
1Note
1
1
1
1Note
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
1
1Note
1
1Note
Z
Z
Z
Z
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Add Data Memory to ACC
Add ACC to Data Memory
Add immediate data to ACC
Add Data Memory to ACC with Carry
Add ACC to Data memory with Carry
Subtract immediate data from the ACC
Subtract Data Memory from ACC
Subtract Data Memory from ACC with result in Data Memory
Subtract Data Memory from ACC with Carry
Subtract Data Memory from ACC with Carry, result in Data Memory
Decimal adjust ACC for Addition with result in Data Memory
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
Logical AND Data Memory to ACC
Logical OR Data Memory to ACC
Logical XOR Data Memory to ACC
Logical AND ACC to Data Memory
Logical OR ACC to Data Memory
Logical XOR ACC to Data Memory
Logical AND immediate Data to ACC
Logical OR immediate Data to ACC
Logical XOR immediate Data to ACC
Complement Data Memory
Complement Data Memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rev. 1.20
Increment Data Memory with result in ACC
Increment Data Memory
Decrement Data Memory with result in ACC
Decrement Data Memory
26
October 24, 2007
HT49RA0/HT49CA0
Mnemonic
Description
Cycles
Flag Affected
Rotate Data Memory right with result in ACC
Rotate Data Memory right
Rotate Data Memory right through Carry with result in ACC
Rotate Data Memory right through Carry
Rotate Data Memory left with result in ACC
Rotate Data Memory left
Rotate Data Memory left through Carry with result in ACC
Rotate Data Memory left through Carry
1
1Note
1
1Note
1
1Note
1
1Note
None
None
C
C
None
None
C
C
Move Data Memory to ACC
Move ACC to Data Memory
Move immediate data to ACC
1
1Note
1
None
None
None
Clear bit of Data Memory
Set bit of Data Memory
1Note
1Note
None
None
Jump unconditionally
Skip if Data Memory is zero
Skip if Data Memory is zero with data movement to ACC
Skip if bit i of Data Memory is zero
Skip if bit i of Data Memory is not zero
Skip if increment Data Memory is zero
Skip if decrement Data Memory is zero
Skip if increment Data Memory is zero with result in ACC
Skip if decrement Data Memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1Note
1note
1Note
1Note
1Note
1Note
1Note
1Note
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read table (current page) to TBLH and Data Memory
Read table (last page) to TBLH and Data Memory
2Note
2Note
None
None
No operation
Clear Data Memory
Set Data Memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of Data Memory
Swap nibbles of Data Memory with result in ACC
Enter power down mode
1
1Note
1Note
1
1
1
1Note
1
1
None
None
None
TO, PDF
TO, PDF
TO, PDF
None
None
TO, PDF
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note:
1. For skip instructions, if the result of the comparison involves a skip then two cycles are required,
if no skip takes place only one cycle is required.
2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.
3. For the ²CLR WDT1² and ²CLR WDT2² instructions the TO and PDF flags may be affected by
the execution status. The TO and PDF flags are cleared after both ²CLR WDT1² and
²CLR WDT2² instructions are consecutively executed. Otherwise the TO and PDF flags
remain unchanged.
Rev. 1.20
27
October 24, 2007
HT49RA0/HT49CA0
Instruction Definition
ADC A,[m]
Add Data Memory to ACC with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the Accumulator.
Operation
ACC ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADCM A,[m]
Add ACC to Data Memory with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADD A,[m]
Add Data Memory to ACC
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
ADD A,x
Add immediate data to ACC
Description
The contents of the Accumulator and the specified immediate data are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + x
Affected flag(s)
OV, Z, AC, C
ADDM A,[m]
Add ACC to Data Memory
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
AND A,[m]
Logical AND Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
Z
AND A,x
Logical AND immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical AND
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
Z
ANDM A,[m]
Logical AND ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
Z
Rev. 1.20
28
October 24, 2007
HT49RA0/HT49CA0
CALL addr
Subroutine call
Description
Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the
stack. The specified address is then loaded and the program continues execution from this
new address. As this instruction requires an additional operation, it is a two cycle instruction.
Operation
Stack ¬ Program Counter + 1
Program Counter ¬ addr
Affected flag(s)
None
CLR [m]
Clear Data Memory
Description
Each bit of the specified Data Memory is cleared to 0.
Operation
[m] ¬ 00H
Affected flag(s)
None
CLR [m].i
Clear bit of Data Memory
Description
Bit i of the specified Data Memory is cleared to 0.
Operation
[m].i ¬ 0
Affected flag(s)
None
CLR WDT
Clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT1
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT2
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
Rev. 1.20
29
October 24, 2007
HT49RA0/HT49CA0
CPL [m]
Complement Data Memory
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa.
Operation
[m] ¬ [m]
Affected flag(s)
Z
CPLA [m]
Complement Data Memory with result in ACC
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa. The complemented result
is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
Z
DAA [m]
Decimal-Adjust ACC for addition with result in Data Memory
Description
Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or
if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble
remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of
6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C
flag may be affected by this instruction which indicates that if the original BCD sum is
greater than 100, it allows multiple precision decimal addition.
Operation
[m] ¬ ACC + 00H or
[m] ¬ ACC + 06H or
[m] ¬ ACC + 60H or
[m] ¬ ACC + 66H
Affected flag(s)
C
DEC [m]
Decrement Data Memory
Description
Data in the specified Data Memory is decremented by 1.
Operation
[m] ¬ [m] - 1
Affected flag(s)
Z
DECA [m]
Decrement Data Memory with result in ACC
Description
Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] - 1
Affected flag(s)
Z
HALT
Enter power down mode
Description
This instruction stops the program execution and turns off the system clock. The contents
of the Data Memory and registers are retained. The WDT and prescaler are cleared. The
power down flag PDF is set and the WDT time-out flag TO is cleared.
Operation
TO ¬ 0
PDF ¬ 1
Affected flag(s)
TO, PDF
Rev. 1.20
30
October 24, 2007
HT49RA0/HT49CA0
INC [m]
Increment Data Memory
Description
Data in the specified Data Memory is incremented by 1.
Operation
[m] ¬ [m] + 1
Affected flag(s)
Z
INCA [m]
Increment Data Memory with result in ACC
Description
Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] + 1
Affected flag(s)
Z
JMP addr
Jump unconditionally
Description
The contents of the Program Counter are replaced with the specified address. Program
execution then continues from this new address. As this requires the insertion of a dummy
instruction while the new address is loaded, it is a two cycle instruction.
Operation
Program Counter ¬ addr
Affected flag(s)
None
MOV A,[m]
Move Data Memory to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
None
MOV A,x
Move immediate data to ACC
Description
The immediate data specified is loaded into the Accumulator.
Operation
ACC ¬ x
Affected flag(s)
None
MOV [m],A
Move ACC to Data Memory
Description
The contents of the Accumulator are copied to the specified Data Memory.
Operation
[m] ¬ ACC
Affected flag(s)
None
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
No operation
Affected flag(s)
None
OR A,[m]
Logical OR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
Z
Rev. 1.20
31
October 24, 2007
HT49RA0/HT49CA0
OR A,x
Logical OR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
Z
ORM A,[m]
Logical OR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²OR² [m]
Affected flag(s)
Z
RET
Return from subroutine
Description
The Program Counter is restored from the stack. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
Affected flag(s)
None
RET A,x
Return from subroutine and load immediate data to ACC
Description
The Program Counter is restored from the stack and the Accumulator loaded with the
specified immediate data. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
None
RETI
Return from interrupt
Description
The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending
when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program.
Operation
Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
None
RL [m]
Rotate Data Memory left
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ [m].7
Affected flag(s)
None
RLA [m]
Rotate Data Memory left with result in ACC
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ [m].7
Affected flag(s)
None
Rev. 1.20
32
October 24, 2007
HT49RA0/HT49CA0
RLC [m]
Rotate Data Memory left through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7
replaces the Carry bit and the original carry flag is rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RLCA [m]
Rotate Data Memory left through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces
the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in
the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RR [m]
Rotate Data Memory right
Description
The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into
bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ [m].0
Affected flag(s)
None
RRA [m]
Rotate Data Memory right with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data
Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ [m].0
Affected flag(s)
None
RRC [m]
Rotate Data Memory right through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0
replaces the Carry bit and the original carry flag is rotated into bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
C
RRCA [m]
Rotate Data Memory right through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is
stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
C
Rev. 1.20
33
October 24, 2007
HT49RA0/HT49CA0
SBC A,[m]
Subtract Data Memory from ACC with Carry
Description
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result
of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or
zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SBCM A,[m]
Subtract Data Memory from ACC with Carry and result in Data Memory
Description
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is
positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SDZ [m]
Skip if decrement Data Memory is 0
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0 the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] - 1
Skip if [m] = 0
Affected flag(s)
None
SDZA [m]
Skip if decrement Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0, the program proceeds with the following instruction.
Operation
ACC ¬ [m] - 1
Skip if ACC = 0
Affected flag(s)
None
SET [m]
Set Data Memory
Description
Each bit of the specified Data Memory is set to 1.
Operation
[m] ¬ FFH
Affected flag(s)
None
SET [m].i
Set bit of Data Memory
Description
Bit i of the specified Data Memory is set to 1.
Operation
[m].i ¬ 1
Affected flag(s)
None
Rev. 1.20
34
October 24, 2007
HT49RA0/HT49CA0
SIZ [m]
Skip if increment Data Memory is 0
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] + 1
Skip if [m] = 0
Affected flag(s)
None
SIZA [m]
Skip if increment Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0 the program proceeds with the following instruction.
Operation
ACC ¬ [m] + 1
Skip if ACC = 0
Affected flag(s)
None
SNZ [m].i
Skip if bit i of Data Memory is not 0
Description
If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is 0 the program proceeds with the following instruction.
Operation
Skip if [m].i ¹ 0
Affected flag(s)
None
SUB A,[m]
Subtract Data Memory from ACC
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUBM A,[m]
Subtract Data Memory from ACC with result in Data Memory
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUB A,x
Subtract immediate data from ACC
Description
The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will
be set to 1.
Operation
ACC ¬ ACC - x
Affected flag(s)
OV, Z, AC, C
Rev. 1.20
35
October 24, 2007
HT49RA0/HT49CA0
SWAP [m]
Swap nibbles of Data Memory
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged.
Operation
[m].3~[m].0 « [m].7 ~ [m].4
Affected flag(s)
None
SWAPA [m]
Swap nibbles of Data Memory with result in ACC
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged. The
result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC.3 ~ ACC.0 ¬ [m].7 ~ [m].4
ACC.7 ~ ACC.4 ¬ [m].3 ~ [m].0
Affected flag(s)
None
SZ [m]
Skip if Data Memory is 0
Description
If the contents of the specified Data Memory is 0, the following instruction is skipped. As
this requires the insertion of a dummy instruction while the next instruction is fetched, it is a
two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
Operation
Skip if [m] = 0
Affected flag(s)
None
SZA [m]
Skip if Data Memory is 0 with data movement to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator. If the value is
zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the
program proceeds with the following instruction.
Operation
ACC ¬ [m]
Skip if [m] = 0
Affected flag(s)
None
SZ [m].i
Skip if bit i of Data Memory is 0
Description
If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is not 0, the program proceeds with the following instruction.
Operation
Skip if [m].i = 0
Affected flag(s)
None
TABRDC [m]
Read table (current page) to TBLH and Data Memory
Description
The low byte of the program code (current page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
TABRDL [m]
Read table (last page) to TBLH and Data Memory
Description
The low byte of the program code (last page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
Rev. 1.20
36
October 24, 2007
HT49RA0/HT49CA0
XOR A,[m]
Logical XOR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XORM A,[m]
Logical XOR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XOR A,x
Logical XOR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical XOR
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Z
Rev. 1.20
37
October 24, 2007
HT49RA0/HT49CA0
Package Information
52-pin QFP (14´14) Outline Dimensions
C
H
D
3 9
G
2 7
I
2 6
4 0
F
A
B
E
1 4
5 2
K
J
1
Symbol
Rev. 1.20
1 3
Dimensions in mm
Min.
Nom.
Max.
A
17.3
¾
17.5
B
13.9
¾
14.1
C
17.3
¾
17.5
D
13.9
¾
14.1
E
¾
1
¾
F
¾
0.4
¾
G
2.5
¾
3.1
H
¾
¾
3.4
I
¾
0.1
¾
J
0.73
¾
1.03
K
0.1
¾
0.2
a
0°
¾
7°
38
October 24, 2007
HT49RA0/HT49CA0
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
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http://www.holtek.com
Copyright Ó 2007 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.20
39
October 24, 2007