HOLTEK HT82K68E-L_11

HT82K68E-L/HT82K68A-L
Multimedia Keyboard Encoder 8-Bit MCU
Features
· Operating voltage: 1.8V~5.5V
· HALT function and wake-up feature reduce power
consumption
· 34 bidirectional I/O line and 3 CMOS output
· Six-level subroutine nesting
· One 8-bit programmable timer counter with overflow
· Bit manipulation instructions
interrupts
· Crystal or RC oscillator
· 16-bit table read instructions
· Watchdog Timer
· 63 powerful instructions
· 3K´16 program EPROM
· All instructions in 1 or 2 machine cycles
· 160´8 data RAM
· 20/28-pin SOP, 32-pin QFN and
48-pin SSOP/LQFP packages
· One external interrupt pin (shared with PC2)
· 2.0V LVR by option (default disable)
General Description
This device is an 8-bit high performance peripheral interface IC, designed for multiple I/O products and multimedia applications. It supports interface to a low speed
PC with multimedia keyboard or wireless keyboard in
Windows 95, Windows 98 or Windows 2000 environment. A HALT feature is included to reduce power consumption.
Rev. 1.40
The mask version HT82K68A-L is fully pin and functionally
compatible with the OTP version HT82K68E-L device.
1
February 1, 2011
HT82K68E-L/HT82K68A-L
Block Diagram
S T A C K 0
S T A C K 1
S T A C K 2
S T A C K 3
P ro g ra m
R O M
P C 2
In te rru p t
C ir c u it
S T A C K 4
S T A C K 5
P ro g ra m
C o u n te r
IN T C
S Y S C L K /4
T M R
T M R C
In s tr u c tio n
R e g is te r
M P 0
M P 1
M
8 b it
U
S Y S C L K /4
X
W D T S
D A T A
M e m o ry
W D T P r e s c a le r
W D T
M
U
X
R C
In s tr u c tio n
D e c o d e r
P E C
M U X
A L U
T im in g
G e n e ra to r
P O R T E
P E
P D C
S T A T U S
P O R T D
P D
S h ifte r
P C C
P O R T C
P C
O S C 2
O S
R E
V D
V S
S
C 1
S E T
D
A C C
P B C
P A C
P A
Rev. 1.40
P O R T B
P B
2
P O R T A
O S C
P E 0 ~ P E 4
P D 0 ~ P D 7
P C 0 ~ P C 7
P B 0 ~ P B 7
P A 0 ~ P A 7
February 1, 2011
HT82K68E-L/HT82K68A-L
Pin Assignment
1
2 0
P A 4
P A 2
2
1 9
P A 5
P A 1
3
1 8
P A 6
P A 0
4
1 7
P A 7
P B 1
5
1 6
O S C 2
P B 5
1
4 8
P B 6
P B 0
6
1 5
O S C 1
P B 4
2
4 7
P B 7
V S S
7
1 4
V D D
P A 3
3
4 6
P A 4
P E 2
8
1 3
R E S
P A 2
4
4 5
P A 5
P C 0
9
1 2
P C 3
P A 1
5
4 4
P A 6
P C 1
1 0
1 1
P C 2
P A 0
6
4 3
P A 7
H T 8 2 K 6 8 E -L /H T 8 2 K 6 8 A -L
2 0 S O P -A
P B 3
7
4 2
N C
P B 2
8
4 1
N C
P B 1
9
4 0
N C
P B 0
1 0
3 9
N C
P C 0
P C 1
P C 2
P C 3
P C 4
P C 5
P C 6
P C 7
P A 3
P D 0
P D 1
P D 2
R E S
V D D
O S C 1
O S C 2
P A 7
2
2 4
3
2 3
2 2
H T 8 2 K 6 8 E -L
H T 8 2 K 6 8 A -L
3 2 Q F N -B
6
5
4
2 1
2 0
1 9
1 8
8
7
9 1 0 1 1 1 2 1 3 1 4 1 5 1 6
1 7
V S S
P D 4
P D 5
P B 0
P B 1
P B 2
P B 3
P A 0
P A 1
P A 2
P A 3
P B 4
P B 5
P A 4
P A 5
P A 6
1
2 8
P B 6
N C
1 1
3 8
O S C 2
P B 4
2
2 7
P B 7
N C
1 2
3 7
O S C 1
P A 3
3
2 6
P A 4
P D 7
1 3
3 6
V D D
P A 2
4
2 5
P A 5
P D 6
1 4
3 5
R E S
P A 1
5
2 4
P A 6
P D 5
1 5
3 4
P E 4 (L E D )
1 6
3 3
P D 3
1 7
3 2
P D 2
6
2 3
P A 7
P B 3
7
2 2
O S C 2
V S S
P B 2
8
2 1
O S C 1
P E 2 (L E D )
1 8
3 1
P D 1
P B 1
9
2 0
V D D
P E 3 (L E D )
1 9
3 0
P D 0
P B 0
1 0
1 9
R E S
P C 0
2 0
2 9
P C 7
V S S
1 1
1 8
P C 7
P C 1
2 1
2 8
P C 6
P C 1
1 2
1 7
P C 6
P C 2
2 2
2 7
P C 5
P C 2
1 3
1 6
P C 5
P E 0
2 3
2 6
P C 4
P C 3
1 4
1 5
P C 4
P E 1
2 4
2 5
P C 3
H T 8 2 K 6 8 E -L /H T 8 2 K 6 8 A -L
4 8 S S O P -A
P A 0
P B 3
P B 2
P B 1
P B 0
P D 7
P D 6
P D 5
P D 4
V S S
P E 2 (L E D )
N C
4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7
1
2
3 6
3 5
3
3 4
4
3 3
5
3 2
H T 8 2 K 6 8 E -L
H T 8 2 K 6 8 A -L
4 8 L Q F P -A
6
7
8
3 1
3 0
2 9
9
2 8
1 0
2 7
1 1
1 2
2 6
1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4
2 5
N C
N C
N C
N C
O S C 2
O S C 1
V D D
R E S
P E 4 (L E D )
P D 3
P D 2
P D 1
P D 0
P C 7
P C 6
P C 5
P C 4
P C 3
P E 1
P E 0
P C 2
P C 1
P C 0
P E 3 (L E D )
P A 0
P D 4
N C
P A 7
P A 6
P A 5
P A 4
P B 7
P B 6
P B 5
P B 4
P A 3
P A 2
P A 1
P B 5
H T 8 2 K 6 8 E -L /H T 8 2 K 6 8 A -L
2 8 S O P -A
3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5
1
Pin Description
Pin Name
I/O
Mask
Option
Description
PA0~PA7
I/O
Wake-up
Pull-high
or None
Bidirectional 8-bit input/output port. Each bit can be configured as a wake-up input
by mask option. Software* instructions determine the CMOS output or Schmitt
Trigger input with or without 12K pull-high resistor.
PB0~PB7
I/O
Pull-high
or None
Bidirectional 8-bit input/output port. Software* instructions determine the output or
Schmitt Trigger input with or without pull-high resistor.
PC0
I/O
Wake-up
Pull-high
or None
This pin is an I/O port. NMOS open drain output with pull-high resistor and can be
used as DATA or CLOCK line of PS2. This pin can be configured as a wake-up
input by mask option.
PC1
I/O
Wake-up
Pull-high
or None
This pin is an I/O port. NMOS open drain output with pull-high resistor and can be
used as DATA or CLOCK line of PS2. This pin can be configured as a wake-up
input by mask option.
PC2~PC3
I/O
Wake-up
Pull-high
or None
Bidirectional 2-bit input/output port. Each bit can be configured as a wake-up input
by mask option. Software* instructions determine the CMOS output or Schmitt
Trigger input with or without pull-high resistor.
PC2 also as external interrupt input pin. PE0 determine whether rising edge or
falling edge of PC2 to trigger the INT circuit.
PC4~PC7
I/O
Pull-high
or None
Bidirectional 4-bit input/output port. Software* instructions determine the CMOS
output or Schmitt Trigger input with or without pull-high resistor.
PD0~PD7
I/O
Pull-high
or None
Bidirectional 8-bit input/output port. Software* instructions determine the CMOS
output or Schmitt Trigger input with or without pull-high resistor.
Rev. 1.40
3
February 1, 2011
HT82K68E-L/HT82K68A-L
I/O
Mask
Option
Description
PE0~PE1
I/O
Pull-high
or None
Bidirectional input/output port. Software* instruction determine the CMOS output
or Schmitt Trigger input with or without pull-high resistor.
If PE0 output 1, rising edge of PC2 trigger INT circuit.
PE0 output 0, falling edge of PC2 trigger INT circuit.
PE2
O
This pin is a CMOS output structure. The pad can function as LED (SCR) drivers
for the keyboard. IOL=18mA at VOL=3.4V
PE3
O
This pin is a CMOS output structure. The pad can function as LED (NUM) drivers
for the keyboard. IOL=18mA at VOL=3.4V
PE4
O
This pin is a CMOS output structure. The pad can function as LED (CAP) drivers for
the keyboard. IOL=18mA at VOL=3.4V
VDD
¾
¾
Positive power supply
VSS
¾
¾
Negative power supply, ground
RES
I
¾
Chip reset input. Active low. Built-in power-on reset circuit to reset the entire chip.
Chip can also be externally reset via RES pin
OSC1
OSC2
I
O
Crystal or
RC
OSC1, OSC2 are connected to an RC network or a crystal for the internal system
clock. In the case of RC operation, OSC2 is the output terminal for the 1/4 system
clock; A 110kW resistor is connected to OSC1 to generate a 2 MHZ frequency.
Pin Name
Note:
*: Software means the HT-IDE (Holtek Integrated Development Environment) can be configured by mask
option.
Absolute Maximum Ratings
Supply Voltage ..........................VSS-0.3V to VSS+6.0V
Storage Temperature ...........................-50°C to 125°C
Input Voltage .............................VSS-0.3V to VDD+0.3V
Operating Temperature ..........................-25°C to 70°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device
reliability.
D.C. Characteristics
Symbol
Parameter
VDD
Operating Voltage
IDD1
Operating Current (Crystal OSC)
Ta=25°C
Test Conditions
VDD
Conditions
¾
¾
3V
No load, fSYS= 6MHz
5V
IDD2
3V
Operating Current (RC OSC)
No load, fSYS= 6MHz
5V
ISTB1
3V
Standby Current (WDT enabled)
No load, system HALT
5V
ISTB2
3V
Standby Current (WDT Disabled)
No load, system HALT
5V
VIL1
VIH1
Rev. 1.40
Input Low Voltage for I/O Ports
(Schmitt)
Input High Voltage for I/O Ports
(Schmitt)
Min.
Typ.
Max.
Unit
1.8
¾
5.5
V
¾
0.7
1.5
mA
¾
2
5
mA
¾
0.5
1.5
mA
¾
2
5
mA
¾
¾
8
mA
¾
¾
15
mA
¾
¾
3
mA
¾
¾
6
mA
3V
¾
0
¾
0.3VDD
V
5V
¾
0
¾
0.3VDD
V
3V
¾
0.7VDD
¾
VDD
V
5V
¾
0.7VDD
¾
VDD
V
4
February 1, 2011
HT82K68E-L/HT82K68A-L
Symbol
VIL2
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
¾
0
¾
0.7
V
5V
¾
0
¾
1.3
V
3V
¾
0.9VDD
¾
VDD
V
5V
¾
0.9VDD
¾
VDD
V
VDD
Conditions
3V
Input Low Voltage (RESET)
VIH2
Input High Voltage (RESET)
VLVR
Low Voltage Reset
¾
¾
¾
2.0
¾
V
IOL
I/O Port Sink Current of PA, PB, PC,
PD, PE0~1
5V
VOL= 0.1VDD
2
4
¾
mA
IOH
I/O Port Source Current of PA, PB,
PC, PD, PE0~4
5V
VOH= 0.9VDD
-2.5
-4
¾
mA
ILED
LED Sink Current (SCR, NUM, CAP)
5V
VOL=3.4V
10
17
25
mA
tPOR
Power-on Reset Time
5V
R=100kW, C=0.1mF
50
100
150
ms
RPH
Internal Pull-high Resistance of PA,
PB, PC, PD, PE Port
3V
¾
30
60
90
kW
5V
¾
15
30
45
kW
Internal Pull-high Resistance of DATA, 3V
CLK
5V
¾
4
9
15
kW
¾
2
4.7
8
kW
RPH1
Df/f
Frequency Variation
5V
Crystal
¾
¾
±1
%
Df/f1
Frequency Variation
5V
RC
¾
¾
±20
%
A.C. Characteristics
Symbol
fSYS1
Parameter
Ta=25°C
Test Conditions
Min.
Typ.
Max.
Unit
¾
450
¾
4000
kHz
5V
¾
450
¾
8000
kHz
3V
¾
450
¾
6000
kHz
5V
¾
450
¾
8000
kHz
3V
¾
45
90
180
ms
5V
¾
35
78
130
ms
12
23
45
ms
9
19
35
ms
¾
1024
¾
tSYS
1
¾
¾
ms
¾
1024
¾
tSYS
1
¾
¾
ms
VDD
Conditions
1.8V
System Clock (Crystal OSC)
fSYS2
System Clock (RC OSC)
tWDTOSC
Watchdog Oscillator Period
3V
tWDT1
Watchdog Time-out Period (RC)
5V
Without WDT
prescaler
tWDT2
Watchdog Time-out Period
(System Clock)
¾
Without WDT
prescaler
tRES
External Reset Low Pulse Width
¾
tSST
System Start-up Timer Period
¾
tINT
Interrupt Pulse Width
¾
Note:
¾
Power-up or
wake-up from HALT
¾
tSYS= 1/fSYS1 or 1/fSYS2
Rev. 1.40
5
February 1, 2011
HT82K68E-L/HT82K68A-L
Functional Description
Execution Flow
When executing a jump instruction, conditional skip execution, loading PCL register, subroutine call, initial reset, internal interrupt, external interrupt or return from
subroutine, the PC manipulates the program transfer by
loading the address corresponding to each instruction.
The device system clock is derived from either a crystal
or an RC oscillator. The system clock is internally divided into four non-overlapping clocks. One instruction
cycle consists of four system clock cycles.
The conditional skip is activated by instruction. Once the
condition is met, the next instruction, fetched during the
current instruction execution, is discarded and a dummy
cycle replaces it to get the proper instruction. Otherwise
proceed with the next instruction.
Instruction fetching and execution are pipelined in such
a way that a fetch takes one instruction cycle while decoding and execution takes the next instruction cycle.
However, the pipelining scheme causes each instruction to effectively execute within one cycle. If an instruction changes the program counter, two cycles are
required to complete the instruction.
The lower byte of the program counter (PCL) is a readable and writeable register (06H). Moving data into the
PCL performs a short jump. The destination will be within
256 locations.
Program Counter - PC
The 12-bit program counter (PC) controls the sequence
in which the instructions stored in the program ROM are
executed and its contents specify a maximum of 4096
addresses.
Once a control transfer takes place, an additional
dummy cycle is required.
After accessing a program memory word to fetch an instruction code, the contents of the program counter are
incremented by one. The program counter then points to
the memory word containing the next instruction code.
The program memory is used to store the program instructions which are to be executed. It also contains
data, table, and interrupt entries, and is organized with
3072´16 bits, addressed by the program counter and table pointer.
T 1
S y s te m
T 2
T 3
T 4
Program Memory - ROM
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
C lo c k
O S C 2 ( R C o n ly )
( N M O S o p e n d r a in o u tp u t)
P C
P C
P C + 1
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
P C + 2
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution Flow
Mode
Program Counter
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial reset
0
0
0
0
0
0
0
0
0
0
0
0
External interrupt
0
0
0
0
0
0
0
0
0
1
0
0
Timer counter overflow
0
0
0
0
0
0
0
0
1
0
0
0
@4
@3
@2
@1
@0
Skip
Loading PCL
Program Counter+2
*11
*10
*9
*8
@7
@6
@5
Jump, call branch
#11
#10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return from subroutine
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Note: *11~*0: Program counter bits
#11~#0: Instruction code bits
Rev. 1.40
S11~S0: Stack register bits
@7~@0: PCL bits
6
February 1, 2011
HT82K68E-L/HT82K68A-L
0 0 0 H
0 0 8 H
Table Higher-order byte register (TBLH) is read only.
The TBLH is read only and cannot be restored. If the
main routine and the ISR (Interrupt Service Routine)
both employ the table read instruction, the contents of
the TBLH in the main routine are likely to be changed
by the table read instruction used in the ISR. Errors
can occur. In other words, using the table read
instruction in the main routine and the ISR
simultaneously should be avoided. However, if the
table read instruction has to be applied in both the
main routine and the ISR, the interrupt is supposed to
be disabled prior to the table read instruction. It will not
be enabled until the TBLH has been backed up. The
table pointer (TBLP) is a read/write register (07H), which
indicates the table location. Before accessing the table,
the location must be placed in TBLP. All table related
instructions need 2 cycles to complete the operation.
These areas may function as normal program memory
depending upon the requirements.
D e v ic e in itia liz a tio n p r o g r a m
T im e r /e v e n t c o u n te r in te r r u p t s u b r o u tin e
n 0 0 H
P ro g ra m
R O M
L o o k - u p ta b le ( 2 5 6 w o r d s )
n F F H
L o o k - u p ta b le ( 2 5 6 w o r d s )
B F F H
1 6 b its
N o te : n ra n g e s fro m
0 to B
Program Memory
Certain locations in the program memory are reserved
for special usage:
· Location 000
Stack Register - STACK
This area is reserved for the initialization program.
After chip reset, the program always begins execution
at location 000H.
This is a special part of the memory which is used to
save the contents of the program counter (PC) only. The
stack is organized into six levels and is neither part of
the data nor part of the program space, and is neither
readable nor writeable. The activated level is indexed by
the stack pointer (SP) and is neither readable nor
writeable. At a subroutine call or interrupt acknowledgement, the contents of the program counter are pushed
onto the stack. At the end of a subroutine or an interrupt
routine, signaled by a return instruction (RET or RETI),
the program counter is restored to its previous value
from the stack. After a chip reset, the SP will point to the
top of the stack.
· Location 004H
Location 004H is reserved for external interrupt
service program. If the PC2 (external input pin) is
activated, the interrupt is enabled, and the stack is not
full, the program begins execution at location 004H.
The pin PE0 determine whether the rising or falling
edge of the PC2 to activate external interrupt service
program.
· Location 008H
This area is reserved for the timer counter interrupt
service program. If timer interrupt results from a timer
counter overflow, and if the interrupt is enabled and
the stack is not full, the program begins execution at
location 008H.
Data Memory - RAM
The data memory is designed with 184 ´ 8 bits. It is divided into two functional groups: special function registers and general purpose data memory (160´8). Most of
them are read/write, but some are read only.
· Table location
Any location in the ROM space can be used as
look-up tables. The instructions TABRDC [m] (the
current page, one page=256 words) and TABRDL [m]
(the last page) transfer the contents of the lower-order
byte to the specified data memory, and the
higher-order byte to TBLH (08H). Only the destination
of the lower-order byte in the table is well-defined, the
other bits of the table word are transferred to the lower
portion of TBLH, the remaining 1 bit is read as 0. The
Instruction(s)
The unused space before 60H is reserved for future expanded usage and reading these locations will get the
result 00H. The general purpose data memory, addressed from 60H to FFH, is used for data and control
information under instruction command. All data memory areas can handle arithmetic, logic, increment, decrement and rotate operations directly. Except for some
dedicated bits, each bit in the data memory can be set
Table Location
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
P11
P10
P9
P8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
0
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Note: *11~*0: Table location bits
P11~P8: Current program counter bits
@7~@0: Table location bits
Rev. 1.40
7
February 1, 2011
HT82K68E-L/HT82K68A-L
Accumulator
and reset by the SET [m].i and CLR [m].i instructions, respectively. They are also indirectly accessible through
Memory pointer registers (MP0;01H, MP1;03H).
0 0 H
The accumulator is closely related to the ALU operations. It is also mapped to location 05H of the data memory and is capable of carrying out immediate data
operations. The data movement between two data
memory locations must pass through the accumulator.
In d ir e c t A d d r e s s in g R e g is te r 0
0 1 H
M P 0
0 2 H
In d ir e c t A d d r e s s in g R e g is te r 1
0 3 H
M P 1
Arithmetic and Logic Unit - ALU
0 4 H
0 5 H
A C C
0 6 H
P C L
This circuit performs 8-bit arithmetic and logic operation.
The ALU provides the following functions:
0 7 H
T B L P
0 8 H
T B L H
· Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
0 9 H
W D T S
· Logic operations (AND, OR, XOR, CPL)
0 A H
S T A T U S
0 B H
IN T C
· Rotation (RL, RR, RLC, RRC)
· Increment and Decrement (INC, DEC)
0 C H
0 D H
T M R
0 E H
T M R C
· Branch decision (SZ, SNZ, SIZ, SDZ ....)
S p e c ia l P u r p o s e
D a ta M e m o ry
The ALU not only saves the results of a data operation but
also changes the status register.
0 F H
1 0 H
1 1 H
1 2 H
P A
1 3 H
P A C
1 4 H
P B
1 5 H
P B C
1 6 H
P C
1 7 H
P C C
1 8 H
P D
1 9 H
P D C
1 A H
P E
1 B H
1 C H
P E C
2 0 H
6 0 H
Status Register - Status
The 8-bit status register (0AH) contains the zero flag (Z),
carry flag (C), auxiliary carry flag (AC), overflow flag
(OV), power down flag (PDF) and watch dog time-out
flag (TO). The status register not only records the status
information but also controls the operation sequence.
With the exception of the TO and PDF flags, bits in the
status register can be altered by instructions like most
other registers. Any data written into the status register
will not change the TO or PDF flags. It should be noted
that operations related to the status register may give
different results from those intended. The TO and PDF
flags can only be changed by system power up, Watchdog Timer overflow, executing the HALT instruction and
clearing the Watchdog Timer.
: U n u s e d .
G e n e ra l P u rp o s e
D a ta M e m o ry
(1 6 0 B y te s )
R e a d a s ² 0 0 ²
F F H
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
RAM Mapping
Indirect Addressing Register
In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be automatically pushed onto the stack. If the contents of status
are important and if the subroutine can corrupt the status register, precaution must be taken to save it properly.
Location 00H and 02H are indirect addressing registers
that are not physically implemented. Any read/write operation of [00H] and [02H] can access the data memory
pointed to by MP0 (01H) and MP1 (03H) respectively.
Reading location 00H or 02H indirectly will return the result 00H. Writing indirectly results in no operation.
The function of data movement between two indirect addressing registers is not supported. The memory pointer
registers, MP0 and MP1, are 8-bit registers which can
be used to access the data memory by combining corresponding indirect addressing registers.
Rev. 1.40
8
February 1, 2011
HT82K68E-L/HT82K68A-L
Bit No.
Label
Function
0
C
C is set if an operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate
through carry instruction.
1
AC
AC is set if an operation results in a carry out of the low nibbles in addition or if no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
2
Z
Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared.
3
OV
OV is set if an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
4
PDF
PDF is cleared when either a system power-up or executing the CLR WDT instruction. PDF is
set by executing a HALT instruction.
5
TO
TO is cleared by a system power-up or executing the CLR WDT or HALT instruction. TO is set
by a WDT time-out.
6, 7
¾
Unused bit, read as ²0²
Status (0AH) Register
program which corrupt the desired control sequence, the
contents should be saved in advance.
Interrupt
The device provides an internal timer counter interrupt
and an external interrupt shared with PC2. The interrupt
control register (INTC;0BH) contains the interrupt
control bits to set not only the enable/disable status but
also the interrupt request flags.
The internal timer counter interrupt is initialized by setting the timer counter interrupt request flag (T0F; bit 5 of
INTC), which is normally caused by a timer counter
overflow. When the interrupt is enabled, and the stack is
not full and the T0F bit is set, a subroutine call to location
08H will occur. The related interrupt request flag (T0F)
will be reset and the EMI bit cleared to disable further interrupts.
Once an interrupt subroutine is serviced, all other interrupts will be blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other
interrupt requests may occur during this interval but only
the interrupt request flag is recorded. If a certain interrupt requires servicing within the service routine, the
EMI bit and the corresponding bit of the INTC may be
set to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If
immediate service is desired, the stack must be prevented from becoming full.
The external interrupt is shared with PC2. The external
interrupt is activated, the related interrupt request flag
(EIF; bit4 of INTC) is then set. When the interrupt is enabled, the stack is not full, and the external interrupt is
active, a subroutine call to location 04H will occur. The
interrupt request flag (EIF) and EMI bits will also be
cleared to disable other interrupts.
The external interrupt (PC2) can be triggered by a high
to low transition, or a low to high transition of the PC2,
which is dependent on the output level of the PE0.
When PE0 is output high, the external interrupt is triggered by a low to high transition of the PC2. When PE0
is output low, the external interrupt is triggered by a high
to low transition of PC2.
All these kinds of interrupt have the wake-up capability.
As an interrupt is serviced, a control transfer occurs by
pushing the program counter onto the stack followed by
a branch to a subroutine at the specified location in the
program memory. Only the program counter is pushed
onto the stack. If the contents of the register and Status
register (STATUS) are altered by the interrupt service
Bit No.
Label
Function
0
EMI
Controls the master (global) interrupt (1= enabled; 0= disabled)
1
EEI
Control the external interrupt
2
ET0I
Controls the timer counter interrupt (1= enabled; 0= disabled)
3
¾
Unused bit, read as ²0²
4
EIF
External interrupt flag
5
T0F
Internal timer counter request flag (1= active; 0= inactive)
6, 7
¾
Unused bit, read as ²0²
INTC (0BH) Register
Rev. 1.40
9
February 1, 2011
HT82K68E-L/HT82K68A-L
chip itself due to process variations. It is, therefore, not
suitable for timing sensitive operations where accurate
oscillator frequency is desired.
During the execution of an interrupt subroutine, other interrupt acknowledgements are held until the RETI instruction is executed or the EMI bit and the related
interrupt control bit are set to 1 (if the stack is not full). To
return from the interrupt subroutine, a RET or RETI instruction may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET will not.
If the Crystal oscillator is used, a crystal across OSC1
and OSC2 is needed to provide the feedback and phase
shift needed for oscillator, no other external components
are needed. Instead of a crystal, the resonator can also
be connected between OSC1 and OSC2 to get a frequency reference, but two external capacitors in OSC1
and OSC2 are required.
Interrupts occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced
on the latter of the two T2 pulses, if the corresponding
interrupts are enabled. In the case of simultaneous requests, the following table shows the priority that is applied. These can be masked by resetting the EMI bit.
Interrupt Source
The WDT oscillator is a free running on-chip RC oscillator, and no external components are required. Even if the
system enters the power down mode, the system clock is
stopped, but the WDT oscillator still works for a period of
approximately 78ms. The WDT oscillator can be disabled
by mask option to conserve power.
Vector
External interrupt 1
04H
Timer counter overflow
08H
V
O S C 1
Once the interrupt request flags (T0F) are set, they will
remain in the INTC register until the interrupts are serviced or cleared by a software instruction.
O S C 1
O S C 2
It is suggested that a program does not use the ²CALL
subroutine² within the interrupt subroutine. Because
interrupts often occur in an unpredictable manner or
need to be serviced immediately in some applications,
if only one stack is left and enabling the interrupt is not
well controlled, once the ²CALL subroutine² operates in
the interrupt subroutine it will damage the original control sequence.
C r y s ta l O s c illa to r
fS Y S /4
(N M O S O p e n
D r a in O u tp u t)
O S C 2
R C
O s c illa to r
System Oscillator
Watchdog Timer - WDT
The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator) or instruction clock (system clock divided by 4), decided by mask options. This
timer is designed to prevent a software malfunction or sequence jumping to an unknown location with unpredictable results. The Watchdog Timer can be disabled by
mask option. If the Watchdog Timer is disabled, all the executions related to the WDT results in no operation.
Oscillator Configuration
There are two oscillator circuits in the microcontroller.
Both are designed for system clocks; the RC oscillator
and the Crystal oscillator, which are determined by
mask options. No matter what oscillator type is
selected, the signal provides the system clock. The
HALT mode stops the system oscillator and resists the
external signal to conserve power.
Once the internal WDT oscillator (RC oscillator normally
with a period of 78ms) is selected, it is first divided by 256
(8-stages) to get the nominal time-out period of approximately 20ms. This time-out period may vary with temperature, VDD and process variations. By invoking the WDT
prescaler, longer time-out periods can be realized. Writing data to WS2, WS1, WS0 (bit 2,1,0 of the WDTS) can
give different time-out periods. If WS2, WS1, WS0 are all
equal to 1, the division ratio is up to 1:128, and the maximum time-out period is 2.6 seconds.
If an RC oscillator is used, an external resistor between
OSC1 and VDD is needed and the resistance must
range from 20kW to 510kW. The system clock, divided
by 4, is available on OSC2, which can be used to synchronize external logic. The RC oscillator provides the
most cost effective solution. However, the frequency of
the oscillation may vary with VDD, temperature and the
S y s te m
D D
c lo c k /4
W D T
O S C
M a s k
O p tio n
S e le c t
W D T P r e s c a le r
8 - b it C o u n te r
7 - b it C o u n te r
8 -to -1 M U X
W S 0 ~ W S 2
W D T T im e - o u t
Watchdog Timer
Rev. 1.40
10
February 1, 2011
HT82K68E-L/HT82K68A-L
Power Down Operation - HALT
If the WDT oscillator is disabled, the WDT clock may still
come from the instruction clock and operate in the same
manner except that in the HALT state the WDT may stop
counting and lose its protecting purpose. In this situation
the WDT logic can be restarted by external logic. The
high nibble and bit 3 of the WDTS are reserved for user
defined flags, which can be used to indicate some specified status.
The HALT mode is initialized by the HALT instruction
and results in the following...
· The system oscillator will turn off but the WDT oscillator
keeps running (if the WDT oscillator is selected).
· The contents of the on–chip RAM and registers
remain unchanged.
· WDT and WDT prescaler will be cleared and recount
If the device operates in a noisy environment, using the
on-chip RC oscillator (WDT OSC) is strongly recommended, since the HALT will stop the system clock.
WS2
WS1
WS0
Division Ratio
0
0
0
1:1
0
0
1
1:2
0
1
0
1:4
0
1
1
1:8
1
0
0
1:16
1
0
1
1:32
1
1
0
1:64
1
1
1
1:128
again (if the WDT clock has come from the WDT
oscillator).
· All I/O ports maintain their original status.
· The PDF flag is set and the TO flag is cleared.
The system can leave the HALT mode by means of an
external reset, interrupt, and external falling edge signal
on port A and port C [0:3] or a WDT overflow. An external reset causes a device initialization and the WDT
overflow performs a ²warm reset². Examining the TO
and PDF flags, the reason for chip reset can be determined. The PDF flag is cleared when system power-up
or executing the CLR WDT instruction and is set when
the HALT instruction is executed. The TO flag is set if the
WDT time-out occurs, and causes a wake-up that only
resets the program counter and stack pointer, the others
keep their original status.
WDTS (09H) Register
The WDT overflow under normal operation will initialize
²chip reset² and set the status bit TO. An overflow in the
HALT mode, initializes a ²warm reset² only when the program counter and stack pointer are reset to zero. To
clear the contents of the WDT (including the WDT
prescaler ), three methods are adopted; external reset
(a low level to RESET), software instruction(s), or a HALT
instruction. There are two types of software instructions;
CLR WDT and CLR WDT1/CLR WDT2. Of these two
types of instruction, only one can be active depending
on the mask option - ²CLR WDT times selection option².
If the ²CLR WDT² is selected (ie. CLR WDT times equal
one), any execution of the CLR WDT instruction will
clear the WDT. In case ²CLR WDT1² and ²CLR WDT2²
are chosen (ie. CLRWDT times equal two), these two instructions must be executed to clear the WDT; otherwise,
the WDT may reset the chip because of the time-out.
On the other hand, awakening from an external interrupt
(PC2), two sequences may happen. If the interrupt is
disabled or the interrupt is enabled but the stack is full,
the program will resume execution at the next instruction. But if the interrupt is enabled and the stack is not
full, the regular interrupt response takes place.
The port A or port C [0:3] wake-up can be considered as
a continuation of normal execution. Each bit in port A
can be independently selected to wake up the device by
mask option. Awakening from an I/O port stimulus, the
program will resume execution of the next instruction.
Once a wake-up event occurs, and the system clock
comes from a crystal, it takes 1024 tSYS (system clock
period) to resume normal operation. In other words, the
device will insert a dummy period after the wake-up. If
the system clock comes from an RC oscillator, it
continues operating immediately. If the wake-up results
in next instruction execution, this will execute
immediately after the dummy period is completed.
To minimize power consumption, all I/O pins should be
carefully managed before entering the HALT status.
Rev. 1.40
11
February 1, 2011
HT82K68E-L/HT82K68A-L
V D D
Reset
tS
R E S E T
There are three ways in which a reset can occur:
· RESET reset during normal operation
S T
S S T T im e - o u t
· RESET reset during HALT
C h ip
· WDT time-out reset during normal operation
R e s e t
Reset Timing Chart
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a warm reset
that just resets the program counter and stack pointer,
leaving the other circuits to remain in their original state.
Some registers remain unchanged during other reset
conditions. Most registers are reset to the ²initial condition² when the reset conditions are met. By examining
the PDF and TO flags, the program can distinguish between different ²chip resets².
TO
PDF
0
0
RESET reset during power-up
u
u
RESET reset during normal operation
0
0
RESET wake-up HALT
1
u
WDT time-out during normal operation
1
1
WDT wake-up HALT
V
D D
R E S E T
RESET Conditions
Reset Circuit
H A L T
W D T
To guarantee that the system oscillator has started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses when the system powers up or when it awakes from the HALT state.
000H
Prescaler
Clear
WDT
Clear. After master reset,
WDT begins counting
Timer counter
Off
Input/output ports
Input mode
Stack Pointer
Points to the top of the stack
0~3
¾
4
TON
5
¾
6
7
TM0
TM1
R e s e t
C o ld R e s e t
P o w e r - o n D e te c tio n
Reset Configuration
Timer Counter
A timer counter (TMR) is implemented in the
microcontroller. The timer counter contains an 8-bit
programmable count-up counter and the clock may
come from the system clock divided by 4.
The functional unit chip reset status is shown below.
Program Counter
S S T
1 0 -s ta g e
R ip p le C o u n te r
O S C 1
When a system power-up occurs, the SST delay is
added during the reset period. But when the reset comes from the RESET pin, the SST delay is disabled.
Any wake-up from HALT will enable the SST delay.
Label
W a rm
R E S E T
Note: ²u² means unchanged
Bit No.
W D T
T im e - o u t
R e s e t
Using the internal instruction clock, there is only one reference time-base.
There are two registers related to the timer counter;
TMR ([0DH]), TMRC ([0EH]). Two physical registers are
mapped to TMR location; writing TMR makes the starting value be placed in the timer counter preload register
and reading TMR gets the contents of the timer counter.
The TMRC is a timer counter control register, which defines some options.
Function
Unused bit, read as "0"
To enable/disable timer counting (0= disabled; 1= enabled)
Unused bit, read as "0"
10= Timer mode (internal clock)
TMRC (0EH) Register
Rev. 1.40
12
February 1, 2011
HT82K68E-L/HT82K68A-L
The state of the registers is summarized in the following table:
Register
WDT Time-out
RESET Reset
(Normal Operation) (Normal Operation)
Reset
(Power On)
RESET Reset
(HALT)
WDT Time-out
(HALT)
MP0
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
MP1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
000H
000H
000H
000H
000H*
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
-xxx xxxx
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
WDTS
0000 0111
0000 0111
0000 0111
0000 0111
uuuu uuuu
STATUS
--00 xxxx
--1u uuuu
--uu uuuu
--00 uuuu
--11 uuuu
INTC
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
TMR
xxxx xxxx
0000 0000
0000 0000
0000 0000
uuuu uuuu
TMRC
00-0 1---
00-0 1---
00-0 1---
00-0 1---
uu-u u---
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PB
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
Program
Counter
PBC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PCC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PD
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PDC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PE
---1 1111
---1 1111
---1 1111
---1 1111
---u uuuu
PEC
---1 1111
---1 1111
---1 1111
---1 1111
---u uuuu
Note:
²*² stands for warm reset
²u² stands for unchanged
²x² stands for unknown
S y s te m
C lo c k /4
T M 1
T M 0
T O N
D a ta B u s
T M 1
T M 0
T im e r C o u n te r
P r e lo a d R e g is te r
T im e r
C o u n te r
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
R e lo a d
O v e r flo w
to In te rru p t
Timer Counter
Rev. 1.40
13
February 1, 2011
HT82K68E-L/HT82K68A-L
write ²1². The pull-high resistance will exhibit automatically
if the pull-high option is selected. The input source(s) also
depend(s) on the control register. If the control register bit
is ²1², input will read the pad state. If the control register bit
is ²0², the contents of the latches will move to the internal
bus. The latter is possible in ²read-modify-write² instruction. For output function, CMOS is the only configuration.
These control registers are mapped to locations 13H, 15H,
17H, 19H and 1BH.
In the timer mode, once the timer counter starts counting, it will count from the current contents in the timer
counter to FFH. Once overflow occurs, the counter is reloaded from the timer counter preload register and generates the interrupt request flag (TF; bit 5 of INTC) at the
same time.
To enable the counting operation, the timer ON bit
(TON; bit 4 of TMRC) should be set to 1. In the case of
timer counter OFF condition, writing data to the timer
counter preload register will also reload that data to the
timer counter. But if the timer counter is turned on,
data written to it will only be kept in the timer counter
preload register. The timer counter will still operate until
overflow occurs. When the timer counter (reading TMR)
is read, the clock will be blocked to avoid errors. As
clock blocking may results in a counting error, this must
be taken into consideration by the programmer.
After a chip reset, these input/output lines stay at high
levels or floating (mask option). Each bit of these input/output latches can be set or cleared by the SET [m].i
or CLR [m].i (m=12H, 14H, 16H, 18H or 1AH) instruction.
Some instructions first input data and then follow the
output operations. For example, the SET [m].i, CLR
[m].i, CPL [m] and CPLA [m] instructions read the entire
port states into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
Input/Output Ports
There are 34 bidirectional input/output lines in the
microcontroller, labeled from PA to PE, which are
mapped to the data memory of [12H], [14H], [16H],
[18H] and [1AH] respectively. All these I/O ports can be
used for input and output operations. For input
operation, these ports are non-latching, that is, the
inputs must be ready at the T2 rising edge of instruction
MOV A,[m] (m=12H, 14H, 16H, 18H or 1AH). For output
operation, all data is latched and remains unchanged
until the output latch is rewritten.
Each line of port A and port C [0:3] has the capability to
wake-up the device.
PC2 is shared with the external interrupt pin, PE2~PE4
is defined as CMOS output pins only. PE0 can determine whether the high to low transition, or the low to
high transition of PC2 to activate the external subroutine, when PE0 output high, the low to high transition of
PC2 to trigger the external subroutine, when PE0 output
low, the high to low transition of PC2 to trigger the external subroutine.
Each I/O line has its own control register (PAC, PBC,
PCC, PDC, PEC) to control the input/output configuration. With this control register, CMOS output or Schmitt
trigger input with or without pull-high resistor (mask option) structures can be reconfigured dynamically (i.e.,
on-the-fly) under software control. To function as an
input, the corresponding latch of the control register must
PE2~PE4 is configured as CMOS output only and is
used to drive the LED. PC0, PC1 is configured as
NMOS open drain output with 4.6kW pull-high resistor
such that it can easy to use as DATA or CLOCK line of
PS2 keyboard application.
V
D a ta B u s
D
W r ite C o n tr o l R e g is te r
Q
C K
Q
S
V
C h ip R e s e t
P A 0
P B 0
P C 0
P D 0
P E 0
Q
D
C K
S
Q
M
R e a d I/O
S y s te m W a k e -u p
( P A & P C 0 ~ P C 3 o n ly )
W e a k
P u ll- u p
M a s k O p tio n
R e a d C o n tr o l R e g is te r
W r ite I/O
D D
D D
U
~ P A
~ P B
~ P C
~ P D
~ P E
7
4
7
7
7
X
M a s k O p tio n
Input/Output Ports
Rev. 1.40
14
February 1, 2011
HT82K68E-L/HT82K68A-L
Low Voltage Reset - LVR
The relationship between VDD and VLVR is shown below.
The microcontroller provides low voltage reset circuit in
order to monitor the supply voltage of the device. If the
supply voltage of the device is within the range
0.9V~VLVR such as changing a battery, the LVR will automatically reset the device internally.
V D D
5 .5 V
V
O P R
5 .5 V
The LVR includes the following specifications:
V
2 .0 V
· The low voltage (0.9V~VLVR) has to remain in their
L V R
2 .0 V
original state to exceed 1ms. If the low voltage state
does not exceed 1ms, the LVR will ignore it and do not
perform a reset function.
· The LVR uses the ²OR² function with the external
0 .9 V
RES signal to perform chip reset.
The relationship between VDD and VLVR is shown
below.
V
VOPR is the voltage range for proper chip
operation at 4MHz system clock.
Note:
D D
5 .5 V
V
L V R
L V R
D e te c t V o lta g e
0 .9 V
0 V
R e s e t S ig n a l
R e s e t
N o r m a l O p e r a tio n
*1
R e s e t
*2
Low Voltage Reset
Note:
*1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system
clock pulses before entering the normal operation.
*2: Since low voltage has to be maintained in its original state and exceed 1ms, therefore 1ms delay enters the
reset mode.
Rev. 1.40
15
February 1, 2011
HT82K68E-L/HT82K68A-L
ROM Code Option
The following shows six kinds of ROM code option in the device. All the ROM code options must be defined to ensure
proper system function.
No.
ROM Code Option
1
OSC type selection. This option is to decide if an RC or Crystal oscillator is chosen as system clock. If the
Crystal oscillator is selected, the XST (Crystal Start-up Timer) default is activated, otherwise the XST is
disabled.
2
WDT source selection. There are three types of selection: on-chip RC oscillator, instruction clock or disable
the WDT.
3
CLRWDT times selection. This option defines the way to clear the WDT by instruction. ²One time² means
that the CLR WDT instruction can clear the WDT. ²Two times² means only if both of the CLR WDT1 and CLR
WDT2 instructions have been executed, only then will the WDT be cleared.
4
Wake-up selection. This option defines the wake-up function activity. External I/O pins (PA and PC [0:3] only)
all have the capability to wake-up the chip from a HALT.
5
Pull-high selection. This option is to decide whether the pull-high resistance is visible or not in the input mode
of the I/O ports. Each bit of an I/O port can be independently selected.
6
LVR enable/disable. User can configure whether enable or disable the circuit by configuration option.
7
The Input type only Schmitt Trigger input type can used for HT82K68E-L.
The Input type Schmitt Trigger input or inverter input type can used for HT82K68A-L.
Application Circuits
RC Oscillator for Multiple I/O Applications
V
D D
F .B .
0 .1 m F
1 0 m .
V
V D D
D D
4 0 k W
fS Y S /4
(N M O S O p e n
D r a in O u tp u t)
V
O S C 1
O S C 2
D D
4 7 k W
IN 4 1 4 8
R E S E T
0 .1 m F
V
D D
C A P
N U M
S C R
C L K
D A T A
C L K
D A T A
Crystal Oscillator or Ceramic Resonator for
Multiple I/O Applications
V
P A
P A
P A
P A
P A
P A
P A
P A
P B
P B
P B
P B
P B
P B
P B
P B
P D
P D
P D
P D
P D
P D
P D
P D
P C
P C
C 0
0
2
C 2
4
C 4
6
C 6
5
C 5
7
C 7
1
R 1
3
R 3
5
R 5
O S C 1
R 0
0
2
R 2
4
R 4
6
R 6
V
0
R 8
2
R 1 0
R 1 1
R 1 2
R 1 3
R 1 4
R 1 5
R 1 6
R 1 7
D D
4 7 k W
IN 4 1 4 8
R E S E T
R 7
7
V D D
O S C 2
0 .1 m F
R 9
7
6
7
6
5
4
3
1
V
D D
C A P
N U M
S C R
C L K
D A T A
H T 8 2 K 6 8 E -L /H T 8 2 K 6 8 A -L
Rev. 1.40
0 .1 m F
R e s e rv e fo r
R e s o n a to r
C 3
3
F .B .
1 0 m F
C 1
1
D D
C L K
D A T A
P A
P A
P A
P A
P A
P A
P A
P A
P B
P B
P B
P B
P B
P B
P B
P B
P D
P D
P D
P D
P D
P D
P D
P D
P C
P C
C 0
0
1
C 1
3
C 3
5
C 5
7
C 7
1
R 1
3
R 3
5
R 5
2
C 2
4
C 4
6
C 6
0
R 0
2
R 2
4
R 4
6
R 6
R 7
7
0
R 8
2
R 1 0
R 1 1
R 1 2
R 1 3
R 1 4
R 1 5
R 1 6
R 1 7
R 9
7
6
7
6
5
4
3
1
H T 8 2 K 6 8 E -L /H T 8 2 K 6 8 A -L
16
February 1, 2011
HT82K68E-L/HT82K68A-L
Instruction Set
subtract instruction mnemonics to enable the necessary
arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for
subtraction. The increment and decrement instructions
INC, INCA, DEC and DECA provide a simple means of
increasing or decreasing by a value of one of the values
in the destination specified.
Introduction
C e n t ra l t o t he s uc c es s f ul oper a t i on o f a n y
microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to
perform certain operations. In the case of Holtek
microcontrollers, a comprehensive and flexible set of
over 60 instructions is provided to enable programmers
to implement their application with the minimum of programming overheads.
Logical and Rotate Operations
For easier understanding of the various instruction
codes, they have been subdivided into several functional groupings.
The standard logical operations such as AND, OR, XOR
and CPL all have their own instruction within the Holtek
microcontroller instruction set. As with the case of most
instructions involving data manipulation, data must pass
through the Accumulator which may involve additional
programming steps. In all logical data operations, the
zero flag may be set if the result of the operation is zero.
Another form of logical data manipulation comes from
the rotate instructions such as RR, RL, RRC and RLC
which provide a simple means of rotating one bit right or
left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for
serial port programming applications where data can be
rotated from an internal register into the Carry bit from
where it can be examined and the necessary serial bit
set high or low. Another application where rotate data
operations are used is to implement multiplication and
division calculations.
Instruction Timing
Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are
required. One instruction cycle is equal to 4 system
clock cycles, therefore in the case of an 8MHz system
oscillator, most instructions would be implemented
within 0.5ms and branch or call instructions would be implemented within 1ms. Although instructions which require one more cycle to implement are generally limited
to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions
which involve manipulation of the Program Counter Low
register or PCL will also take one more cycle to implement. As instructions which change the contents of the
PCL will imply a direct jump to that new address, one
more cycle will be required. Examples of such instructions would be ²CLR PCL² or ²MOV PCL, A². For the
case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then
this will also take one more cycle, if no skip is involved
then only one cycle is required.
Branches and Control Transfer
Program branching takes the form of either jumps to
specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the
sense that in the case of a subroutine call, the program
must return to the instruction immediately when the subroutine has been carried out. This is done by placing a
return instruction RET in the subroutine which will cause
the program to jump back to the address right after the
CALL instruction. In the case of a JMP instruction, the
program simply jumps to the desired location. There is
no requirement to jump back to the original jumping off
point as in the case of the CALL instruction. One special
and extremely useful set of branch instructions are the
conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program
will continue with the next instruction or skip over it and
jump to the following instruction. These instructions are
the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits.
Moving and Transferring Data
The transfer of data within the microcontroller program
is one of the most frequently used operations. Making
use of three kinds of MOV instructions, data can be
transferred from registers to the Accumulator and
vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most
important data transfer applications is to receive data
from the input ports and transfer data to the output ports.
Arithmetic Operations
The ability to perform certain arithmetic operations and
data manipulation is a necessary feature of most
microcontroller applications. Within the Holtek
microcontroller instruction set are a range of add and
Rev. 1.40
17
February 1, 2011
HT82K68E-L/HT82K68A-L
Bit Operations
Other Operations
The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek
microcontrollers. This feature is especially useful for
output port bit programming where individual bits or port
pins can be directly set high or low using either the ²SET
[m].i² or ²CLR [m].i² instructions respectively. The feature removes the need for programmers to first read the
8-bit output port, manipulate the input data to ensure
that other bits are not changed and then output the port
with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used.
In addition to the above functional instructions, a range
of other instructions also exist such as the ²HALT² instruction for Power-down operations and instructions to
control the operation of the Watchdog Timer for reliable
program operations under extreme electric or electromagnetic environments. For their relevant operations,
refer to the functional related sections.
Instruction Set Summary
The following table depicts a summary of the instruction
set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions.
Table Read Operations
Table conventions:
Data storage is normally implemented by using registers. However, when working with large amounts of
fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an
area of Program Memory to be setup as a table where
data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be
referenced and retrieved from the Program Memory.
Mnemonic
x: Bits immediate data
m: Data Memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Description
Cycles
Flag Affected
1
1Note
1
1
1Note
1
1
1Note
1
1Note
1Note
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
C
1
1
1
1Note
1Note
1Note
1
1
1
1Note
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
1
1Note
1
1Note
Z
Z
Z
Z
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Add Data Memory to ACC
Add ACC to Data Memory
Add immediate data to ACC
Add Data Memory to ACC with Carry
Add ACC to Data memory with Carry
Subtract immediate data from the ACC
Subtract Data Memory from ACC
Subtract Data Memory from ACC with result in Data Memory
Subtract Data Memory from ACC with Carry
Subtract Data Memory from ACC with Carry, result in Data Memory
Decimal adjust ACC for Addition with result in Data Memory
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
Logical AND Data Memory to ACC
Logical OR Data Memory to ACC
Logical XOR Data Memory to ACC
Logical AND ACC to Data Memory
Logical OR ACC to Data Memory
Logical XOR ACC to Data Memory
Logical AND immediate Data to ACC
Logical OR immediate Data to ACC
Logical XOR immediate Data to ACC
Complement Data Memory
Complement Data Memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rev. 1.40
Increment Data Memory with result in ACC
Increment Data Memory
Decrement Data Memory with result in ACC
Decrement Data Memory
18
February 1, 2011
HT82K68E-L/HT82K68A-L
Mnemonic
Description
Cycles
Flag Affected
Rotate Data Memory right with result in ACC
Rotate Data Memory right
Rotate Data Memory right through Carry with result in ACC
Rotate Data Memory right through Carry
Rotate Data Memory left with result in ACC
Rotate Data Memory left
Rotate Data Memory left through Carry with result in ACC
Rotate Data Memory left through Carry
1
1Note
1
1Note
1
1Note
1
1Note
None
None
C
C
None
None
C
C
Move Data Memory to ACC
Move ACC to Data Memory
Move immediate data to ACC
1
1Note
1
None
None
None
Clear bit of Data Memory
Set bit of Data Memory
1Note
1Note
None
None
Jump unconditionally
Skip if Data Memory is zero
Skip if Data Memory is zero with data movement to ACC
Skip if bit i of Data Memory is zero
Skip if bit i of Data Memory is not zero
Skip if increment Data Memory is zero
Skip if decrement Data Memory is zero
Skip if increment Data Memory is zero with result in ACC
Skip if decrement Data Memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1Note
1note
1Note
1Note
1Note
1Note
1Note
1Note
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read table (current page) to TBLH and Data Memory
Read table (last page) to TBLH and Data Memory
2Note
2Note
None
None
No operation
Clear Data Memory
Set Data Memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of Data Memory
Swap nibbles of Data Memory with result in ACC
Enter power down mode
1
1Note
1Note
1
1
1
1Note
1
1
None
None
None
TO, PDF
TO, PDF
TO, PDF
None
None
TO, PDF
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note:
1. For skip instructions, if the result of the comparison involves a skip then two cycles are required,
if no skip takes place only one cycle is required.
2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.
3. For the ²CLR WDT1² and ²CLR WDT2² instructions the TO and PDF flags may be affected by
the execution status. The TO and PDF flags are cleared after both ²CLR WDT1² and
²CLR WDT2² instructions are consecutively executed. Otherwise the TO and PDF flags
remain unchanged.
Rev. 1.40
19
February 1, 2011
HT82K68E-L/HT82K68A-L
Instruction Definition
ADC A,[m]
Add Data Memory to ACC with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the Accumulator.
Operation
ACC ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADCM A,[m]
Add ACC to Data Memory with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADD A,[m]
Add Data Memory to ACC
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
ADD A,x
Add immediate data to ACC
Description
The contents of the Accumulator and the specified immediate data are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + x
Affected flag(s)
OV, Z, AC, C
ADDM A,[m]
Add ACC to Data Memory
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
AND A,[m]
Logical AND Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
Z
AND A,x
Logical AND immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical AND
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
Z
ANDM A,[m]
Logical AND ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
Z
Rev. 1.40
20
February 1, 2011
HT82K68E-L/HT82K68A-L
CALL addr
Subroutine call
Description
Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the
stack. The specified address is then loaded and the program continues execution from this
new address. As this instruction requires an additional operation, it is a two cycle instruction.
Operation
Stack ¬ Program Counter + 1
Program Counter ¬ addr
Affected flag(s)
None
CLR [m]
Clear Data Memory
Description
Each bit of the specified Data Memory is cleared to 0.
Operation
[m] ¬ 00H
Affected flag(s)
None
CLR [m].i
Clear bit of Data Memory
Description
Bit i of the specified Data Memory is cleared to 0.
Operation
[m].i ¬ 0
Affected flag(s)
None
CLR WDT
Clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT1
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT2
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
Rev. 1.40
21
February 1, 2011
HT82K68E-L/HT82K68A-L
CPL [m]
Complement Data Memory
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa.
Operation
[m] ¬ [m]
Affected flag(s)
Z
CPLA [m]
Complement Data Memory with result in ACC
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa. The complemented result
is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
Z
DAA [m]
Decimal-Adjust ACC for addition with result in Data Memory
Description
Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or
if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble
remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of
6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C
flag may be affected by this instruction which indicates that if the original BCD sum is
greater than 100, it allows multiple precision decimal addition.
Operation
[m] ¬ ACC + 00H or
[m] ¬ ACC + 06H or
[m] ¬ ACC + 60H or
[m] ¬ ACC + 66H
Affected flag(s)
C
DEC [m]
Decrement Data Memory
Description
Data in the specified Data Memory is decremented by 1.
Operation
[m] ¬ [m] - 1
Affected flag(s)
Z
DECA [m]
Decrement Data Memory with result in ACC
Description
Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] - 1
Affected flag(s)
Z
HALT
Enter power down mode
Description
This instruction stops the program execution and turns off the system clock. The contents
of the Data Memory and registers are retained. The WDT and prescaler are cleared. The
power down flag PDF is set and the WDT time-out flag TO is cleared.
Operation
TO ¬ 0
PDF ¬ 1
Affected flag(s)
TO, PDF
Rev. 1.40
22
February 1, 2011
HT82K68E-L/HT82K68A-L
INC [m]
Increment Data Memory
Description
Data in the specified Data Memory is incremented by 1.
Operation
[m] ¬ [m] + 1
Affected flag(s)
Z
INCA [m]
Increment Data Memory with result in ACC
Description
Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] + 1
Affected flag(s)
Z
JMP addr
Jump unconditionally
Description
The contents of the Program Counter are replaced with the specified address. Program
execution then continues from this new address. As this requires the insertion of a dummy
instruction while the new address is loaded, it is a two cycle instruction.
Operation
Program Counter ¬ addr
Affected flag(s)
None
MOV A,[m]
Move Data Memory to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
None
MOV A,x
Move immediate data to ACC
Description
The immediate data specified is loaded into the Accumulator.
Operation
ACC ¬ x
Affected flag(s)
None
MOV [m],A
Move ACC to Data Memory
Description
The contents of the Accumulator are copied to the specified Data Memory.
Operation
[m] ¬ ACC
Affected flag(s)
None
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
No operation
Affected flag(s)
None
OR A,[m]
Logical OR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
Z
Rev. 1.40
23
February 1, 2011
HT82K68E-L/HT82K68A-L
OR A,x
Logical OR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
Z
ORM A,[m]
Logical OR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²OR² [m]
Affected flag(s)
Z
RET
Return from subroutine
Description
The Program Counter is restored from the stack. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
Affected flag(s)
None
RET A,x
Return from subroutine and load immediate data to ACC
Description
The Program Counter is restored from the stack and the Accumulator loaded with the
specified immediate data. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
None
RETI
Return from interrupt
Description
The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending
when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program.
Operation
Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
None
RL [m]
Rotate Data Memory left
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ [m].7
Affected flag(s)
None
RLA [m]
Rotate Data Memory left with result in ACC
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ [m].7
Affected flag(s)
None
Rev. 1.40
24
February 1, 2011
HT82K68E-L/HT82K68A-L
RLC [m]
Rotate Data Memory left through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7
replaces the Carry bit and the original carry flag is rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RLCA [m]
Rotate Data Memory left through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces
the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in
the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RR [m]
Rotate Data Memory right
Description
The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into
bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ [m].0
Affected flag(s)
None
RRA [m]
Rotate Data Memory right with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data
Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ [m].0
Affected flag(s)
None
RRC [m]
Rotate Data Memory right through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0
replaces the Carry bit and the original carry flag is rotated into bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
C
RRCA [m]
Rotate Data Memory right through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is
stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
C
Rev. 1.40
25
February 1, 2011
HT82K68E-L/HT82K68A-L
SBC A,[m]
Subtract Data Memory from ACC with Carry
Description
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result
of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or
zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SBCM A,[m]
Subtract Data Memory from ACC with Carry and result in Data Memory
Description
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is
positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SDZ [m]
Skip if decrement Data Memory is 0
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0 the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] - 1
Skip if [m] = 0
Affected flag(s)
None
SDZA [m]
Skip if decrement Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0, the program proceeds with the following instruction.
Operation
ACC ¬ [m] - 1
Skip if ACC = 0
Affected flag(s)
None
SET [m]
Set Data Memory
Description
Each bit of the specified Data Memory is set to 1.
Operation
[m] ¬ FFH
Affected flag(s)
None
SET [m].i
Set bit of Data Memory
Description
Bit i of the specified Data Memory is set to 1.
Operation
[m].i ¬ 1
Affected flag(s)
None
Rev. 1.40
26
February 1, 2011
HT82K68E-L/HT82K68A-L
SIZ [m]
Skip if increment Data Memory is 0
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] + 1
Skip if [m] = 0
Affected flag(s)
None
SIZA [m]
Skip if increment Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0 the program proceeds with the following instruction.
Operation
ACC ¬ [m] + 1
Skip if ACC = 0
Affected flag(s)
None
SNZ [m].i
Skip if bit i of Data Memory is not 0
Description
If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is 0 the program proceeds with the following instruction.
Operation
Skip if [m].i ¹ 0
Affected flag(s)
None
SUB A,[m]
Subtract Data Memory from ACC
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUBM A,[m]
Subtract Data Memory from ACC with result in Data Memory
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUB A,x
Subtract immediate data from ACC
Description
The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will
be set to 1.
Operation
ACC ¬ ACC - x
Affected flag(s)
OV, Z, AC, C
Rev. 1.40
27
February 1, 2011
HT82K68E-L/HT82K68A-L
SWAP [m]
Swap nibbles of Data Memory
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged.
Operation
[m].3~[m].0 « [m].7 ~ [m].4
Affected flag(s)
None
SWAPA [m]
Swap nibbles of Data Memory with result in ACC
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged. The
result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC.3 ~ ACC.0 ¬ [m].7 ~ [m].4
ACC.7 ~ ACC.4 ¬ [m].3 ~ [m].0
Affected flag(s)
None
SZ [m]
Skip if Data Memory is 0
Description
If the contents of the specified Data Memory is 0, the following instruction is skipped. As
this requires the insertion of a dummy instruction while the next instruction is fetched, it is a
two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
Operation
Skip if [m] = 0
Affected flag(s)
None
SZA [m]
Skip if Data Memory is 0 with data movement to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator. If the value is
zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the
program proceeds with the following instruction.
Operation
ACC ¬ [m]
Skip if [m] = 0
Affected flag(s)
None
SZ [m].i
Skip if bit i of Data Memory is 0
Description
If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is not 0, the program proceeds with the following instruction.
Operation
Skip if [m].i = 0
Affected flag(s)
None
TABRDC [m]
Read table (current page) to TBLH and Data Memory
Description
The low byte of the program code (current page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
TABRDL [m]
Read table (last page) to TBLH and Data Memory
Description
The low byte of the program code (last page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
Rev. 1.40
28
February 1, 2011
HT82K68E-L/HT82K68A-L
XOR A,[m]
Logical XOR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XORM A,[m]
Logical XOR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XOR A,x
Logical XOR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical XOR
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Z
Rev. 1.40
29
February 1, 2011
HT82K68E-L/HT82K68A-L
Package Information
20-pin SOP (300mil) Outline Dimensions
1 1
2 0
A
B
1
1 0
C
C '
G
H
D
E
a
F
· MS-013
Symbol
A
Nom.
Max.
0.393
¾
0.419
B
0.256
¾
0.300
C
0.012
¾
0.020
C¢
0.496
¾
0.512
D
¾
¾
0.104
E
¾
0.050
¾
F
0.004
¾
0.012
G
0.016
¾
0.050
H
0.008
¾
0.013
a
0°
¾
8°
Symbol
A
Rev. 1.40
Dimensions in inch
Min.
Dimensions in mm
Min.
Nom.
Max.
9.98
¾
10.64
B
6.50
¾
7.62
C
0.30
¾
0.51
C¢
12.60
¾
13.00
D
¾
¾
2.64
E
¾
1.27
¾
F
0.10
¾
0.30
G
0.41
¾
1.27
H
0.20
¾
0.33
a
0°
¾
8°
30
February 1, 2011
HT82K68E-L/HT82K68A-L
28-pin SOP (300mil) Outline Dimensions
2 8
1 5
A
B
1
1 4
C
C '
G
H
D
E
a
F
· MS-013
Symbol
Nom.
Max.
A
0.393
¾
0.419
B
0.256
¾
0.300
C
0.012
¾
0.020
C¢
0.697
¾
0.713
D
¾
¾
0.104
E
¾
0.050
¾
F
0.004
¾
0.012
G
0.016
¾
0.050
H
0.008
¾
0.013
a
0°
¾
8°
Symbol
Rev. 1.40
Dimensions in inch
Min.
Dimensions in mm
Min.
Nom.
Max.
A
9.98
¾
10.64
B
6.50
¾
7.62
C
0.30
¾
0.51
C¢
17.70
¾
18.11
D
¾
¾
2.64
E
¾
1.27
¾
F
0.10
¾
0.30
G
0.41
¾
1.27
H
0.20
¾
0.33
a
0°
¾
8°
31
February 1, 2011
HT82K68E-L/HT82K68A-L
SAW Type 32-pin (5mm´5mm) QFN Outline Dimensions
D
D 2
2 5
3 2
2 4
b
1
E
E 2
e
1 7
8
1 6
A 1
A 3
L
9
K
A
Symbol
Nom.
Max.
A
0.028
¾
0.031
A1
0.000
¾
0.002
A3
¾
0.008
¾
b
0.007
¾
0.012
D
¾
0.197
¾
E
¾
0.197
¾
e
¾
0.020
¾
D2
0.049
¾
0.128
E2
0.049
¾
0.128
L
0.012
¾
0.020
K
¾
¾
¾
Symbol
Rev. 1.40
Dimensions in inch
Min.
Dimensions in mm
Min.
Nom.
Max.
A
0.70
¾
0.80
A1
0.00
¾
0.05
A3
¾
0.20
¾
b
0.18
¾
0.30
D
¾
5.00
¾
E
¾
5.00
¾
e
¾
0.50
¾
D2
1.25
¾
3.25
E2
1.25
¾
3.25
L
0.30
¾
0.50
K
¾
¾
¾
32
February 1, 2011
HT82K68E-L/HT82K68A-L
48-pin SSOP (300mil) Outline Dimensions
4 8
2 5
A
B
1
2 4
C
C '
G
H
D
E
Symbol
F
Dimensions in inch
Min.
Nom.
Max.
A
0.350
¾
0.358
B
0.272
¾
0.280
C
0.350
¾
0.358
D
0.272
¾
0.280
E
¾
0.020
¾
F
¾
0.008
¾
G
0.053
¾
0.057
H
¾
¾
0.063
I
¾
0.004
¾
J
0.018
¾
0.030
K
0.004
¾
0.008
a
0°
¾
7°
Symbol
A
Rev. 1.40
a
Dimensions in mm
Min.
Nom.
Max.
8.90
¾
9.10
B
6.90
¾
7.10
C
8.90
¾
9.10
D
6.90
¾
7.10
E
¾
0.50
¾
F
¾
0.20
¾
G
1.35
¾
1.45
H
¾
¾
1.60
I
¾
0.10
¾
J
0.45
¾
0.75
K
0.10
¾
0.20
a
0°
¾
7°
33
February 1, 2011
HT82K68E-L/HT82K68A-L
48-pin LQFP (7mm´7mm) Outline Dimensions
C
H
D
3 6
G
2 5
I
3 7
2 4
F
A
B
E
4 8
1 3
K
a
J
1
Symbol
Dimensions in inch
Min.
Nom.
Max.
A
0.350
¾
0.358
B
0.272
¾
0.280
C
0.350
¾
0.358
D
0.272
¾
0.280
E
¾
0.020
¾
F
¾
0.008
¾
G
0.053
¾
0.057
H
¾
¾
0.063
I
¾
0.004
¾
J
0.018
¾
0.030
K
0.004
¾
0.008
a
0°
¾
7°
Symbol
A
Rev. 1.40
1 2
Dimensions in mm
Min.
Nom.
Max.
8.90
¾
9.10
B
6.90
¾
7.10
C
8.90
¾
9.10
D
6.90
¾
7.10
E
¾
0.50
¾
F
¾
0.20
¾
G
1.35
¾
1.45
H
¾
¾
1.60
I
¾
0.10
¾
J
0.45
¾
0.75
K
0.10
¾
0.20
a
0°
¾
7°
34
February 1, 2011
HT82K68E-L/HT82K68A-L
Product Tape and Reel Specifications
Reel Dimensions
D
T 2
A
C
B
T 1
SOP 20W
Symbol
Description
Dimensions in mm
A
Reel Outer Diameter
330.0±1.0
B
Reel Inner Diameter
100.0±1.5
C
Spindle Hole Diameter
D
Key Slit Width
T1
Space Between Flange
T2
Reel Thickness
13.0
+0.5/-0.2
2.0±0.5
24.8
+0.3/-0.2
30.2±0.2
SOP 28W (300mil)
Symbol
Description
Dimensions in mm
A
Reel Outer Diameter
330.0±1.0
B
Reel Inner Diameter
100.0±1.5
C
Spindle Hole Diameter
D
Key Slit Width
T1
Space Between Flange
T2
Reel Thickness
Rev. 1.40
13.0
+0.5/-0.2
2.0±0.5
24.8
+0.3/-0.2
30.2±0.2
35
February 1, 2011
HT82K68E-L/HT82K68A-L
SAW Type QFN 32-pin (5mm´5mm)
Symbol
Description
Dimensions in mm
A
Reel Outer Diameter
330.0±1.0
B
Reel Inner Diameter
100.0±0.1
C
Spindle Hole Diameter
D
Key Slit Width
13.0
+0.5/-0.2
2.0±0.5
T1
Space Between Flange
T2
Reel Thickness
12.5
+0.3/-0.2
¾
SSOP 48W
Symbol
Description
A
Reel Outer Diameter
B
Reel Inner Diameter
C
Spindle Hole Diameter
D
Key Slit Width
T1
Space Between Flange
T2
Reel Thickness
Rev. 1.40
Dimensions in mm
330.0±1.0
100.0±0.1
13.0
+0.5/-0.2
2.0±0.5
32.2
+0.3/-0.2
38.2±0.2
36
February 1, 2011
HT82K68E-L/HT82K68A-L
Carrier Tape Dimensions
P 0
D
P 1
t
E
F
W
C
D 1
B 0
P
K 0
A 0
R e e l H o le
IC
p a c k a g e p in 1 a n d th e r e e l h o le s
a r e lo c a te d o n th e s a m e s id e .
SOP 20W
Symbol
Description
Dimensions in mm
24.0
+0.3/-0.1
W
Carrier Tape Width
P
Cavity Pitch
12.0±0.1
E
Perforation Position
1.75±0.10
F
Cavity to Perforation (Width Direction)
11.5±0.1
D
Perforation Diameter
1.5
1.50
+0.1/-0.0
+0.25/-0.00
D1
Cavity Hole Diameter
P0
Perforation Pitch
P1
Cavity to Perforation (Length Direction)
2.0±0.1
A0
Cavity Length
10.8±0.1
B0
Cavity Width
13.3±0.1
K0
Cavity Depth
3.2±0.1
4.0±0.1
t
Carrier Tape Thickness
0.30±0.05
C
Cover Tape Width
21.3±0.1
SOP 28W (300mil)
Symbol
Description
Dimensions in mm
W
Carrier Tape Width
24.0±0.3
P
Cavity Pitch
12.0±0.1
E
Perforation Position
1.75±0.10
F
Cavity to Perforation (Width Direction)
D
Perforation Diameter
11.5±0.1
1.5
1.50
+0.1/-0.0
+0.25/-0.00
D1
Cavity Hole Diameter
P0
Perforation Pitch
4.0±0.1
P1
Cavity to Perforation (Length Direction)
2.0±0.1
A0
Cavity Length
10.85±0.10
B0
Cavity Width
18.34±0.10
K0
Cavity Depth
2.97±0.10
t
Carrier Tape Thickness
0.35±0.01
C
Cover Tape Width
21.3±0.1
Rev. 1.40
37
February 1, 2011
HT82K68E-L/HT82K68A-L
P 0
D
P 1
t
E
F
W
D 1
C
B 0
K 1
P
K 2
A 0
R e e l H o le ( C ir c le )
IC
p a c k a g e p in 1 a n d th e r e e l h o le s
a r e lo c a te d o n th e s a m e s id e .
R e e l H o le ( E llip s e )
SSOP 48W
Symbol
Description
Dimensions in mm
W
Carrier Tape Width
32.0±0.3
P
Cavity Pitch
16.0±0.1
E
Perforation Position
1.75±0.10
F
Cavity to Perforation (Width Direction)
14.2±0.1
D
Perforation Diameter
D1
Cavity Hole Diameter
2 Min.
P0
Perforation Pitch
4.0±0.1
P1
Cavity to Perforation (Length Direction)
2.0±0.1
A0
Cavity Length
12.0±0.1
B0
Cavity Width
16.2±0.1
K1
Cavity Depth
2.4±0.1
K2
Cavity Depth
3.2±0.1
1.50
+0.25/-0.00
t
Carrier Tape Thickness
0.35±0.05
C
Cover Tape Width
25.5±0.1
Rev. 1.40
38
February 1, 2011
HT82K68E-L/HT82K68A-L
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor Inc. (Shenzhen Sales Office)
5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057
Tel: 86-755-8616-9908, 86-755-8616-9308
Fax: 86-755-8616-9722
Holtek Semiconductor (USA), Inc. (North America Sales Office)
46729 Fremont Blvd., Fremont, CA 94538, USA
Tel: 1-510-252-9880
Fax: 1-510-252-9885
http://www.holtek.com
Copyright Ó 2011 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.40
39
February 1, 2011