HOLTEK HTG2190

HTG2190
8-Bit 1024 Pixel Dot Matrix LCD MCU Series
Features
· Operating voltage: 2.4V~3.6V
· R to F function for temperature measurement
· 64K´16 bits program ROM
· Synchronous serial interface
· 2.3K´8 bits data RAM
· On-chip RC oscillator for system clock
· 15~39 bidirectional I/O lines
· 32768Hz crystal oscillator for time base and LCD
driver
· 16 common´40~64 segment LCD driver
· Watchdog Timer
· Two 16-bit programmable timer/event counters with
· HALT function and wake-up feature reduce power
overflow interrupts
consumption
· One 8-bit programmable timer with 8-stage prescaler
· Eight-level subroutine nesting
for PFD
· Bit manipulation instructions
· One 8-bit programmable timer with 8-stage prescaler
· 63 powerful instructions
for time base
· Built-in supply voltage detection circuit
· One 8-bit PWM audio output to directly drive speaker
· One interrupt input
or buzzer
· One 12-bit current type D/A output with 4-bit volume
· 128-pin QFP package
control
General Description
low power applications among which are calculators,
clock timer, game, scales, leisure products, other hand
held LCD products and battery operated systems in particular.
The HTG2190 is an 8-bit high performance RISC-like
microcontroller capable of driving 1024 pixel (max.)
LCD display. Its single cycle instruction and two-stage
pipeline architecture make it suitable for high speed applications. The device is suited for use in multiple LCD
Rev. 1.20
1
July 5, 2002
HTG2190
Block Diagram
S Y S C L K /4
S T A C K 0
IN T /S IN
S T A C K 2
In te r r u p t
C ir c u it
S T A C K 3
P ro g ra m
C o u n te r
S T A C K 4
S T A C K 5
S T A C K 6
P ro g ra m
R O M
IN T C
S T A C K 7
M
T M R 0 C
M P 0
M P 1
U
D A T A
M e m o ry
X
M U X
X
P B 6 /T M R 1
R T F
M
U
1 6 b it
W D T S
P E C
W D T R C
O S C
¸ 2 5 6
W D T P r e s c a le r
In s tr u c tio n
D e c o d e r
P B 7 /T M R 0
1 6 b it
T M R 1
M
X
S Y S C L K /4
T M R 1 C
In s tr u c tio n
R e g is te r
U
T M R 0
S T A C K 1
P O R T E
P E 0 ~ P E 7 /S E G 4 0 ~ S E G 4 7
P E
S T A T U S
A L U
X IN /P C 7 /S E G 6 3
X O U T /P C 6 /S E G 6 2
T im in g
G e n e r a tio n
P D C
S h ifte r
P C C
O S C O
O S
R E
V D
V S
S
A C C
C I
S
D
P O R T D
P D 0 ~ P D 7 /S E G 4 8 ~ S E G 5 5
P D
P B C
L C D
M e m o ry
L C D
P C 0 ~ P C 7 /S E G 5 6 ~ S E G 6 3
P O R T B
P B 0 , P B 2 ~ P B 7
P B
S E G 0
P E 0 ~
P D 0 ~
P C 0 ~
X O U T
X IN /P
S C L K /P B 5
IN T /S IN
S O U T /P B 4
S Y S C L K
P A C
S u p p ly V o lta g e
D e te c tio n
D r iv e r
C O M 0 ~ C O M 1 5
P O R T C
P C
~ 3
P E
P D
P C
/P
C 7
9
7 /S E
7 /S E
5 /S E
C 6 /S
/S E G
G 4
G 4
G 5
E G
6 3
P O R T A
P A 0 ~ P A 7
P A
8 -s ta g e
P r e s c a le r
T M R 2
0 ~ S E G 4 7
8 ~ S E G 5 5
6 ~ S E G 6 1
6 2
S Y S C L K
P W M D A C 1
T M R 2 C
M
P F D
S e r ia l
In te rfa c e
M
P W M D A C 2
8 -s ta g e
P r e s c a le r
S Y S C L K
U
P B 0 /P W M 1
U
X
P W M 2 /A U D
X
8 -s ta g e
P r e s c a le r
3 2 7 6 8 H z C ry s ta l
4 b its
V o lu m e
c o n tro l
S Y S C L K
P W M D A C 1
1 2 b its
D /A
T M R 3
8 -s ta g e
P r e s c a le r
M
U
X
T M R 3 C
P W M
D /A
P W M D A C 2
Rev. 1.20
2
July 5, 2002
HTG2190
Pin Assignment
X IN /P C
X O U T /P C
P C
P C
P C
P C
P C
P C
P D
P D
P D
P D
P D
P D
P D
P D
P E
P E
P E
P E
P E
P E
P E
P E
P
7 S E G
6 S E G
5 /S E G
4 /S E G
3 /S E G
2 /S E G
1 /S E G
0 /S E G
7 /S E G
6 /S E G
5 /S E G
4 /S E G
3 /S E G
2 /S E G
1 /S E G
0 /S E G
7 /S E G
6 /S E G
5 /S E G
4 /S E G
3 /S E G
2 /S E G
1 /S E G
0 /S E G
S E G
S E G
S E G
S E G
N C
A 0
6 3
6 2
6 1
6 0
5 9
5 8
5 7
5 6
5 5
5 4
5 3
5 2
5 1
5 0
4 9
4 8
4 7
4 6
4 5
4 4
4 3
4 2
4 1
4 0
3 9
3 8
3 7
3 6
N C
N C
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S
S
S
S
S
S
G 3
G 3
G 3
G 3
G 3
G 3
G 2
G 2
G 2
G 2
G 2
G 2
G 2
G 2
G 2
G 2
G 1
G 1
G 1
G 1
G 1
G 1
G 1
G 1
G 1
G 1
E G
E G
E G
E G
E G
E G
7
8
9
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
1 2 8 1 2 7 1 2 6 1 2 5 1 2 4 1 2 3 1 2 2 1 2 1 1 2 0 1 1 9 1 1 8 1 1 7 1 1 6 1 1 5 1 1 4 1 1 3 1 1 2 1 1 1 1 1 0 1 0 9 1 0 8 1 0 7 1 0 6 1 0 5 1 0 4 1 0 3 1 0 2 1 0 1 1 0 0 9 9
5
1
9 8
9 7
9 6
2
9 5
3
9 4
4
9 3
5
9 2
6
9 1
7
9 0
8
8 9
9
8 8
1 0
8 7
1 1
8 6
1 2
8 5
1 3
8 4
1 4
8 3
1 5
8 2
H T G 2 1 9 0
1 2 8 Q F P -A
1 6
1 7
1 8
8 1
8 0
7 9
1 9
7 8
2 0
7 7
2 1
7 6
2 2
7 5
2 3
7 4
2 4
7 3
2 5
7 2
2 6
7 1
9
0
1
2
3
4
5
6
2 7
7 0
2 8
6 9
2 9
6 8
3 0
6 7
3 1
4
5
6
7
8
3 2
6 6
3 3 3 4
3 5
3 6
3 8 3 9
3 7
4 0 4 1
4 2
4 3
4 4
4 5
4 6
4 7 4 8
4 9
5 0
5 1
5 2
5 3
5 4
5 5
5 6
5 7 5 8
5 9
6 0
6 1
6 3 6 4
6 2
6 5
N C
P A
P A
P A
P A
P A
P A
P A
P B
P B
P B
P B
P B
P B
P B
A U
R E
IN T
V D
O S
N C
N C
N C
N C
O S
N C
V S
N C
C A
N C
N C
N C
1
2
3
4
5
6
7
2
3
4 /S O
5 /S C
6 /T M
7 /T M
0 /P W
D /P W
S
/S IN
D
C 1
U T
L K
R 1 /R T F
R 0
M 1
M 2
C 0
S
P 1
N C
C A
C A
N C
N C
N C
N C
C A
V O
V O
V O
V O
C O
C O
C O
C O
C O
C O
C O
C O
C O
C O
C O
C O
C O
C O
C O
C O
S E
S E
S E
S E
P 2
P 3
P 4
U T
U T
U T
U T
M 0
M 1
M 2
M 3
M 4
M 5
M 6
M 7
M 8
M 9
M 1
M 1
M 1
M 1
M 1
M 1
G 0
G 1
G 2
G 3
3
3
4 4
3 3
2 2
1 1
0
1
2
4
5
Rev. 1.20
July 5, 2002
HTG2190
Pad Assignment
3
1
4
2
0
9
7
5
3
1
6
8
9
8
6
4
2
0
7
1 0 7
1 0 6
1 0 5
1 0 4
1 0 3
1 0 2
1 0 1
1 0 0
9 9
9 8
9 7
9 6
9 5
9 4
9 3
9 2
9 1
9 0
8 9
8 8
1 8
7 5
1 9
7 4
P A 0
P A 1
P A 2
P A 3
P A 4
P A 5
P A 6
P A 7
P B 2
P B 3
P B 4
P B 5
P B 6
P B 7
7 3
P B 0 /P W M 1
7 2
P W M 2 /A U D
7 1
R E S
7 0
IN T /S IN
2 6
6 9
V D D
2 7
6 8
O S C I
6 5
O S C O
V S S
0
5
1 0 8
4
5
8 7
6
8 6
7
9
6
1 0 9
3
3
7
1 1 0
2
1
8
6 3
6 2
6 1
6 0
5 9
5 8
5 7
5 6
5 5
5 4
5 3
5 2
5 1
5 0
4 9
4 8
4 7
4 6
4 5
4 4
4 3
4 2
4 1
2
5
1 1 1
E G
E G
E G
E G
E G
E G
E G
E G
E G
E G
E G
E G
E G
E G
E G
E G
E G
E G
E G
E G
E G
E G
E G
4
9
8
7
G 3
G 3
G 3
G 3
G 3
G 3
G 2
G 2
G 2
G 2
G 2
G 2
G 2
G 2
G 2
G 2
G 1
G 1
G 1
G 1
G 1
G 1
G 1
G 1
G 1
G 1
E G
E G
E G
E G
1 1 2
7 /S
6 /S
5 /S
4 /S
3 /S
2 /S
1 /S
0 /S
7 /S
6 /S
5 /S
4 /S
3 /S
2 /S
1 /S
0 /S
7 /S
6 /S
5 /S
4 /S
3 /S
2 /S
1 /S
6
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S
S
S
S
1 1 4 1 1 3
X IN /P C
X O U T /P C
P C
P C
P C
P C
P C
P C
P D
P D
P D
P D
P D
P D
P D
P D
P E
P E
P E
P E
P E
P E
P E
G 3
G 3
G 3
G 3
P E 0 /S E G 4 0
S E
S E
S E
S E
1
8 5
8
8 4
9
8 3
1 0
8 2
1 1
8 1
1 2
8 0
1 3
7 9
1 4
7 8
1 5
(0 , 0 )
1 6
7 7
7 6
1 7
2 0
2 1
2 2
2 3
2 4
2 5
T R IM 4 6 7
T R IM 3 6 6
T R IM 1 5 9 6 3
T R IM 2
2 8
2 9
3 0
3 1
3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4
4 5 4 6 4 7
4 8 4 9 5 0 5 1
5 2 5 3
5 4
5 5
5 6
5 8
5 7
6 0
6 4
6 1
/S O
/S C
/T M
/T M
U T
L K
R 1 /R T F
R 0
6 2
P 2
P 3
P 4
U T
U T
U T
U T
M 0
M 1
M 2
M 3
M 4
M 5
M 6
M 7
M 8
M 9
M 1
M 1
M 1
M 1
M 1
M 1
G 0
G 1
G 2
G 3
G 4
G 5
C A P 1
C A
C A
C A
V O
V O
V O
V O
C O
C O
C O
C O
C O
C O
C O
C O
C O
C O
C O
C O
C O
C O
C O
C O
S E
S E
S E
S E
S E
S E
4 4
3 3
2 2
1 1
0
1
2
3
4
5
Chip size: 3420 ´ 3855 (mm)2
* The IC substrate should be connected to VSS in the PCB layout artwork.
Pad Coordinates
Unit: mm
Pad No.
X
Y
Pad No.
X
Y
1
-1561.08
1781.81
58
1214.37
-1797.56
2
-1577.85
1535.18
59
1156.72
-1465.33
3
-1577.85
1428.50
60
1331.47
-1797.56
4
-1577.85
1322.07
61
1442.47
-1797.56
5
-1577.85
1215.39
62
1559.56
-1797.56
6
-1577.85
1108.96
63
1264.67
-1465.33
7
-1577.85
1002.28
64
1492.25
-1516.38
8
-1577.85
895.86
65
1492.25
-1404.62
Rev. 1.20
4
July 5, 2002
HTG2190
Pad No.
X
Y
Pad No.
X
Y
9
-1577.85
789.18
66
1264.67
-1351.53
10
-1577.85
682.75
67
1240.28
-1235.20
11
-1577.85
576.33
68
1492.25
-1119.38
12
-1577.85
469.65
69
1515.36
-991.36
13
-1577.85
363.22
70
1517.14
-867.16
14
-1577.85
256.54
71
1517.14
-745.49
15
-1577.85
150.11
72
1517.14
-596.65
16
-1577.85
43.43
73
1517.14
-422.91
17
-1577.85
-62.99
74
1517.14
-271.27
18
-1577.85
-169.67
75
1517.14
-154.18
19
-1577.85
-276.10
76
1517.14
20
-1577.85
-382.78
77
1517.14
-40.13
76.45
21
-1577.85
-489.20
78
1517.14
190.50
22
-1577.85
-595.88
79
1517.14
307.34
23
-1577.85
-702.31
80
1517.14
421.39
24
-1577.85
-809.99
81
1517.14
538.23
25
-1577.85
-915.42
82
1517.14
652.27
26
-1577.85
-1022.10
83
1517.14
768.86
27
-1577.85
-1128.52
84
1517.14
882.90
28
-1577.85
-1235.20
85
1517.14
999.74
29
-1577.85
-1341.63
86
1517.14
1113.79
30
-1577.85
-1448.31
87
1517.14
1230.63
31
-1577.85
-1554.73
88
1544.83
1734.82
32
-1577.85
-1797.56
89
1427.99
1734.82
33
-1471.17
-1797.56
90
1313.94
1734.82
34
-1364.74
-1797.56
91
1196.85
1734.82
35
-1258.06
-1797.56
92
1083.06
1734.82
36
-1151.64
-1797.56
93
965.96
1734.82
37
-1044.96
-1797.56
94
851.92
1734.82
38
-938.53
-1797.56
95
735.08
1734.82
39
-831.85
-1797.56
96
621.03
1734.82
40
-725.42
-1797.56
97
503.94
1734.82
41
-618.74
-1797.56
98
389.89
1734.82
42
-512.32
-1797.56
99
273.05
1734.82
43
-405.64
-1797.56
100
159.00
1734.82
44
-299.21
-1797.56
101
41.91
1734.82
45
-192.53
-1797.56
102
-72.14
1734.82
46
-1797.56
103
-188.98
1734.82
47
-86.11
20.57
-1797.56
104
-303.02
1734.82
48
127.00
-1797.56
105
-420.12
1734.82
49
233.45
-1797.56
106
-534.16
1734.82
50
340.11
-1797.56
107
-651.00
1734.82
51
446.53
-1797.56
108
-765.05
1734.82
52
553.21
-1797.56
109
-882.14
1734.82
53
659.64
-1797.56
110
-995.93
1734.82
54
766.83
-1797.56
111
-1113.03
1734.82
55
873.25
-1797.56
112
-1241.55
1781.81
56
979.68
-1797.56
113
-1347.98
1781.81
57
1100.07
-1797.56
114
-1454.66
1781.81
Rev. 1.20
5
July 5, 2002
HTG2190
Pad Descriptions
I/O
Mask Option
37~1
SEG0~SEG39
114~112
Pad No.
Pad Name
O
¾
LCD segment signal output
53~38
COM0~COM15
O
¾
LCD common signal output
54~57
VOUT11, VOUT22
VOUT33, VOUT44
O
¾
LCD driving power generated
62, 61,
60, 58
CAP1, CAP2,
CAP3, CAP4
¾
¾
LCD system voltage booster condenser connecting terminal.
59, 63
66, 67
TRIM1~TRIM4
¾
¾
Test pin only
64
VSS
¾
¾
Negative power supply, ground
68
65
OSCI
OSCO
O
69
VDD
¾
I
Crystal or RC
¾
Description
OSCI and OSCO are connected to an RC network or a crystal (by mask option) for the internal system clock. In the
case of RC operation,OSCI is connected to the RC network
of the internal system clock.
Positive power supply
70
INT/SIN
I
INT or Serial
Data Input
Selectable as external interrupt Schmitt trigger input or serial
data input by mask option. External interrupt Schmitt trigger
input with pull-high resistor. Edge triggered activated on INT
or Serial data input a high to low transition. Serial data input
with pull-high resistor. INT shares pad with SIN.
71
RES
I
¾
Schmitt trigger reset input. Active low without pull-high resistor.
72
PWM2/AUD
O
PWM2 CMOS
Output or
AUD Output
Selectable as negative PWM CMOS output or audio output
by mask option. PWM2 share pad with AUD.
PB0/PWM1
I/O
or
O
I/O or
PWM1 CMOS
Output
Selectable as bidirectional input/output or positive PWM
CMOS output by mask option. On bidirectional input/output
mode, software instructions determine whether each pad is
a CMOS output or Schmitt trigger input with pull-high resistor. PB0 shares pad with PWM1.
I/O or
TMR0 Input
Selectable as bidirectional input/output or TMR0 input by
mask option. On bidirectional input/output mode, software
instructions determine whether it is a CMOS output or
Schmitt trigger input with pull-high resistor. On TMR0 input
mode, it uses Timer/Event Counter 0. Software can be
optioned with or without pull-high resistor. PB7 shares pad
with TMR0.
I/O or
TMR1 Input
or
RTF Input
Selectable as bidirectional input/output or TMR1 input or
RTF input by mask option. On bidirectional input/output
mode, software instructions determine whether it is a
CMOS output or Schmitt trigger input with pull-high resistor.
On TMR1 and RTF input mode, it uses Timer/Event Counter 1. Software can be optioned with or without pull-high resister and be option the RTF function disable or enable.
PB6 and TMR1 share pad with RTF.
73
74
75
Rev. 1.20
PB7/TMR0
PB6/TMR1/RTF
I/O
or
I
I/O
or
I
6
July 5, 2002
HTG2190
Pad No.
Pad Name
I/O
Mask Option
Description
Selectable as bidirectional input/output or serial interface
clock signal by mask option. On bidirectional input/output
mode, software instructions determine whether it is a CMOS
output or Schmitt trigger input .
76
I/O or
PB5/SCLK
I/O
77
PB4/SOUT
I/O
or
O
SOUT Output
78
79
PB3
PB2
I/O
¾
87~80
88
89
PA0~PA7
I/O
XIN/PC7/SEG63
XOUT/PC6/SEG62
I
or
I/O
or
O
PC0~5/SEG56~61
95~90
103~96 PD0~7/SEG48~55
111~104 PE0~7/SEG40~47
I/O
or
O
SCLK Signal
I/O or
Serial I/O interface clock signal.
At Master mode: SCLK should be set as serial clock output
pin and after 8 clock output from SCLK terminal, clock output is automatically suspended and SCLK terminal is fixed
at a high level.
At Slave mode: SCLK should be set as serial clock input pin
and after 8 clock input from SCLK terminal, subsequent
clock input are masked. PB5 shares pad with SLCK
Selectable as bidirectional input/output or serial data output
master by mask option. On bidirectional input/output
mode, software instructions determine whether it is a
CMOS output or Schmitt trigger input . On serial output mode,
SOUT pin is a CMOS output. PB4 shares pad with SOUT.
Software instructions determine whether it is a CMOS output or Schmitt trigger input with pull-high resistor. When the
PB6/TMR1/RTF pad is selected to be in RTF mode, the
PB3, PB2 pull-high resistor is not present.
Bidirectional 8-bit input/output port. Each bit can be configured as a wake-up input by mask option. Software instructions determine whether it is a CMOS output or Schmitt
None Wake-up trigger input with pull-high resistor.
Wake-up
or
Crystal or I/O
or Segment
Output
Selectable as 32768Hz crystal or bidirectional input/output
or segment signal output by mask option. 32768Hz crystal
for timer3 and LCD clock source. XOUT and PC6 share
with SEG62 Pad,XIN and PC7 share with SEG63 pad.
Three bidirectional 8-bit input/output ports. Software instructions determine the CMOS output or Schmitt trigger input with pull-high resistor. PC, PD, PE can be individually
I/O or
optioned for segment output by mask option. PC0~PC7
Segment Output share pads with SEG56~SEG63, PD0~PD7 share pads
with SEG48~SEG55, and PE0~PE7 share pads with
SEG40~SEG47.
Absolute Maximum Ratings
Supply Voltage .........................................-0.3V to 3.6V
Storage Temperature ............................-50°C to 125°C
Input Voltage..............................VSS-0.3V to VDD+0.3V
Operating Temperature...............................0°C to 70°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Rev. 1.20
7
July 5, 2002
HTG2190
D.C. Characteristics
Symbol
Parameter
Ta=25°C
Test Conditions
VDD
Conditions
Min.
Typ.
Max.
Unit
VDD
Operating Voltage
¾
¾
2.4
¾
3.6
V
IDD
Operating Current (RC OSC)
3V
No load, fSYS=4MHz
¾
1
1.5
mA
ISTB1
Standby Current (RTC ON, LCD ON)
3V
No load, HALT
¾
9
30
mA
ISTB2
Standby Current (RTC ON, LCD OFF)
3V
No load, HALT
¾
3.5
15
mA
VIL1
Input Low Voltage for I/O Ports
3V
¾
0
¾
0.9
V
VIH1
Input High Voltage for I/O Ports
3V
¾
2.1
¾
3
V
VIL2
Input Low Voltage (TMR0, TMR1, INT)
3V
¾
0
¾
0.7
V
VIH2
Input High Voltage (TMR0, TMR1, INT)
3V
¾
2.3
¾
3
V
VIL3
Input Low Voltage (RES)
3V
¾
¾
1.5
¾
V
VIH3
Input High Voltage (RES)
3V
¾
¾
2.4
¾
V
IOL1
I/O Ports Sink Current
3V
VOL=0.3V
1.5
4
¾
mA
IOH1
I/O Ports Source Current
3V
VOH=2.7V
-1
-2
¾
mA
VLCD
LCD Voltage
3V
3.96
4.4
4.84
V
IOL2
PWM1/PWM2 Sink Current
3V
VOL=0.3V
12
16
¾
mA
IOH2
PWM1/PWM2 Source Current
3V
VOH=2.7V
-8
-10
¾
mA
IOL3
Audio Sink Current
3V
VOL=0.3V
1.5
2
¾
mA
IOH3
Audio Source Current
3V
VOH=2.7V
-1.5
-2
¾
mA
IOL4
Segment 0~39 Output Sink Current
3V
VOL=0.3V
80
130
¾
mA
IOH4
Segment 0~39 Output Source Current
3V
VOH=2.7V
-50
-90
¾
mA
IOL5
Segment 40~63 Output Sink Current
3V
VOL=0.3V
40
80
¾
mA
IOH5
Segment 40~63 Output Source Current
3V
VOH=2.7V
-30
-60
¾
mA
RPH
Pull-high Resistance of I/O Ports,
TMR0, TMR1 & INT
3V
30
60
100
kW
¾
¾
A.C. Characteristics
Symbol
Parameter
Ta=25°C
Test Conditions
VDD
Conditions
Min.
Typ.
Max.
Unit
fSYS
System Clock (RC OSC)
3V
¾
400
¾
4000
kHz
fTIMER
Timer Input Frequency (TMR0,TMR1)
3V
¾
0
¾
4000
kHz
tWDTOSC Watchdog Oscillator
3V
¾
45
90
180
ms
tWDT
Watchdog Time-out Period (RC)
3V
12
23
45
ms
tRES
External Reset Low Pulse width
¾
¾
1
¾
¾
ms
¾
1024
¾
tSYS
1
¾
¾
ms
Without WDT
prescaler
tSST
System Start-up Timer Period
¾
Power-up or wake-up
from HALT
tINT
Interrupt Pulse Width
¾
¾
Note: tSYS=1/fSYS
Rev. 1.20
8
July 5, 2002
HTG2190
Functional Description
After accessing a program memory word to fetch an instruction code, the contents of the program counter are
incremented by one. The program counter then points to
the memory word containing the next instruction code.
Execution flow
The system clock for the HTG2190 is derived from either a crystal or an RC oscillator. It is internally divided
into four non-overlapping clocks. One instruction cycle
consists of four system clock cycles.
When executing a jump instruction, conditional skip execution, loading PCL register, subroutine call, initial reset, internal interrupt, external interrupt or return from
subroutine, the PC manipulates the program transfer by
loading the address corresponding to each instruction.
Instruction fetching and execution are pipelined in such
a way that a fetch takes one instruction cycle while decoding and execution takes the next instruction cycle.
However, the pipelining scheme causes each instruction to effectively execute within one cycle. If an instruction changes the program counter, two cycles are
required to complete the instruction.
The conditional skip is activated by instruction. Once the
condition is met, the next instruction, fetched during the
current instruction execution, is discarded and a dummy
cycle takes its place while the correct instruction is obtained.
Program counter - PC
The 13-bit program counter (PC) controls the sequence
in which the instructions stored in program ROM are executed.
T 1
S y s te m
T 2
T 3
T 4
T 1
T 2
T 3
T 4
T 1
T 2
T 3
The lower byte of the program counter (PCL) is a
read/write register (06H). Moving data into the PCL perT 4
C lo c k
O S C 2 (R C
B a n k 0
1 3 b its
P ro g ra m
C o u n te r
o n ly )
P C
P C
P C + 1
B a n k 2
0 0 0 0 H
P C + 2
1 F F F H
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
S ta c k
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
B a n k 1
8 1 9 2 ´ 1 6
B its
2 0 0 0 H
3 F F F H
B a n k 7
4 0 0 0 H
E 0 0 0 H
5 F F F H
F F F F H
B a n k P o in te r
R e g is te r
B it7 ,B it6 ,B it5
A 1 5 ,A 1 4 ,A 1 3
B u ffe r
L a tc h d a ta o n E x e c u tio n o f J u m p o r C a ll In s tr u c tio n
6 4 K P r o g r a m R O M A d d r e s s in g A r c h ite c tu r e
Execution flow
Mode
Program ROM Address
*15
*14 *13 *12
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
External or serial
input interrupt
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
Timer/Event
Counter 0 overflow
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
Timer/Event
Counter 1 overflow
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
Timer 2 overflow
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
Timer 3 overflow
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
PC+2
Skip
Loading PCL
*15
*14 *13 *12
*11
*10
*9
*8
@7
@6
@5
@4
@3
@2
@1 @0
Jump, call branch
BP.7 BP.6 BP.5 #12 #11 #10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return from
subroutine
S15 S14 S13 S12 S11 S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Program ROM address
Note: *15~*0: Program ROM address
S15~S0: Stack register bits
@7~@0: PCL bits
BP.5~BP.7: Bit 5~7 of bank pointer (04H)
#12~#0: Instruction code bits
Rev. 1.20
9
July 5, 2002
HTG2190
forms a short jump. The destination must be within 256
locations.
0 0 0 0 H
0 0 0 4 H
When a control transfer takes place, an additional
dummy cycle is required.
0 0 0 8 H
0 0 0 C H
Program memory - ROM
0 1 0 H
The program memory, which contains executable program instructions, data and table information, is composed of a 65536 x 16 bit format. However as the PC
(program counter) is comprised of only 13 bits, the remaining 3 ROM address bits are managed by dividing
the program memory into 8 banks, each bank having a
range between 0000H and 1FFFH. To move from the
present ROM bank to a different ROM bank, the higher 3
bits of the ROM address are set by the BP (Bank
Pointer), while the remaining 13 bits of the PC are set in
the usual way by executing the appropriate jump or call
instruction. As the full 16 address bits are latched during
the execution of a call or jump instruction, the correct
value of the BP must first be setup before a jump or call
is executed. When either a software or hardware interrupt is received, note that no matter which ROM bank
the program is in the program will always jump to the appropriate interrupt service address in Bank 0. The original full 16 bit address will be stored on the stack and
restored when the relevant RET/RETI instruction is executed, automatically returning the program to the original ROM bank. This eliminates the need for
programmers to manage the BP when interrupts occur.
0 1 4 H
E x te r n a l o r s e r ia l in p u t in te r r u p t s u b r o u tin e
T im e r /e v e n t c o u n te r 0 in te r r u p t s u b r o u tin e
T im e r /e v e n t c o u n te r 1 in te r r u p t s u b r o u tin e
T im e r 2 in te r r u p t s u b r o u tin e
T im e r 3 in te r r u p t s u b r o u tin e
0 1 8 H
P ro g ra m
R O M
D /A b u ffe r e m p ty in te r r u p t
F F F F H
1 6 b its
Program memory
·
·
Certain locations in Bank 0 of program memory are reserved for special usage:
· ROM Bank 0 (BP5~BP7=000B)
·
The ROM bank 0 ranges from 0000H to 1FFFH.
· Location 000H
This area is reserved for the initialization program. After a chip reset, the program always begins execution
at location 000H.
· Location 004H
This area is reserved for the external interrupt or serial
input interrupt service routine. If the INT input pin is
activated, and the interrupt is enabled and the stack is
not full, the program will jump to location 004H and begins execution.
·
·
· Location 008H/00CH
This area is reserved for the Timer/Event Counter 0/1 interrupt service program. If a timer interrupt results from a
Instruction
D e v ic e in itia liz a tio n p r o g r a m
Timer/Event Counter 0/1 overflow, and if the interrupt is
enabled and the stack is not full, the program will jump to
location 008H/00CH and begins execution.
Location 010H/014H
This area is reserved for the timer 2/3 interrupt service
program. If a timer interrupt resulting from a timer 2/3
overflow, and if the interrupt is enabled and the stack
is not full, the program will jump to location
010H/014H and begins execution.
Location 018H
This area is reserved for the PWM D/A buffer empty
interrupt service program. After the system latch a D/A
code at RAM address 28H, the interrupt is enable, and
the stack is not full, the program begins execution at
location 018H.
Location 020H
For best condition, this location is reserved as the beginning when writing a program.
ROM Bank 1~7 (BP5~BP7=001B~111)
The range of the ROM starts from n000H to
(n+1)FFFH. (n=2,4,6,8,10,12,14)
Table location
Any location in the ROM space can be used as look up
table. The instructions TABRDC [m] (use for any
bank) and TABRDL [m] (only used for last page of program ROM) transfers the contents of the lower-order
byte to the specified data memory, and the
higher-order byte to TBLH (08H). Only the destination
of the lower-order byte in the table is well-defined, the
Table Location
*15
*14
*13
*12
*11
*10
*9
*8
*7
*6
*5
*4
TABRDC [m]
#7
#6
#5
#4
#3
#2
#1
#0
@7
@6
@5
@4
@3 @2 @1 @0
*3
*2
*1
*0
TABRDL [m]
1
1
1
1
1
1
1
1
@7
@6
@5
@4
@3 @2 @1 @0
Table location
Note: @7~@0: TBLP register bit7~bit0
*15~*0: Program ROM table address bit15~bit0
#7~#0: TBHP register bit7~bit0
Rev. 1.20
10
July 5, 2002
HTG2190
higher-order byte of the table word are transferred to
the TBLH. The Table Higher-order byte register
(TBLH) is read only. The Table Pointer (TBHP, TBLP)
is a read/write register (1FH, 07H), used to indicate
the table location. Before accessing the table, the location must be placed in TBLP. The TBLH is read only
and cannot be restored. If the main routine and the
ISR (Interrupt Service Routine) both employ the table
read instruction, the contents of the TBLH in the main
routine are likely to be changed by the table read instruction used in the ISR. If this happens errors can
occur. In other words, using the table read instruction
in the main routine and the ISR simultaneously should
be avoided. However, if the table read instruction has
to be applied in both the main routine and the ISR, the
interrupt(s) should be disabled prior to the table read
instruction. It should not be enabled until the TBLH
has been backed up. All table related instructions
need two cycles to complete the operation. These areas may function as normal program memory depending upon requirements.
0 0 H
IA R 0
In d ir e c t A d d r e s s in g R e g is te r 0
0 1 H
M P 0
M e m o r y P o in te r 0
0 2 H
IA R 1
In d ir e c t A d d r e s s in g R e g is te r 1
0 3 H
M P 1
M e m o r y P o in te r 1
0 4 H
B P
B a n k P o in te r
0 5 H
A C C
0 6 H
P C L
0 7 H
T B L P
A c c u m u la to r
P ro g ra m
C o u n te r L o w e r - b y te R e g is te r
T a b le P o in te r L o w e r - o r d e r B y te R e g is te r
0 8 H
T B L H
T a b le H ig h e r - o r d e r B y te R e g is te r
0 9 H
W D T S
W a tc h d o g T im e r O p tio n S e ttin g R e g is te r
0 A H
S T A T U S
S ta tu s R e g is te r
0 B H
IN T C 0
In te r r u p t C o n tr o l R e g is te r 0
0 C H
T M R 0 H
T im e r C o u n te r 0 H ig h e r - o r d e r B y te R e g is te r
0 D H
T M R 0 L
0 E H
T M R 0 C
T im e r C o u n te r 0 C o n tr o l R e g is te r
0 F H
T M R 1 H
T im e r /E v e n t C o u n te r 1 H ig h e r - o r d e r B y te R e g is te r
1 0 H
T M R 1 L
T im e r /E v e n t C o u n te r 1 L o w - o r d e r B y te R e g is te r
1 1 H
T M R 1 C
P A
T im e r /E v e n t C o u n te r 1 C o n tr o l R e g is te r
P A I/O D a ta R e g is te r
1 2 H
1 3 H
P A C
1 4 H
P B
1 5 H
P B C
1 6 H
P C
1 7 H
P C C
1 8 H
P D
1 9 H
P D C
1 A H
P E
1 B H
P E C
T im e r C o u n te r 0 L o w e r - o r d e r B y te R e g is te r
P A I/O
C o n tr o l R e g is te r
P B I/O
P B I/O
P C
P C
D a ta R e g is te r
C o n tr o l R e g is te r
I/O
I/O
P D
D a ta R e g is te r
C o n tr o l R e g is te r
I/O
D a ta R e g is te r
P D
I/O
P E I/O
P E I/O
C o n tro l
S p e c ia l P u r p o s e
D a ta M e m o ry
D a ta R e g is te r
C o n tr o l R e g is te r
1 C H
1 D H
1 E H
1 F H
Stack register - STACK
2 0 H
2 1 H
This is a special part of memory which is used to save
the contents of the program counter (PC) only. The
stack is organized into 8 levels and is neither part of the
data nor program space, and is neither readable nor
writeable. The activated level is indexed by the stack
pointer (SP) and is neither readable nor writeable. At a
subroutine call or interrupt acknowledgment, the contents of the program counter are pushed onto the stack.
At the end of a subroutine or an interrupt routine, signaled by a return instruction (RET or RETI), the program
counter is restored to its previous value from the stack.
After a chip reset, the SP will point to the top of the stack.
2 2 H
2 3 H
2 4 H
In te r r u p t C o n tr o l R e g is te r 1
T a b le P o in te r H ig h e r - o r d e r B y te R e g is te r
T M R 2
T im e r 2 R e g is te r
T M R 2 C
T im e r 2 C o n tr o l R e g is te r
T M R 3
T im e r 3 R e g is te r
T im e r 3 C o n tr o l R e g is te r
2 6 H
X 'T A L C
X 't a l F a s t O s c illa t o r u p C o n t r o l
2 7 H
P W M C
2 8 H
P W M
S E R C
2 9 H
2 A H
2 B H
2 C H
2 D H
P W M
P W M
C o n tro l
D a ta
S e r ia l C o n tr o l
S E R D A T A
C O L 0
C o lo r 0 P a le tte s
C O L 1
C o lo r 1 P a le tte s
C O L 2
S e r ia l D a ta
C o lo r 2 P a le tte s
2 E H
C O L 3
2 F H
C O M R
D A L
D /A D a ta L o w e r - o r d e r B y te R e g is te r
D A H
D /A D a ta H ig h e r - o r d e r B y te R e g is te r
V O L C
V o lu m e C o n tr o l R e g is te r
3 0 H
3 1 H
3 2 H
3 3 H
3 F H
4 0 H
F F H
4 0 H
F F H
4 0 H
F F H
In a similar case, if the stack is full and a CALL is subsequently executed, stack overflow occurs and the first entry will be lost (only the most recent eight return address
are stored).
T B H P
T M R 3 C
2 5 H
If the stack is full and a non-masked interrupt takes place,
the interrupt request flag will be recorded but the acknowledge will be inhibited. When the stack pointer is decremented (by RET or RETI), the interrupt will be serviced.
This feature prevents stack overflow allowing the programmer to use the structure more easily.
IN T C 1
C o lo r 3 P a le tte s
C o m m o n P a d A d d re s s R o ta to r
: U n u s e d
G e n e ra l P u rp o s e
B a n k 0 D a ta M e m o ry
(1 9 2 B y te )
G e n e ra l P u rp o s e
B a n k 1 D a ta M e m o ry
(1 9 2 B y te )
G e n e ra l P u rp o s e
B a n k 1 1 D a ta M e m o ry
(1 9 2 B y te )
8 0 H
F F H
8 0 H
F F H
Data memory - RAM
B a n k 1 4 D a ta M e m o ry
(1 2 8 B y te )
B a n k 1 5 D a ta M e m o ry
(1 2 8 B y te )
RAM mapping
· Bank 0 (BP4~BP0=00000)
The Bank 0 data memory includes special purpose
and general purpose memory. The special purpose
memory is addressed from 00H to 3FH. All data memory areas can handle arithmetic, logic, increment,
decrement and rotate operations directly. Except for
some dedicated bits, each bit in the data memory can
be set and reset by the SET [m].i and CLR [m].i instructions, respectively. They are also indirectly accessible through the memory pointer registers
(MP0;01H, MP1;03H).
Rev. 1.20
· Bank 1~11 (BP4~BP0=0001B~1011B)
The range of RAM starting from 40H to FFH are for
general purpose. Only MP1 can deal with the memory
of this range.
11
July 5, 2002
HTG2190
· Bank 14/15 (BP4~BP0=01110B~01111B)
ment outputs share pins with I/O pins, PE0~PE7
(SEG40~47), PD0~PD7(SEG48~55) and PC0~PC7
(SEG56~63). Whether segment output or I/O pin can be
decided by mask option.
The range of RAM starts from 80H to FFH. Every bit
stands for one dot on the LCD. If the bit is ²1², the light
of the dot on the LCD will be turned on. If the bit is ²0²,
then it will be turned off. Only MP1 can deal with the
memory of this range.
The contrast form of RAM location, COMMON, and
SEGMENT is as follows.
LCD driver output can be enabled or disabled by setting
COL3 (bit 6 of COL3; 2EH) without the influence of the
related memory condition.
On the Color LCD Mode: Every two bits stands for one
dot on the ECB. If the both bits is not 0, the light of the
dot on the ECB will be turned on. If the both bits is 0,
then it will be selected to color 0. Only MP1 can be deal
with the memory of this range. The contrast form of RAM
location, COMMON, and SEGMENT is as follows.
LCD driver output
The maximum output number of the HTG2190 LCD
driver is 16´64. The Common output signal can be selected as 16 com or 8 com by mask option. The LCD
driver bias type is ²C² type, external capacitor is required and the bias voltage is 1/4 bias. Some of the SegAddress
D7
D6
D5
D4
D3
D2
D1
D0
80H
SEG0~COM3
SEG0~COM2
SEG0~COM1
SEG0~COM0
81H
SEG0~COM7
SEG0~COM6
SEG0~COM5
SEG0~COM4
82H
SEG1~COM3
SEG1~COM2
SEG1~COM1
SEG1~COM0
83H
SEG1~COM7
SEG1~COM6
SEG1~COM5
SEG1~COM4
84H
SEG2~COM3
SEG2~COM2
SEG2~COM1
SEG2~COM0
85H
SEG2~COM7
SEG2~COM6
SEG2~COM5
SEG2~COM4
FAH
SEG61~COM3
SEG61~COM2
SEG61~COM1
SEG61~COM0
FBH
SEG61~COM7
SEG61~COM6
SEG61~COM5
SEG61~COM4
FCH
SEG62~COM3
SEG62~COM2
SEG62~COM1
SEG62~COM0
FDH
SEG62~COM7
SEG62~COM6
SEG62~COM5
SEG62~COM4
FEH
SEG63~COM3
SEG63~COM2
SEG63~COM1
SEG63~COM0
FFH
SEG63~COM7
SEG63~COM6
SEG63~COM5
SEG63~COM4
LCD RAM mapping Bank14
Address
D7
D6
D5
D4
D3
D2
D1
D0
80H
SEG0~COM11
SEG0~COM10
SEG0~COM9
SEG0~COM8
81H
SEG0~COM15
SEG0~COM14
SEG0~COM13
SEG0~COM12
82H
SEG1~COM11
SEG1~COM10
SEG1~COM9
SEG1~COM8
83H
SEG1~COM15
SEG1~COM14
SEG1~COM13
SEG1~COM12
84H
SEG2~COM11
SEG2~COM10
SEG2~COM9
SEG2~COM8
85H
SEG2~COM15
SEG2~COM14
SEG2~COM13
SEG2~COM12
FAH
SEG61~COM11
SEG61~COM10
SEG61~COM9
SEG61~COM8
FBH
SEG61~COM15
SEG61~COM14
SEG61~COM13
SEG61~COM12
FCH
SEG62~COM11
SEG62~COM10
SEG62~COM9
SEG62~COM8
FDH
SEG62~COM15
SEG62~COM14
SEG62~COM13
SEG62~COM12
FEH
SEG63~COM11
SEG63~COM10
SEG63~COM9
SEG63~COM8
FFH
SEG63~COM15
SEG63~COM14
SEG63~COM13
SEG63~COM12
LCD RAM mapping Bank15
Rev. 1.20
12
July 5, 2002
HTG2190
Register
Address
COL0
2BH
COL1
2CH
COL2
2DH
Bit No.
Label
0~4
P0~P4
5~7
¾
0~4
P0~P4
5~7
¾
0~4
P0~P4
5~7
¾
Description
Color0 palette
Unused bit read only
Color1 palette
Unused bit read only
Color2 palette
Unused bit read only
How to select the color:
Dn+1
Dn
Color 0
0
0
Color 1
0
1
Color 2
1
0
Color 3
1
1
Segment¾Common
LCDC register
Register
Bit No.
Label
0~4
P0~P4
5
¾
6
LCD
Controls the LCD output (0=disable, 1=enable) (Default=1)
7
RC
LCD clock source select (Default=0)
1=32768Hz crystal
COL3
Function
Color3 palette
Unused bit, read as ²0²
0=system clock (note*)
COL3 register
Note:
* When the mask option is selected to 32K x¢tal disable, user should be set ²0² to COL3.7.
But the 32K x¢tal can¢t be disabled in the HT-IDE2000 tools, so user should take care of this difference.
An example of an ECB driving waveform is shown below:
8 COM, 1/4 bias LCD clock source=16384Hz
8
V
C O M 0
1
8
2
1
2
W
D D
3 /4 V D D
2 /4 V D D
1 /4 V D D
G N D
w '
V
S E G
C O M 0 -S E G
D D
3 /4 V D D
2 /4 V D D
1 /4 V D D
G N D
V
L C D
1 /4 V
L C D
-1 /4 V
L C D
-V
L C D
w '
O N
O F F
6 4 H z
N o t e : W ' R e a l a c t iv e s e g m e n t s ig n a l w id t h W '= 13 W2 ~ 3 1 W
3 2
2 B H ,2 C H ,2 D H b it0 ~ b it4 )
W : M a x . a c tiv e s e g m e n t s ig n a l w id th
Rev. 1.20
13
( a d ju s ta b le w id th b y R A M
A d d re s s
July 5, 2002
HTG2190
16COM, 1/4bias LCD clock source=32768Hz
1 6
V
C O M 0
W
1
2
1 6
1
2
D D
3 /4 V D D
2 /4 V D D
1 /4 V D D
G N D
w '
V
S E G
3 /4 V D D
2 /4 V D D
1 /4 V D D
G N D
V
C O M 0 -S E G
D D
w '
L C D
1 /4 V
L C D
-1 /4 V
L C D
-V
L C D
O N
O F F
6 4 H z
N o t e : W ' R e a l a c t iv e s e g m e n t s ig n a l w id t h W '= 13 W2 ~ 3 1 W
3 2
2 B H ,2 C H ,2 D H b it0 ~ b it4 )
W : M a x . a c tiv e s e g m e n t s ig n a l w id th
( a d ju s ta b le w id th b y R A M
A d d re s s
On the BW LCD Mode: Bank14 has a general purpose data RAM and for Bank15, every 1 bit stands for one dot on the
LCD. If the bits is not 0, the light of the dot on the LCD will be turned on. If the bits is 0, then it will be turned off. Only MP1
can deal with the memory of this range. The contrast form of RAM location, COMMON and SEGMENT is as follows:
Address
80H
COM0
Bit0
COM1
Bit1
COM2
Bit2
COM3
Bit3
COM4
Bit4
COM5
Bit5
COM6
Bit6
COM7
Bit7
Address
C0H
COM8
Bit0
COM9
Bit1
COM10
Bit2
COM11
Bit3
COM12
Bit4
COM13
Bit5
COM14
Bit6
COM15
Bit7
81H
82H
83H
84H
85H --------------------91H
92H
----
----
----
BFH
C1H
C2H
C3H
C4H C5H -------------------------
----
----
----
FEH
FFH
----
----
----
SEG63
SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 -------------SEG17 SEG18
LCD display memory: (Bank15)
Rev. 1.20
14
July 5, 2002
HTG2190
An example of an LCD driving waveform is shown below.
8 COM, 1/4 bias
3 2 H z
3
2
1
4
6
5
8
7
2
1
3
4
5
6
1 2
1 3
1 4
1 5
8
7
3
2
1
4
5
5 1 2 H z
C O M 0
V D D
3 /4 V D D
2 /4 V D D
1 /4 V D D
G N D
C O M 1
V D D
3 /4 V D D
2 /4 V D D
1 /4 V D D
G N D
S E G 0
V D D
3 /4 V D D
2 /4 V D D
1 /4 V D D
G N D
16 COM, 1/4 bias
3 2 H z
1
2
3
4
5
6
7
8
9
1 0
1 1
1 6
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5 1 6
1 0 2 4 H z
C O M 0
V D D
3 /4 V D D
2 /4 V D D
1 /4 V D D
G N D
C O M 1
V D D
3 /4 V D D
2 /4 V D D
1 /4 V D D
G N D
S E G 0
V D D
3 /4 V D D
2 /4 V D D
1 /4 V D D
G N D
Rev. 1.20
15
July 5, 2002
HTG2190
SSL3
SSL2
SSL1
SSL0
Description
x
0
0
0
The Pad of common 0 is connected to common 0 signal and the Pad of
common 1 is connected to common 1 signal and so on.
x
0
0
1
The Pad of common 0 is connected to common 1 signal and the Pad of
common 1 is connected to common 2 signal and so on.
x
0
1
0
The Pad of common 0 is connected to common 2 signal and the Pad of
common 1 is connected to common 3 signal and so on.
x
0
1
1
The Pad of common 0 is connected to common 3 signal and the Pad of
common 1 is connected to common 4 signal and so on.
x
1
0
0
The Pad of common 0 is connected to common 4 signal and the Pad of
common 1 is connected to common 5 signal and so on.
x
1
0
1
The Pad of common 0 is connected to common 5 signal and the Pad of
common 1 is connected to common 6 signal and so on.
x
1
1
0
The Pad of common 0 is connected to common 6 signal and the Pad of
common 1 is connected to common 7 signal and so on.
x
1
1
1
The Pad of common 0 is connected to common 7 signal and the Pad of
common 1 is connected to common 0 signal and so on.
COMR register
Indirect addressing register
Status register - STATUS
Locations 00H and 02H are indirect addressing registers that are not physically implemented. Any read/write
operation of [00H] and [02H] access data memory
pointed to by MP0 (01H) and MP1 (03H) respectively.
Reading location 00H or 02H indirectly returns the result
00H, while writing to it indirectly results in no operation.
This 8-bit register (0AH) contains the zero flag (Z), carry
flag (C), auxiliary carry flag (AC), overflow flag (OV),
power down flag (PD) and Watchdog time-out flag (TO).
It also records the status information and controls the operation sequence.
With the exception of the TO and PD flags, bits in the
status register can be altered by instructions like any
other register. Any data written into the status register
will not change the TO or PD flags. In addition, operations related to the status register may give different results from those intended. The TO and PD flags can only
be changed by a system power up, Watchdog Timer
overflow, executing the HALT instruction and clearing
the Watchdog Timer.
The data movement function between two indirect addressing registers is not supported. The memory pointer
registers MP0 and MP1, are 8-bit registers used to access the data memory by combining corresponding indirect addressing registers, Bank1~Bank11, Bank14 and
Bank15 can use MP1 only.
Accumulator
The accumulator closely relates to ALU operations. It is
also mapped to location 05H of the data memory and is
the one which can operate with immediate data. The
data movement between two data memory must pass
through the accumulator.
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
In addition, on entering the interrupt sequence or executing the subroutine call, the status register will not be
pushed onto the stack automatically. If the contents of
the status register are important and the subroutine can
corrupt the status register, the programmer must take
precautions to save it properly.
Arithmetic and logic unit - ALU
This circuit performs 8-bit arithmetic and logic operation.
The ALU provides the following functions:
· Arithmetic operations (ADD, ADC, SUB,
Interrupt
SBC, DAA)
The HTG2190 provides external and a PWM D/A interrupt and internal timer/event counter interrupts. The interrupt control register (INTC;0BH, INTCH;1EH) contains
the interrupt control bits to set the enable/disable and the
interrupt request flags.
· Logic operations (AND, OR, XOR, CPL)
· Rotation (RL, RR, RLC, RRC)
· Increment and Decrement (INC, DEC)
· Branch decision (SZ, SNZ, SIZ, SDZ ....)
The ALU not only saves the results of a data operation but
can also change the status register.
Rev. 1.20
16
July 5, 2002
HTG2190
Labels
Bits
Function
C
0
C is set if the operation results in a carry during an addition operation or if a borrow does not take
place during a subtraction operation; otherwise C is cleared. Also it is affected by a rotate through
carry instruction.
AC
1
AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from the
high nibble into the low nibble in subtraction; otherwise AC is cleared.
Z
2
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.
OV
3
OV is set if the operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared.
PD
4
PD is cleared when either a system power-up or executing the CLR WDT instruction. PD is set by
executing the HALT instruction.
TO
5
TO is cleared by a system power-up or executing the CLR WDT or HALT instruction. TO is set by a
WDT time-out.
¾
6,7
Unused bit, read as ²0²
STATUS register
Once an interrupt subroutine is serviced, all other interrupts will be blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other
interrupt requests may happen during this interval but
only the interrupt request flag is recorded. If a certain interrupt needs servicing within the service routine, the EMI
bit and the corresponding INTC bit may be set to allow interrupt nesting. If the stack is full, the interrupt request will
not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If immediate service is
desired, the stack must be prevented from becoming full.
The Timer/Event Counter 1 and timer 2/3 interrupt is operated in the same manner as Timer/Event Counter 0.
The related interrupt control bits ET1I and T1F of
Timer/Event Counter 1 are bit 3 and bit 6 of INTC0 respectively. While ET2I/ET3I and T2F/T3F are the related control bits and the related request flags of
TMR2/TMR3, which locate at bit0/bit1 and bit4/bit5 of
the INTC1 respectively.
During the execution of an interrupt subroutine, other interrupt acknowledgments are held until the RETI instruction is
executed or the EMI bit and the related interrupt control bit
are set to 1 (of course, if the stack is not full). To return from
the interrupt subroutine, the RET or RETI instruction may
be invoked. RETI will set the EMI bit to enable an interrupt
service, but RET will not.
All these kinds of interrupt have the wake-up capability.
As an interrupt is serviced, a control transfer occurs by
pushing the program counter and A15~A13 bits onto the
stack and then branching to subroutines at specified location(s) in the program memory. Only the program
counter are pushed and A15~A13 bits onto the stack. If
the contents of the register and Status register
(STATUS) are altered by the interrupt service program
which corrupt the desired control sequence, the contents must be saved first.
Interrupts occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests,
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
External interrupt is triggered by a high to low transition
of INT which sets the related interrupt request flag (EIF;
bit 4 of INTC0). When the interrupt is enabled, and the
stack is not full and the external interrupt is active, a subroutine call to location 04H will occur. The interrupt request flag (EIF) and EMI bits will be cleared to disable
other interrupts.
Interrupt Source
The internal Timer/Event Counter 0 interrupt is initialized by setting the Timer/Event Counter 0 interrupt request flag (T0F; bit 5 of INTC0), caused by a
Timer/Event Counter 0 overflow. When the interrupt is
enabled, and the stack is not full and the T0F bit is set, a
subroutine call to location 08H will occur. The related interrupt request flag (T0F) will be reset and the bit
cleared to disable further interrupts.
Rev. 1.20
Priority
Vector
External interrupt
1
04H
Timer/Event Counter 0 overflow
2
08H
Timer/Event Counter 1 overflow
3
0CH
Timer 2 overflow
4
10H
Timer 3 overflow
5
14H
PWM D/A interrupt
6
18H
The Timer/Event Counter 0/1 and timer 2/3 interrupt request flag (T0F/T1F/T2F/T3F), external interrupt request
flag (EIF), PWM D/A interrupt request flag (PWMF) enable
timer/ event counter 0/1/2/3 bit (ET0I/ET1I/ET2I/ ET3I),
enable PWM D/A interrupt bit (PWMI), enable external interrupt bit (EEI) and enable master interrupt bit (EMI) form
17
July 5, 2002
HTG2190
Register
Bit No.
Label
0
EMI
Master (Global) interrupt (1=enable; 0=disable)
1
EEI
External interrupt (1=enable; 0=disable)
2
ET0I
Timer/Event Counter 0 interrupt (1=enable; 0=disable)
3
ET1I
Timer/Event Counter 1 interrupt (1=enable; 0=disable)
4
EIF
External interrupt request flag (1=active; 0=inactive)
5
T0F
Internal Timer/Event Counter 0 request flag. (1=active; 0=inactive)
6
T1F
Internal Timer/Event Counter 1 request flag. (1=active; 0=inactive)
7
¾
INTC0
Function
Unused bit, read as ²0²
INTC0 register
Register
Bit No.
Label
0
ET2I
Controls the Timer 2 interrupt. (1=enable; 0=disable)
1
ET3I
Controls the Timer 3 interrupt. (1=enable; 0=disable)
2
PWMI
3
¾
4
T2F
Internal Timer 2 request flag. (1=active; 0=inactive)
5
T3F
Internal Timer 3 request flag. (1=active; 0=inactive)
6
PWMF
7
¾
INTC1
Function
PWM D/A interrupt (1=enable; 0=disable)
Should be set ²0² always.
PWM D/A flag (1=enable; 0=disable)
Should be set ²0² always.
INTC1 register
The RC oscillator signal provides the internal system
clock. The HALT mode stops the system oscillator and
ignores any external signal to conserve power. Only the
RC oscillator is designed to drive the internal system
clock. The RTC oscillator provides the timer3 and LCD
driver clock source.
the interrupt control register (INTC0/INTC1) located at
0BH/1EH in the data memory. EMI, EEI, ET0I, ET1I, ET2I,
ET3I, PWMI, are used to control the enabling/disabling of
interrupts. These bits prevent the requested interrupt being serviced. Once the interrupt request flags (T0F, T1F,
T2F, T3F, EIF, PWMF) are set, they will remain in the
INTC0/INTC1 register until the interrupts are serviced or
cleared by a software instruction.
The RC oscillator needs an external resistor connected
between OSCI and VSS. The resistance value must
range from 50kW~400kW
It is recommended that application programs do not
use CALL subroutines within an interrupt subroutine.
Interrupts often occur in an unpredictable manner or need
to be serviced immediately in some applications. If only
one stack is left and the interrupt enable is not well
controlled, once a CALL subroutine if used in the interrupt subroutine will corrupt the original control sequence.
However, the frequency of the oscillator may vary with
VDD, temperature and the chip itself due to process variations. It is, therefore, not suitable for timing sensitive
operations where accurate oscillator frequency is desired.
The RTC oscillator is used to provide clock source for
LCD driver and Timer3. It can be enabled or disabled by
mask option.
Oscillator configuration
There are two oscillator circuit in the HTG2190.
X O U T
3 2 7 6 8 H z
R C
O s c illa to r
There is another oscillator circuit designed for the real
time clock. In this case, only the 32768Hz crystal oscillator can be applied. The crystal should be connected between and XOUT, and two external capacitors along
with one external resistor are required for the oscillator
circuit in order to get a stable frequency.
X IN
O S C I
R T C O s c illa to r
System and RTC oscillator
Rev. 1.20
18
July 5, 2002
HTG2190
The WDT oscillator is a free running on-chip RC oscillator, requiring no external components. Even if the system enters the power down mode, and the system clock
is stopped, the WDT oscillator still runs with a period of
approximately 78ms. The WDT oscillator can be disabled by mask option to conserve power.
RES), software instructions, or a HALT instruction. The
software instruction is ²CLR WDT² and execution of the
²CLR WDT² instruction will clear the WDT.
Power down operation - HALT
The HALT mode is initialized by a ²HALT² instruction
and results in the following.
Watchdog Timer - WDT
The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator). This timer is designed to
prevent a software malfunction or sequence jumping to
an unknown location with unpredictable results. The
Watchdog Timer can be disabled by a mask option. If
the Watchdog Timer is disabled, all the executions related to the WDT result in no operation.
· The system oscillator will turn off but the WDT oscilla-
Once the internal WDT oscillator (RC oscillator with a
nominal period of 78ms) is selected, it is first divided by
256 (8-stages) to get the nominal time-out period of approximately 20 ms. This time-out period may vary with
temperature, VDD and process variations. By invoking
the WDT prescaler, longer time-out periods can be realized. Writing data to WS2, WS1, WS0 (bit 2,1,0 of the
WDTS) can give different time-out periods. If WS2,
WS1, WS0 all equal to 1, the division ratio is up to 1:128,
and the maximum time-out period is 2.6 seconds.
· The PD flag is set and the TO flag is cleared.
WS2
WS1
WS0
Division Ratio
0
0
0
1:1
0
0
1
1:2
0
1
0
1:4
0
1
1
1:8
1
0
0
1:16
1
0
1
1:32
1
1
0
1:64
1
1
1
1:128
tor keeps running (if the WDT oscillator is selected).
· The contents of the on chip RAM and registers remain
unchanged.
· WDT and WDT prescaler will be cleared and recount
again.
· All I/O ports maintain their original status.
The system can leave the HALT mode by means of an
external reset, an interrupt, an external falling edge signal on port A or a WDT overflow. An external reset
causes a device initialization and the WDT overflow performs a ²warm reset². By examining the TO and PD flags,
the reason for the chip reset can be determined. The PD
flag is cleared when the system powers-up or executing
the ²CLR WDT² instruction and is set when the ²HALT² instruction is executed. The TO flag is set if a WDT time-out
occurs, and causes a wake-up that only resets the PC and
SP. The others maintain their original status.
The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit
in port A can be independently selected to wake up the
device by a mask option. Awakening from an I/O port
stimulus, the program will resume execution of the next
instruction. If awakening from an interrupt, two sequences may happen. If the related interrupt is disabled
or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. If the
interrupt is enabled and the stack is not full, the regular
interrupt response takes place.
WDTS register
If the device operates in a noisy environment, using the
on-chip RC oscillator (WDT OSC) is strongly recommended, since the HALT will stop the system clock.
Once a wake-up event occurs, it takes 1024 tSYS (system clock period) to resume normal operation. In other
words, a dummy cycle period will be inserted after a
wake-up. If the wake-up results from an interrupt acknowledge, the actual interrupt subroutine will be delayed by one more cycle. If the wake-up results in next
instruction execution, this will be executed immediately
after a dummy period is finished. If an interrupt request
The WDT overflow under normal operation will initialize
a ²chip reset² and set the status bit ²TO². Whereas in
the HALT mode, the overflow will initialize a ²warm re set² only the PC and SP are reset to zero. To clear the
contents of the WDT (including the WDT prescaler ),
three methods are adopted; external reset (a low level to
W D T
O S C
W D T P r e s c a le r
8 - b it C o u n te r
7 - b it C o u n te r
8 -to -1 M U X
W S 0 ~ W S 2
W D T T im e - o u t
Watchdog Timer
Rev. 1.20
19
July 5, 2002
HTG2190
flag is set to ²1² before entering the HALT mode, the
wake-up function of the related interrupt will be disabled.
V D D
R E S
To minimize power consumption, all I/O pins should be
carefully managed before entering the HALT status.
tS
S T
S S T T im e - o u t
C h ip
Reset
R e s e t
There are 3 ways in which a reset can occur:
Reset timing chart
· RES reset during normal operation
· RES reset during HALT
H A L T
· WDT time-out reset during normal operation
W D T
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a ²warm re set² that resets only the PC and SP, leaving the other
circuits in their original state. Some registers remain unchanged during any other reset conditions. Most registers are reset to their ²initial condition² when the reset
conditions are met. By examining the PD flag and TO
flag, the program can distinguish between different
²chip resets².
TO
PD
0
0
RES reset during power-up
u
u
RES reset during normal operation
0
1
RES wake-up HALT
1
u
WDT time-out during normal operation
1
1
WDT wake-up HALT
W a rm
W D T
R e s e t
T im e - o u t
R e s e t
R E S
C o ld
R e s e t
S S T
1 0 -s ta g e
R ip p le C o u n te r
O S C I
P o w e r - o n D e te c tin g
Reset configuration
RESET Conditions
When a system power up occurs, the SST delay is
added during the reset period. But when the reset comes from the RES pin, the SST delay is disabled. Any
wake-up from HALT will enable the SST delay.
The functional unit chip reset status is shown in the table.
Note: ²u² stands for ²unchange²
To guarantee that the system oscillator has started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses after a system
power up or when awakening from a HALT state.
V
D D
R E S
Program Counter
000H
Interrupt
Disable
Prescaler
Clear
WDT
Clear. After master reset,
WDT begins counting
Timer/Event Counter
(0/1/2/3)
Off
LCD Display
Enable
Pull-high of TMR0/TMR1 With pull-high resistor
Input/output Ports
Input mode
SP
Points to the top of the
stack
Reset circuit
The state of the registers is summarized in the following table:
Reset
(power on)
WDT time-out
(normal operation)
RES reset
(normal operation)
RES reset
(HALT)
WDT time-out
(HALT)*
TMR1H
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR1L
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR1C
00-0 1---
00-0 1---
00-0 1---
00-0 1---
uu-u u---
TMR0H
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
Register
Rev. 1.20
20
July 5, 2002
HTG2190
Register
TMR0L
Reset
(power on)
WDT time-out
(normal operation)
RES reset
(normal operation)
RES reset
(HALT)
WDT time-out
(HALT)*
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR0C
00-0 1---
00-0 1---
00-0 1---
00-0 1---
uu-u u---
TMR2
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR2C
00-0 1000
00-0 1000
00-0 1000
00-0 1000
uu-u uuuu
TMR3
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR3C
00-0 1000
00-0 1000
00-0 1000
00-0 1000
uu-u uuuu
INTCH
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
TBHP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000H
0000H
0000H
0000H
0000H
MP0
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
MP1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
STATUS
--00 xxxx
--1u uuuu
--uu uuuu
--01 uuuu
--11 uuuu
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
-uuu uuuu
Program
Counter
BP
INTCL
-000 0000
-000 0000
-000 0000
-000 0000
WDTS
0000 0111
0000 0111
0000 0111
0000 0111
uuuu uuuu
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PB
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PBC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PWMC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PWM
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
SERC
-111 1111
-111 1111
-111 1111
-111 1111
-111 1111
SERDATA
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
COL0
---0 0000
---0 0000
---0 0000
---0 0000
---0 0000
COL1
---0 0000
---0 0000
---0 0000
---0 0000
---0 0000
COL2
---0 0000
---0 0000
---0 0000
---0 0000
---0 0000
COL3
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
DAL
0000 ----
0000 ----
0000 ----
0000 ----
0000 ----
DAH
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
VOLC
0000 ----
0000 ----
0000 ----
0000 ----
0000 ----
PCC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PD
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PDC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PE
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PEC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
X¢TAL
0000 1100
0000 1100
0000 1100
0000 1100
0000 1100
Note:
²*² stands for ²warm reset²
²u² stands for ²unchange²
²x² stands for ²unknown²
²-² stands for ²unknown²
Rev. 1.20
21
July 5, 2002
HTG2190
ter 0; TMR0H (0CH), TMR0L (0DH), TMR0C (0EH).
Writing to TMR0L only writes the data into a low byte
buffer. Writing to TMR0H will write the data and the contents of the low byte buffer into the Timer/Event Counter
0 preload register (16-bit) simultaneously. The
Timer/Event Counter 0 preload register is changed only
by a write to TMR0H operation. Writing to TMR0L will
keep the Timer/Event Counter 0 preload register unchanged.
Timer/Event Counter 0/1
Two timer/event counters are implemented in the
HTG2190. The Timer/Event Counter 0 and 1 contain
16-bit programmable count-up counters whose clock
may come from an external source or the system clock
divided by 4. It should be noted that, if the Timer/Event
Counter 0 is selected, the TMR0 pin should be enabled
by mask option. The pull-high resistor can be disabled
or enabled by software instruction.
Reading TMR0H will also latch the TMR0L into the low
byte buffer to avoid false timing problems. Reading the
TMR0L only returns the value from the low byte buffer
which may be a previously loaded value. In other words,
the low byte of Timer/Event Counter 0 cannot be read di-
Using the internal instruction clock, there is only one reference time-base. The external clock input allows the
user to count external events, measure time intervals or
pulse width, or to generate an accurate time base.
There are three registers related to Timer/Event CounS y s te m
C lo c k /4
T M R 0
T M R 1
D a ta B u s
T M 1
T M 0
T im e r /E v e n t C o u n te r 0 /1
P r e lo a d R e g is te r
R e lo a d
T E
T M 1
T M 0
T O N
T im e r /E v e n t
C o u n te r 0 /1
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
O v e r flo w
to In te rru p t
L o w B y te
B u ffe r
Timer/Event Counter 0/1
Label
Bits
¾
0~2
Function
Unused bit, read as ²0²
TE
3
Defines the TMR0/TMR1 active edge of timer/event counter
(0=active on low to high; 1=active on high to low)
TON
4
Enable/disable timer counting
(0=disabled; 1=enabled)
¾
5
Unused bit, read as ²0²
TM1, TM0
7, 6
Define the operating mode (TM1, TM0)
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Unused
00=Unused
TMR0C/TMR1C register
Label
Bits
Function
FAST
0
0=speed-up 32K x'tal (default)
1=Non-speed-up 32K x'tal
RTF
1
Select the R-to-F function
0=disable R-to-F (default), 1=enable R-to-F
RTMR0
2
Select the TMR0 pull-high resistor (1=with pull-high; 0=without pull-high)
RTMR1
3
Select the TMR1 pull-high resistor (1=with pull-high; 0=without pull-high)
VDET
4
Supply voltage detection circuit (1=enable VDET, 0=disable VDET)
¾
5~7
Unused bit, read as ²0²
X'TALC register
Rev. 1.20
22
July 5, 2002
HTG2190
Low voltage detect function (LVD)
rectly. It must read the TMR0H first to ensure that the
low byte contents of Timer/Event Counter 0 are latched
into the buffer.
The HTG2190 provides low voltage detect to monitor
the supply voltage of devices. The user can use the
x¢talc.4 to enable/disable (1/0) the LVD function and
read the LVD detect status (0/1) from x¢talc.4 otherwise,
the LVD function is disabled. If the x¢talc.4 is ²1², means
low battery otherwise if still work (VD=(V22+150mV)±
100mV, VD means voltage detect value).
There are three registers related to the Timer/Event
Counter 1; TMR1H (0FH), TMR1L (10H), TMR1C (11H).
The Timer/Event Counter 1 operates in the same manner
as Timer/Event Counter 0.
The TMR0C is the Timer/Event Counter 0 control register, which defines the Timer/Event Counter 0 options.
The Timer/Event Counter 1 has the same options as the
Timer/Event Counter 0 and is defined by TMR1C.
R to F function
The HTG2190 provides an ²R to F² (Resistor to Frequency) function for temperature measurement and so
on.
The timer/event counter control registers define the operating mode, counting enable or disable and active
edge.
The application circuit is shown below.
The TM0, TM1 bits define the operating mode. The
event count mode is used to count external events,
which implies that the clock source comes from an external (TMR0/TMR1) pin. The timer mode functions as a
normal timer with the clock source coming from the instruction clock. The pulse width measurement mode
can be used to count the high or low level duration of an
external signal (TMR0/TMR1). The counting method is
based on the instruction clock.
P B 2
P B 3
H T G 2 1 9 0
T M R 1
C
R to F application circuit
In the event count or timer mode, once the timer/event
counter starts counting, it will count from the current
contents in the timer/event counter to FFFFH. Once
overflow occurs, the counter is reloaded from the
timer/event counter preload register and generates a
corresponding interrupt request flag (T0F/T1F; bit 5/6 of
INTC) at the same time.
V
D D
R T M R 1 ( X 'T A L C . 3 )
1
To enable the counting operation, the Timer ON bit
(TON; bit 4 of TMR0C/TMR1C) should be set to 1. In the
pulse width measurement mode, TON will be cleared
automatically after the measurement cycle is complete.
But in the other two modes TON can only be reset by instruction. The overflow of the timer/event counter is one
of the wake-up sources. No matter what the operation
mode is, writing a 0 to ET0I/ET1I can disable the corresponding interrupt service.
T o T im e r 1
M a x
0
T M R 1
S 1
R - F ( X 'T A L C . 1 )
R to F structure
In the case of a timer/event counter OFF condition, writing data to the timer/event counter preload register will
also reload that data to the timer/event counter. But if the
timer/event counter is turned on, data written to the
timer/event counter will only be kept in the
timer/event counter preload register. The timer/event
counter will continue to operate until an overflow occurs.
R1 is a fixed resistor about 10kW for reference, while R2
is a thermistor whose resistance is variable according to
the temperature. C is a capacitance about 2200pF for
charge and discharge purposes. It should be noted that,
if the R to F function is selected, the pull-high resistors of
TMR1. The TMR1 pull-high resistor can be disabled by
software instruction. The related frequency of R1 is
measured by setting PB3 to be an output pin and PB2 to
be an input pin. Then set the PB3 to be a source current
to charge the capacitance C. If the charged voltage ar-
When the timer/event counter (reading TMR0H/
TMR1H) is read, the clock will be blocked to avoid errors. As this may result in a counting error, this must
be taken into consideration by the programmer.
Rev. 1.20
R 2
R 1
23
July 5, 2002
HTG2190
rives as VIH (input high voltage) of S1 gate, the NMOS
will be turned on for discharge. The same manner can
be used for measuring the related frequency of R2, but
the roles of PB2 and PB3 should be exchanged.
V
to TMR2 location; writing to TMR2 makes the starting
value be placed in the Timer 2 preload register and
reading the TMR2 obtains the contents of the timer 2
counter. The TMR2C is a control register, which defines
the division ratio of the prescaler and counting enable or
disable.
IH
V
Writing data to B2, B1 and B0 (bit 2, 1, 0 of TMR2C) can
generate various clock source.
IL
Once the timer 2 starts counting, it will count from the
current contents in the counter to FFH. Once an overflow occurs, the counter is reloaded from the preload
register, and generates an interrupt request flag (T2F;
bit 4 of the INTCH). To enable the counting operation,
the timer on bit (TON ; bit 4 of TMR2C) should be set to
²1².
Charge/discharge waveform
During execution of R to F function, the TMR1 should be
set as event counter to count the charge/discharge
waveform. Since the falling edge of the charge/discharge waveform is sharper than the rising edge, it is
recommended that the active edge of the event counter
on high to low be defined by setting TE (bit 3 of TMR1C).
For proper operation, bit 6 of TMR2C should be set to
²1², and bit3, bit7 should be set to ²0².
For other detailed operation about Timer/Event Counter
1, refer to a related section of the Timer/Event Counter
0/1.
Timer 2 can also be used as a buzzer output by setting
PB.0 and AUD to be PWM1 and PWM2 output respectively by mask option. When the PWM1/PWM2 is selected, setting 2FH.6/2FH.7 to ²1² will select PFD/PFDB
output and setting 2FH.6/2FH.7 to ²0² will select
PWM1/PWM2 output. When the PFD/PFDB function is
selected, setting 2FH.4/2FH.5 to ²1² will enable
PFD/PFDB output and setting 2FH.4/2FH.5 to ²0² will
disable PFD/PFDB output. PFD Frequency= T2f/
[(256-TMR2)´2].
An example of a software program written for the purpose of measuring related frequency of R2 is shown below.
SET
PBC.3
; set PB.3 to be input pin
CLR
PBC.2
; set PB.2 to be output pin
SET
PB.2
; output source current at
PB.2
CLR
X¢TALC.3
; disable TMR1 pull-high
resistor
Mov
A, 48H
; set TMR1 to be event
counter
Mov
CLR
CLR
TMR1C, A
TMR1L
TMR1H
TMR2C
; and active edge on high to
low
; set TMR1L and TMR1H to
be ²00²
;
SET
TMR1C.4
; turn on TMR1
SET
XT¢ALC.1
; turn on R to F function
B1
B0
0
0
0
SYS CLK/2
0
0
1
SYS CLK/4
0
1
0
SYS CLK/8
0
1
1
SYS CLK/16
1
0
0
SYS CLK/32
1
0
1
SYS CLK/64
1
1
0
SYS CLK/128
1
1
1
SYS CLK/256
TMR2C Bit4 to enable/disable timer counting (0=disable;1=enable)
Timer 2/3
TMR2C Bit3, always write ²0²
Timer 2 is an 8-bit counter, and its clock source come
from the system clock divided by an 8-stage prescaler.
There are two registers related to timer 2 ; TMR2 (21H)
and TMR2C (22H). Two physical registers are mapped
TMR2C Bit5, always write ²0²
Rev. 1.20
T2f
B2
TMR2C Bit6, always write ²1²
TMR2C Bit7, always write ²0²
24
July 5, 2002
HTG2190
D a ta B u s
S y s te m
R e lo a d
T im e r 2
P r e lo a d R e g is te r
8 -s ta g e
P r e s c a le r
C lo c k
T o in te r r u p t
T 2 f
¸ 2
T im e r 2
T O N
O v e r flo w
2 F H .5
P W M 2
P W M D A C 2
2 F H .7
2 F H .4
P W M 1
P W M D A C 1
2 F H .6
Timer 2
S y s te m
C lo c k
8 S ta g e P r e s c a le r
F 0
n e a r 3 2 7 6 8 H z
P r e lo a d
m a s k o p tio n
T 3 f
F 1
8 S ta g e P r e s c a le r
3 2 K X 'A T L
T im e r 3
T O N
¸ 3 2
2 E H .7
* If
If
If
If
th
th
th
th
e 8
e 1
e 8
e 1
C O
6 C
C O
6 C
M B /W m o d
O M B /W m o
M E C B m o d
O M E C B m o
e is s
d e is
e is s
d e is
L C D D r iv e r
(1 0 2 4 H z )
*
e le c
s e le
e le c
s e le
te d
c te
te d
c te
, th e
d , th
, th e
d , th
IN T
v a
e v
v a
e v
lu e
a lu
lu e
a lu
o f
e o
o f
e o
th e
f th
th e
f th
d iv id e
e d iv id
d iv id e
e d iv id
r is 6
e r is
r is 2
e r is
4 .
3 2 .
.
1 .
Timer 3
Label
Bits
SSL3~0
3~0
PFD
PFDB
4
5
F1 can select 4 frequencies by mask option
Function
Auto Mask Option
LCD common used
Enable/disable PFD output
(0=disable, 1=enable)
System Clock near 512kHz
fSYS/16
System Clock near 1024kHz
fSYS/32
Enable/disable PFDB output
(0=disable, 1=enable)
System Clock near 2048kHz
fSYS/64
System Clock near 4096kHz
fSYS/128
PWM1
6
Select PFDB/PWM1 output
(0=PWM1, 1=PFDB)
PWM2
7
S el e c t P FD / P W M 2 o u t p u t
(0=PWM2, 1=PFD)
Time base frequency = T3f / (256 - TMR3)
TMR3C Bit 4 to enable/disable timer counting (0=disable; 1=enable)
TMR3C Bit6, always write ²1²
TMR3C Bit7, always write ²0²
TMR3C Bit 3, always write ²0²
COMR register
TMR3C
T3f
B2
B1
B0
0
0
0
F1/2
0
0
1
F1/4
0
1
0
F1/8
0
1
1
F1/16
1
0
0
F1/32
1
0
1
F1/64
1
1
0
F1/128
1
1
1
F1/256
Rev. 1.20
F0
Timer 3 has the same structure and operating manner
with timer 2, except for clock source and PFD function.
The timer 3 can be used as a time base to generate a
regular internal interrupt. The clock source of timer 3
can come from RTC OSC (X'tal 32kHz) or system clock
divided by an 8-stage prescaler. If the RTC mask option
is enabled, a 32kHz crystal is needed to connect across
XIN and XOUT pins. The 32kHz signal is processed by
an 8-stage prescaler to generate various counting clock
for timer 3. There are two registers related to timer 3;
TMR3 (24H) and TMR3C (25H). Writing data to B2, B1,
B0 (bit 2, 1, 0 of TMR3C) can generate various counting
clock.
25
July 5, 2002
HTG2190
Input/output ports
Each line of port A has a wake-up capability. PC, PD and
PE can be selected as segment output by mask option. If
the segment output is selected, the related I/O register
(PC, PD and PE) cannot be used as a general purpose
register. Reading the register will result to an unknown
state.
There are 39 bidirectional input/output lines in the
HTG2190, labeled from PA to PE, which are mapped to
the data memory of [12H], [14H], [16H], [18H], [1AH], respectively. All these I/O ports can be used for input and
output operations. For input operation, these ports are
non-latching, that is, the inputs must be ready at the T2
rising edge of instruction MOV A,[m] (m=12H, 14H, 16H,
18H, 1AH). For output operation, all data is latched and
remain unchanged until the output latch is rewritten.
PWM interface
The HTG2190 provides an 8 bit (bit7 is a sign bit) PWM
D/A interface, which is good for speech synthesis. The
user can record or synthesize the sound and digitize it
into the program ROM.
Each I/O line has its own control register (PAC, PCC,
PDC, PEC) which controls the input/output configuration. With this control register, CMOS output or Schmitt
trigger input with or without pull-high resistor structures
can be reconfigured dynamically (i.e., on-the-fly) under
software control. To function as an input, the corresponding latch of the control register must write ²1². The
pull-high resistance will be exhibited automatically if the
pull-high option is selected. The input source also depends on the control register. If the control register bit is
²1² input will read the pad state. If the control register bit
is ²0² the contents of the latches will move to the internal
bus. The latter is possible in ²read-modify-write² instruction. For output function, CMOS is the only configuration. These control registers are mapped to locations
13H, 15H, 17H, 19H, 1BH.
These sound could be played back in sequence of the
function as designed by the internal program ROM.
There are several algorithms that can be used in the
HTG2190, they are PCM, mLAW, DPCM, ADPCM.....
The PWM circuit provides two pad outputs: PWM2,
PWM1 which can directly drive a piezo or a 32W speaker
without adding any external element. Refer to the Application Circuits.
The PWM clock source comes from the system clock divided by a 3-bit prescaler. Setting data to P0, P1 and P2
(bit 3, 4, 5 of 27H) can generate various clock sources.
The clock source are used for PWM modulating clock
and sampling clock. After setting the start bit (bit 0 of
27H) and the next falling edge coming from the
prescaler, the ²DIV² will generate a serial clock to PWM
counter for modulation and PWMI for interrupt. The
PWM counter latch data at the first ²F1² clock falling
edge and the start counter at ²F1² rising edge. The
PWM base frequency is 32kHz. For every 32kHz latch
data once. The ²F2² clock is synchronous with the first
²F1² clock and it is also connected to the PWM output
latch. In setting the ²start bit² initial status, the ²PWM1
DAC² outputs a ²low² level and change the output status
to ²high² while the ²7-bit counter² overflows.
After a chip reset, these input/output lines stay at
Schmitt trigger input with pull-high resistor. Each bit of
these input/output latches can be set or cleared by the
SET [m].i or CLR [m].i (m=12H, 14H, 16H, 18H, 1AH) instruction.
Some instructions first input data and then follow the
output operations. For example, the SET [m].i, CLR
[m].i, CPL [m] and CPLA [m] instructions read the entire
port states into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
V
D
Q
D a ta B u s
C K
W r ite C o n tr o l R e g is te r
Q
S
V
C h ip R e s e t
M a s k O p tio n
R e a d C o n tr o l R e g is te r
D
W r ite I/O
P A 0
P B 0
P C 0
P D 0
P E 0
Q
C K
S
Q
M
R e a d I/O
S y s te m
D D
D D
W e a k
P u ll- u p
U
~ P
, P
~ P
~ P
~ P
A 7
B 2 ~ P B 7
C 7
D 7
E 7
X
W a k e - U p ( P A o n ly )
M a s k O p tio n
Input/output ports
Rev. 1.20
26
July 5, 2002
HTG2190
6/7
Bit
BZ/SP
F2
(Sampling
Rate)
F1
Bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Device
0
0
F0
F0/64
32W speaker
0
1
F0
F0/128
32W speaker
1
0
F0
F0/64
Buzzer/8W speaker
1
1
F0
F0/128
Buzzer/8W speaker
Bits
0
Enable/disable PWM output
0: enable, 1: disable
BZ/SP
1
Output driver select
1:buzzer ; 0:speaker
6/7 Bits
2
PWM counter bit select
1:7 bits ; 0:6 bits
P0~P2
3 bits preload counter
3~5 Bit543: 000B~111B (0~7)
Bit3: LSB
D0, D1
6, 7 PWMI
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
X
²X² stands for don¢t care
bit7: Sign bit
Serial I/O interface function
The serial interface of the HTG2190 has two types of operation mode: master mode and slave mode.
In the master mode, it uses an internal clock as synchronous clock. In the slave mode, the synchronous output
from the external (master side) serial device is input.
The master mode and slave mode are selected through
registers SERC.2 and SERC.3; when the master mode
is selected, a synchronous clock may be selected from
among 2 types as shown in table.
Function
PWM dis/EN
D6
Note:
On the above table, we can easily see that the sampling
rate is dependent on the system clock. If start bit is set to
²1², the PWM2 and PWM1 will output a GND level voltage.
Label
D7
6-bit
PWM data buffer
²F1² for PWM modulation clock and F2 for sampling clock
²F0² fSYS/(n+1) n=0~7 (n:3 bits preload counter)
Note:
7-bit
SERC.3
SERC.2
Mode
Synchronous
Clock
1
1
Slave mode
External clock
1
0
Master mode
SCLKS
0
1
Master mode
SCLKX
0
0
No used
PWMC register
D1
D0
PWM Interrupt
0
0
1
0
1
2
1
0
4
1
1
8
The ratio of latch to interrupt
F 0
P W M
d is /E N
L a tc h
3 2 k H z
1 2 8 c lo c k
F 1
F 2
O n e s a m p lin g tim e
7 bits PWM counter bit
Rev. 1.20
27
July 5, 2002
HTG2190
D a ta B u s
S y s te m
c lo c k
P W M D a ta
B u ffe r (2 8 H )
P r e s c a le r
F 0
S ta r t b it
2 7 H .0
P W M I
F 1
D iv .
D D
D
7 B its C o u n te r
C K
O v e r flo w
P E
F 2
V
Q
C K
Q
R
P W M D A C 1 fo r 3 2 W
S P K
P W M D A C 2 fo r 3 2 W
S P K
27H.1=0 speaker
D a ta B u s
S y s te m
C lo c k
F 0
S ta r t b it
2 7 H .0
P W M I
P W M D a ta
B u ffe r (2 8 H )
P r e s c a le r
D iv .
F 1
C K
D D
D
7 - b it C o u n te r
O v e r flo w
P E
F 2
V
Q
C K
Q
R
S ig n b it
P W M D A C 1 fo r B Z
P W M D A C 2 fo r B Z
27H.1=1 buzzer
SOUT is latch data at H to L by fixed mode
SERC
At initial reset, the slave mode (external clock mode) is
selected. Moreover, the synchronous clock, along with
the input/output of the 8 bits serial data, is controlled as
follows:
SCLKX
SCLKS
0
16K
fSYS/4
· At master mode, after output of 8 clock from the SCLK
1
8K
fSYS/8
b6
b5
b4
0
0
0
0
0
1
0
4K
fSYS/16
0
1
1
2K
fSYS/32
terminal, clock output is automatically suspended and
SCLK terminal is fixed at high level.
· At slave mode, after input of 8 clocks to the terminal,
subsequent clock inputs are masked.
1
0
0
1K
fSYS/64
Serial data output
1
0
1
512
fSYS/128
1
1
0
256
fSYS/256
1
1
1
128
fSYS/512
By setting the parallel data to serial data registers
SERDATA individually and writing ²0² to SERC.0, it synchronizes with the synchronous clock and serial data is
output at the SOUT terminal.
S C L K
C L K
S C L K
C L K
S O U T
S O U T
S O U T
S O U T
S IN
In p u t T e r m in a l
H T G 2 1 9 0
S IN
S IN
P B 2
P B 2
E x te rn a l
S e r ia l D e v ic e
H T G 2 1 9 0
(a ) M a s te r m o d e
Rev. 1.20
S IN
In p u t T e r m in a l
E x te rn a l
S e r ia l D e v ic e
( b ) S la v e m o d e
28
July 5, 2002
HTG2190
When the output of the 8 bits data from D0~D7 is completed, the interrupt factor flag is set to ²1² and interrupt
is generated. Moreover, the interrupt can be masked by
the interrupt mask register INTC.
The input data will be fetched at the rising edge (.1=²0²)
of SCLK. When the input of the 8 bits data from D0~D7
is completed, the interrupt factor flag EIF is set to ²1²
and interrupt is generated. Moreover, the interrupt can
be masked by the interrupt mask register SERDATA.
Note, however, that regardless of the setting of the interrupt mask register, the interrupt factor flag is set to ²1²
after input of the 8 bits data.
Note, however, that regardless of the setting of the interrupt mask register, the interrupt factor flag is set to ²1²
after output of the 8 bits data.
Serial data input
By writing ²0² to SERC.0, the serial data is input from
the SIN terminal, synchronizes with the synchronous
clock, and is sequentially read in the 8 bits shift register.
;* use master mode
;* serial clock=F1/2
;*
serial
equ
2Ah
;serialdatabuffer
serc
equ
29h
;serial control register
data
equ
51h
;
org
004h
jmp
serial_op
;serial
;
;
serialap:
;serial function testing (PA=16h)
mov
a,55h
mov
data,a
mov
serial,a
;write data to serial register
set
pbc
;set port B I/P
clr
pbc.5
;serial clock output
mov
a,00000111b
;SCLKX=F1/2
mov
serc,a
;latch data (h->1)
sz
pb.2
;
jmp
wait
set
EEI
clr
serc.0
;trigger the serial interface start
mov
a,data
;reload data to register
mov
serial,a
clr
serc.0
serail_I:
wait:
ret
serial_op:
;enable serial
ret
Rev. 1.20
29
July 5, 2002
HTG2190
;* use slave mode
;* serial clock=external clock
;*
org
004h
jmp
serial_ip
;serial interrupt
;
serialap:
;serial function testing (PA=16h)
clr
pac
;set port A O/P
mov
a,serial
;show initial data from serial buffer
mov
pa,a
set
pbc.5
set
serc.2
set
serc.3
;select salve mode
set
serc.1
;latch data (h->1)
clr
serc.0
;enable trigger
clr
pbc.2
;set pb.2 output pin
set
EEI
set
pb.2
sz
pb.2
jmp
wait
mov
a,data
;trigger the serial interface start
mov
pa,a
;show register data to port A
serial_i:
;serial clock input
wait:
;
ret
serial_ip:
mov
a,serial
mov
data,a
clr
pb.2
reti
Rev. 1.20
30
July 5, 2002
HTG2190
D B 7 ~ D B 0
S D 0 ~ S D 7
S IN
D 0
S e r io u s
M S B
B u ffe r
Q
D
D 7
S O U T
C
S 0
S 1
S 3
S E N
C lo c k
S e le c to r
F C L K
3 - b it
C o u n te r
In te rru p t
C o n tro l
IN T 0
C lo c k
C o n tro l
S C L K
S ta r tin g C o n tr o l
S IT R G
Serial I/O
IN P U T , S E N = 0
S IT R G
S C L K
S IN
B 7
B 6
B 5
B 4
B 3
B 2
B 1
B 0
B 7
B 6
B 5
B 4
B 3
B 2
B 1
B 0
S D 0
IN T 0
P B 2
IN P U T , S E N = 1
S IT R G
S C L K
S IN
S D 0
B 7
B 6
B 5
B 4
B 3
B 2
B 1
B 0
IN T 0
P B 2
O U T P U T
S IT R G
S C L K
S D 7
S O U T
B 7
B 6
B 7
B 5
B 6
B 4
B 3
B 5
B 4
B 2
B 3
B 1
B 2
B 0
B 1
B 0
IN T 0
N o te : * B 0 ~ B 7 m e a n s 8 b its
* * T h e s e r ia l d a ta tr a n s fe r fr o m
H i b it to L o w b it.
Serial data
Rev. 1.20
31
July 5, 2002
HTG2190
The audio output
Only 12 bits which include the high nibble of DAL and
the whole byte of DAH are used. The correct procedure
for DAC output as shown below, high nibble data of DAL
must be written next at first, and then the DAH data is
written.
D a ta B u s
D A H
(D 0 ~ D 7 )
C 1 1 ~ C 0
D A L
(D 4 ~ D 7 )
V O L C
(D 4 ~ D 7 )
D A C
A U D
P IN
There are 16 scales of volume controllable level that are
provided for the current type DAC output. The programmer only writes the volume control data to the VOLC
register (32H). Only the high nibble of VOLC are used.
Note that writing 0H to the high nibble of VOLC does not
denote mute output, this means there is still leakage
from AUD pin through external NPN transistor, and also
external 8W speaker leak current. Only load 00h to
DAH-DAL will turn off DAC and prevent leakage.
V 3 ~ V 0
The HTG2190 series provide a 12-bits current type DAC
devices for driving an external 8W speaker through an
external NPN transistor. The programmer must write the
voice data to the register DAL (30H) and DAH (31H).
Mask option
The following shows many kinds of mask options in the HTG2190. All these option should be defined on order to ensure proper system functioning.
No.
Mask Option
1
WDT enable or disable selection.
WDT can be enable or disable by mask option.
2
Wake-up selection. This option defines the wake-up function activity.
External I/O pins (PA only) all have the capability to wake-up the chip from a HALT mode by a following edge.
3
External interrupt input pin share with other function selection.
INT/SEG37: INT can be set as an external interrupt input pin or LCD segment output pin.
4
I/O pins share with other functions selection.
PB0/PWM1: PB0 can be set as I/O pin or positive audio PWM output pin.
PWM2/AUD: PWM2 can be set as negative PWM output pin or current type D/A output pin.
PB4/SOUT: PB4 can be set as I/O pin or serial data output pin.
PB5/SCLK: PB5 can be set as I/O pin or serial driving clock pin.
PB6/TMR1/RTF: PB6 can be set as I/O pin, Timer/Event Counter 1 input pin or resistor to frequency input pin.
PB7/TMR0: PB7 can be set as I/O pin or Timer/Event Counter 0 input pin.
5
I/O pins share with other function selection.
PC0/SEG56, PC1/SEG57, PC2/SEG58, PC3/SEG59, PC4/SEG60, PC5/SEG61: PC0~PC5 can be set as
I/O pins or LCD segment output pins.
PC6/SEG63/XIN, PC7/SEG62/XOUT: PC6, PC7 can be set as I/O pins, LCD segment output pins or XIN,
XOUT pins are connect to 32768Hz crystal.
6
Segment output pins share with other function selection.
SEG55~SEG48/PD7~PD0: SEG55~SEG48 can be set as LCD segment output pins or I/O pins.
SEG47~SEG40/PE7~PE0: SEG47~SEG40 can be set as LCD segment output pins or I/O pins
7
LCD common selection. There are two types of selection: 8-common or 16-common
8
LCD type selection. There are two types of selection: black/white LCD or color ECB
Rev. 1.20
32
July 5, 2002
HTG2190
Application Circuits
3 2
(fS
Y S
s p e a k e r /b u z z e r a p p lic a tio n
**
6 2 k W
= 4 M H z )
O S C I
C O M 0 ~ 1 5
S E G 0 ~ 6 3
(M a x .)
V
8
L C D
P A N E L
(fS
Y S
s p e a k e r a p p lic a tio n
**
6 2 k W
= 4 M H z )
3 0 k W
D D
P B 2
3 2 W S P K
o r B u z z e r
P B 3
P B 6 /T M R 1
P W M 2 /A U D
R E S
0 .1 m F
3 0 k W
2 2 0 0 p F
R E S
0 .1 m F
3 0 k W
L C D
P A N E L
C O M 0 ~ 1 5
S E G 0 ~ 6 3
(M a x .)
V
P W M 1 /P B 0
D D
O S C I
P B 2
P B 3
*
P B 6 /T M R 1
P A 0 ~ P A 7
3 0 k W
V
*
2 2 0 0 p F
X IN /S E G 6 3 /P C 7
D D
X IN /S E G 6 3 /P C 7
8 W
X O U T /S E G 6 2 /P C 6
X O U T /S E G 6 2 /P C 6
P W
IN T /S IN
P B 7 /T M R 0
M 2 /A U D
P B 7 /T M R 0
P B 5 /S C L K
C A P 1
P B 5 /S C L K
C A P 1
0 .1 m F
C A P 2
C A P 3
V O U T 1 1
C A P 4
V O U T 2 2
V O U T 3 3
V O U T 4 4
8 0 5 0
P B 4 /S O U T
P B 4 /S O U T
0 .1 m F
S P K
0 .1 m F
IN T /S IN
P A 0 ~ P A 7
2 k W
0 .1 m F
C A P 2
0 .1 m F
0 .1 m F
0 .1 m F
C A P 3
V O U T 1 1
C A P 4
V O U T 2 2
V O U T 3 3
0 .1 m F
V O U T 4 4
0 .1 m F
H T G 2 1 9 0
0 .1 m F
0 .1 m F
0 .1 m F
0 .1 m F
H T G 2 1 9 0
Note: * Optional capacitors can be added to get a more accurate frequency.
Since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropriate
value of external capacitors.
** R=100kW, fSYS=2MHz
R=200kW, fSYS=1MHz
Rev. 1.20
33
July 5, 2002
HTG2190
Instruction Set Summary
Description
Instruction
Cycle
Flag
Affected
Add data memory to ACC
Add ACC to data memory
Add immediate data to ACC
Add data memory to ACC with carry
Add ACC to data memory with carry
Subtract immediate data from ACC
Subtract data memory from ACC
Subtract data memory from ACC with result in data memory
Subtract data memory from ACC with carry
Subtract data memory from ACC with carry and result in data memory
Decimal adjust ACC for addition with result in data memory
1
1(1)
1
1
1(1)
1
1
1(1)
1
1(1)
1(1)
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
C
1
1
1
1(1)
1(1)
1(1)
1
1
1
1(1)
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Increment data memory with result in ACC
Increment data memory
Decrement data memory with result in ACC
Decrement data memory
1
1(1)
1
1(1)
Z
Z
Z
Z
Rotate data memory right with result in ACC
Rotate data memory right
Rotate data memory right through carry with result in ACC
Rotate data memory right through carry
Rotate data memory left with result in ACC
Rotate data memory left
Rotate data memory left through carry with result in ACC
Rotate data memory left through carry
1
1(1)
1
1(1)
1
1(1)
1
1(1)
None
None
C
C
None
None
C
C
Move data memory to ACC
Move ACC to data memory
Move immediate data to ACC
1
1(1)
1
None
None
None
Clear bit of data memory
Set bit of data memory
1(1)
1(1)
None
None
Mnemonic
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
AND data memory to ACC
OR data memory to ACC
Exclusive-OR data memory to ACC
AND ACC to data memory
OR ACC to data memory
Exclusive-OR ACC to data memory
AND immediate data to ACC
OR immediate data to ACC
Exclusive-OR immediate data to ACC
Complement data memory
Complement data memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Rev. 1.20
34
July 5, 2002
HTG2190
Instruction
Cycle
Flag
Affected
Jump unconditionally
Skip if data memory is zero
Skip if data memory is zero with data movement to ACC
Skip if bit i of data memory is zero
Skip if bit i of data memory is not zero
Skip if increment data memory is zero
Skip if decrement data memory is zero
Skip if increment data memory is zero with result in ACC
Skip if decrement data memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1(2)
1(2)
1(2)
1(2)
1(3)
1(3)
1(2)
1(2)
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read ROM code (current page) to data memory and TBLH
Read ROM code (last page) to data memory and TBLH
2(1)
2(1)
None
None
No operation
Clear data memory
Set data memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of data memory
Swap nibbles of data memory with result in ACC
Enter power down mode
1
1(1)
1(1)
1
1
1
1(1)
1
1
None
None
None
TO,PD
TO(4),PD(4)
TO(4),PD(4)
None
None
TO,PD
Mnemonic
Description
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note:
x: Immediate data
m: Data memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Ö: Flag is affected
-: Flag is not affected
(1)
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle
(four system clocks).
(2)
: If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more
cycle (four system clocks). Otherwise the original instruction cycle is unchanged.
(3) (1)
:
(4)
Rev. 1.20
and (2)
: The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the
CLR WDT1 or CLR WDT2 instruction, the TO and PD are cleared.
Otherwise the TO and PD flags remain unchanged.
35
July 5, 2002
HTG2190
Instruction Definition
ADC A,[m]
Add data memory and carry to the accumulator
Description
The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
ADCM A,[m]
Add the accumulator and carry to data memory
Description
The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
ADD A,[m]
Add data memory to the accumulator
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the accumulator.
Operation
ACC ¬ ACC+[m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
ADD A,x
Add immediate data to the accumulator
Description
The contents of the accumulator and the specified data are added, leaving the result in the
accumulator.
Operation
ACC ¬ ACC+x
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
ADDM A,[m]
Add the accumulator to the data memory
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the data memory.
Operation
[m] ¬ ACC+[m]
Affected flag(s)
Rev. 1.20
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
36
July 5, 2002
HTG2190
AND A,[m]
Logical AND accumulator with data memory
Description
Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
AND A,x
Logical AND immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_AND operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
ANDM A,[m]
Logical AND data memory with the accumulator
Description
Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
CALL addr
Subroutine call
Description
The instruction unconditionally calls a subroutine located at the indicated address. The
program counter increments once to obtain the address of the next instruction, and pushes
this onto the stack. The indicated address is then loaded. Program execution continues
with the instruction at this address.
Operation
Stack ¬ PC+1
PC ¬ addr
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
CLR [m]
Clear data memory
Description
The contents of the specified data memory are cleared to 0.
Operation
[m] ¬ 00H
Affected flag(s)
Rev. 1.20
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
37
July 5, 2002
HTG2190
CLR [m].i
Clear bit of data memory
Description
The bit i of the specified data memory is cleared to 0.
Operation
[m].i ¬ 0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
CLR WDT
Clear Watchdog Timer
Description
The WDT is cleared (clears the WDT). The power down bit (PD) and time-out bit (TO) are
cleared.
Operation
WDT ¬ 00H
PD and TO ¬ 0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
0
0
¾
¾
¾
¾
CLR WDT1
Preclear Watchdog Timer
Description
Together with CLR WDT2, clears the WDT. PD and TO are also cleared. Only execution of
this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PD flags remain unchanged.
Operation
WDT ¬ 00H*
PD and TO ¬ 0*
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
0*
0*
¾
¾
¾
¾
CLR WDT2
Preclear Watchdog Timer
Description
Together with CLR WDT1, clears the WDT. PD and TO are also cleared. Only execution of
this instruction without the other preclear instruction, sets the indicated flag which implies
this instruction has been executed and the TO and PD flags remain unchanged.
Operation
WDT ¬ 00H*
PD and TO ¬ 0*
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
0*
0*
¾
¾
¾
¾
CPL [m]
Complement data memory
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa.
Operation
[m] ¬ [m]
Affected flag(s)
Rev. 1.20
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
38
July 5, 2002
HTG2190
CPLA [m]
Complement data memory and place result in the accumulator
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa. The complemented result
is stored in the accumulator and the contents of the data memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
DAA [m]
Decimal-Adjust accumulator for addition
Description
The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal
carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a
carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored
in the data memory and only the carry flag (C) may be affected.
Operation
If ACC.3~ACC.0 >9 or AC=1
then [m].3~[m].0 ¬ (ACC.3~ACC.0)+6, AC1=AC
else [m].3~[m].0 ¬ (ACC.3~ACC.0), AC1=0
and
If ACC.7~ACC.4+AC1 >9 or C=1
then [m].7~[m].4 ¬ ACC.7~ACC.4+6+AC1,C=1
else [m].7~[m].4 ¬ ACC.7~ACC.4+AC1,C=C
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
Ö
DEC [m]
Decrement data memory
Description
Data in the specified data memory is decremented by 1.
Operation
[m] ¬ [m]-1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
DECA [m]
Decrement data memory and place result in the accumulator
Description
Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]-1
Affected flag(s)
Rev. 1.20
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
39
July 5, 2002
HTG2190
HALT
Enter power down mode
Description
This instruction stops program execution and turns off the system clock. The contents of
the RAM and registers are retained. The WDT and prescaler are cleared. The power down
bit (PD) is set and the WDT time-out bit (TO) is cleared.
Operation
PC ¬ PC+1
PD ¬ 1
TO ¬ 0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
0
1
¾
¾
¾
¾
INC [m]
Increment data memory
Description
Data in the specified data memory is incremented by 1
Operation
[m] ¬ [m]+1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
INCA [m]
Increment data memory and place result in the accumulator
Description
Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]+1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
JMP addr
Directly jump
Description
The program counter are replaced with the directly-specified address unconditionally, and
control is passed to this destination.
Operation
PC ¬addr
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
MOV A,[m]
Move data memory to the accumulator
Description
The contents of the specified data memory are copied to the accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
Rev. 1.20
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
40
July 5, 2002
HTG2190
MOV A,x
Move immediate data to the accumulator
Description
The 8-bit data specified by the code is loaded into the accumulator.
Operation
ACC ¬ x
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
MOV [m],A
Move the accumulator to data memory
Description
The contents of the accumulator are copied to the specified data memory (one of the data
memories).
Operation
[m] ¬ACC
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
PC ¬ PC+1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
OR A,[m]
Logical OR accumulator with data memory
Description
Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
OR A,x
Logical OR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_OR operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
ORM A,[m]
Logical OR data memory with the accumulator
Description
Data in the data memory (one of the data memories) and the accumulator perform a
bitwise logical_OR operation. The result is stored in the data memory.
Operation
[m] ¬ACC ²OR² [m]
Affected flag(s)
Rev. 1.20
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
41
July 5, 2002
HTG2190
RET
Return from subroutine
Description
The program counter is restored from the stack. This is a 2-cycle instruction.
Operation
PC ¬ Stack
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
RET A,x
Return and place immediate data in the accumulator
Description
The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data.
Operation
PC ¬ Stack
ACC ¬ x
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
RETI
Return from interrupt
Description
The program counter is restored from the stack, and interrupts are enabled by setting the
EMI bit. EMI is the enable master (global) interrupt bit.
Operation
PC ¬ Stack
EMI ¬ 1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
RL [m]
Rotate data memory left
Description
The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ [m].7
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
RLA [m]
Rotate data memory left and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the
rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ [m].7
Affected flag(s)
Rev. 1.20
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
42
July 5, 2002
HTG2190
RLC [m]
Rotate data memory left through carry
Description
The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
Ö
RLCA [m]
Rotate left through carry and place result in the accumulator
Description
Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the
carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored
in the accumulator but the contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
Ö
RR [m]
Rotate data memory right
Description
The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ [m].0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
RRA [m]
Rotate right and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving
the rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i) ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ [m].0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
RRC [m]
Rotate data memory right through carry
Description
The contents of the specified data memory and the carry flag are together rotated 1 bit
right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
Rev. 1.20
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
Ö
43
July 5, 2002
HTG2190
RRCA [m]
Rotate right through carry and place result in the accumulator
Description
Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces
the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is
stored in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
Ö
SBC A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
SBCM A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
SDZ [m]
Skip if decrement data memory is 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. If the result is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, [m] ¬ ([m]-1)
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SDZA [m]
Decrement data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. The result is stored in the accumulator but the data memory remains
unchanged. If the result is 0, the following instruction, fetched during the current instruction
execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, ACC ¬ ([m]-1)
Affected flag(s)
Rev. 1.20
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
44
July 5, 2002
HTG2190
SET [m]
Set data memory
Description
Each bit of the specified data memory is set to 1.
Operation
[m] ¬ FFH
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SET [m]. i
Set bit of data memory
Description
Bit i of the specified data memory is set to 1.
Operation
[m].i ¬ 1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SIZ [m]
Skip if increment data memory is 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a
dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with
the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, [m] ¬ ([m]+1)
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SIZA [m]
Increment data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the next
instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper
instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, ACC ¬ ([m]+1)
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SNZ [m].i
Skip if bit i of the data memory is not 0
Description
If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data
memory is not 0, the following instruction, fetched during the current instruction execution,
is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i¹0
Affected flag(s)
Rev. 1.20
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
45
July 5, 2002
HTG2190
SUB A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the accumulator.
Operation
ACC ¬ ACC+[m]+1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
SUBM A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the data memory.
Operation
[m] ¬ ACC+[m]+1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
SUB A,x
Subtract immediate data from the accumulator
Description
The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+x+1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
SWAP [m]
Swap nibbles within the data memory
Description
The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged.
Operation
[m].3~[m].0 « [m].7~[m].4
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SWAPA [m]
Swap data memory and place result in the accumulator
Description
The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.3~ACC.0 ¬ [m].7~[m].4
ACC.7~ACC.4 ¬ [m].3~[m].0
Affected flag(s)
Rev. 1.20
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
46
July 5, 2002
HTG2190
SZ [m]
Skip if data memory is 0
Description
If the contents of the specified data memory are 0, the following instruction, fetched during
the current instruction execution, is discarded and a dummy cycle is replaced to get the
proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SZA [m]
Move data memory to ACC, skip if 0
Description
The contents of the specified data memory are copied to the accumulator. If the contents is
0, the following instruction, fetched during the current instruction execution, is discarded
and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed
with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SZ [m].i
Skip if bit i of the data memory is 0
Description
If bit i of the specified data memory is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i=0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
TABRDC [m]
Move the ROM code (current page) to TBLH and data memory
Description
The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved
to the specified data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
TABRDL [m]
Move the ROM code (last page) to TBLH and data memory
Description
The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to
the data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
Rev. 1.20
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
47
July 5, 2002
HTG2190
XOR A,[m]
Logical XOR accumulator with data memory
Description
Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
XORM A,[m]
Logical XOR data memory with the accumulator
Description
Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
XOR A,x
Logical XOR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Rev. 1.20
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
48
July 5, 2002
HTG2190
Package Information
128-pin QFP (14´20) outline dimensions
C
H
D
1 0 2
G
6 5
I
6 4
1 0 3
F
A
B
E
1 2 8
3 9
=
K
J
3 8
1
Symbol
A
Rev. 1.20
Dimensions in mm
Min.
Nom.
Max.
17.00
¾
17.50
B
13.90
¾
14.10
C
23.00
¾
23.50
D
19.90
¾
20.10
E
¾
0.50
¾
F
¾
0.20
¾
G
2.50
¾
3.10
H
¾
¾
3.40
I
¾
0.10
¾
J
0.65
¾
0.95
K
0.10
¾
0.20
a
0°
¾
7°
49
July 5, 2002
HTG2190
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor Inc. (Shanghai Sales Office)
7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233
Tel: 021-6485-5560
Fax: 021-6485-0313
http://www.holtek.com.cn
Holtek Semiconductor Inc. (Shenzhen Sales Office)
5/F, Unit A, Productivity Building, Cross of Science M 3rd Road and Gaoxin M 2nd Road, Science Park, Nanshan District,
Shenzhen, China 518057
Tel: 0755-8616-9908, 8616-9308
Fax: 0755-8616-9533
Holtek Semiconductor Inc. (Beijing Sales Office)
Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031
Tel: 010-6641-0030, 6641-7751, 6641-7752
Fax: 010-6641-0125
Holtek Semiconductor Inc. (Chengdu Sales Office)
709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016
Tel: 028-6653-6590
Fax: 028-6653-6591
Holmate Semiconductor, Inc. (North America Sales Office)
46729 Fremont Blvd., Fremont, CA 94538
Tel: 510-252-9880
Fax: 510-252-9885
http://www.holmate.com
Copyright Ó 2002 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.20
50
July 5, 2002