STK10C68 ABSOLUTE MAXIMUM RATINGSa Note a: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Voltage on Input Relative to Ground . . . . . . . . . . . . . .–0.5V to 7.0V Voltage on Input Relative to VSS . . . . . . . . . . –0.6V to (VCC + 0.5V) Voltage on DQ0-7 . . . . . . . . . . . . . . . . . . . . . . –0.5V to (VCC + 0.5V) Temperature under Bias . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W DC Output Current (1 output at a time, 1s duration) . . . . . . . . 15mA (VCC = 5.0V ± 10%) DC CHARACTERISTICS SYMBOL INDUSTRIAL/ MILITARY COMMERCIAL PARAMETER MIN MAX ICC b Average VCC Current ICC c ICC b ISB d Average VCC Current (Standby, Cycling TTL Input Levels) ISB d VCC Standby Current (Standby, Stable CMOS Input Levels) IILK Input Leakage Current IOLK Off-State Output Leakage Current VIH Input Logic “1” Voltage 2.2 VCC + .5 VIL Input Logic “0” Voltage VSS – .5 0.8 1 2 3 1 2 VOH MIN UNITS NOTES MAX 85 75 65 N/A 90 75 65 55 mA mA mA mA tAVAV = 25ns tAVAV = 35ns tAVAV = 45ns tAVAV = 55ns Average VCC Current during STORE 3 3 mA All Inputs Don’t Care, VCC = max Average VCC Current at tAVAV = 200ns 5V, 25°C, Typical 10 10 mA W ≥ (V CC – 0.2V) All Others Cycling, CMOS Levels 27 23 20 N/A 28 24 21 20 mA mA mA mA tAVAV = 25ns, E ≥ VIH tAVAV = 35ns, E ≥ VIH tAVAV = 45ns, E ≥ VIH tAVAV = 55ns, E ≥ VIH 750 1500 µA E ≥ (V CC – 0.2V) All Others VIN ≤ 0.2V or ≥ (VCC – 0.2V) ±1 ±1 µA VCC = max VIN = VSS to VCC ±5 ±5 µA VCC = max VIN = VSS to VCC, E or G ≥ VIH 2.2 VCC + .5 V All Inputs VSS – .5 0.8 V All Inputs V IOUT = – 4mA 0.4 V IOUT = 8mA 85/125 °C Note a: Output Logic “1” Voltage VOL Output Logic “0” Voltage TA Operating Temperature 2.4 2.4 0.4 0 70 –40/-55 Note b: ICC and ICC are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded. 1 3 Note c: ICC is the average current required for the duration of the STORE cycle (tSTORE ) . 2 Note d: E ≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out. AC TEST CONDITIONS 5.0V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1 CAPACITANCEe SYMBOL 480 Ohms (TA = 25°C, f = 1.0MHz) PARAMETER MAX UNITS CONDITIONS CIN Input Capacitance 8 pF ∆V = 0 to 3V COUT Output Capacitance 7 pF ∆V = 0 to 3V OUTPUT 255 Ohms 30 pF INCLUDING SCOPE AND FIXTURE Note e: These parameters are guaranteed but not tested. Figure 1: AC Output Loading September 2003 2 Document Control # ML0006 rev 0.1 STK10C68 (VCC = 5.0V ± 10%) SRAM READ CYCLES #1 & #2 SYMBOLS NO. #1, #2 STK10C68-25 PARAMETER Alt. MIN MAX STK10C68-35 MIN MAX STK10C68-45 MIN STK10C68-55 MAX MIN MAX UNITS 1 tELQV tACS Chip Enable Access Time 2 tAVAVf tRC Read Cycle Time 3 tAVQVg tAA Address Access Time 25 35 45 55 ns 4 tGLQV tOE Output Enable to Data Valid 10 15 20 25 ns 5 tAXQXg tOH Output Hold after Address Change 5 5 5 5 6 tELQX tLZ Chip Enable to Output Active 5 5 5 5 7 tEHQZh tHZ Chip Disable to Output Inactive 8 tGLQX tOLZ Output Enable to Output Active 9 tGHQZh tOHZ Output Disable to Output Inactive 10 tELICCHe tPA Chip Enable to Power Active 11 tEHICCLd, e tPS Chip Disable to Power Standby 25 25 35 35 10 0 0 12 0 12 0 ns ns 12 ns 12 ns 55 ns ns 0 35 45 ns ns 0 10 0 25 55 55 10 10 0 45 45 ns Note f: W must be high during SRAM READ cycles and low during SRAM WRITE cycles. NE must be high during entire cycle. Note g: I/O state assumes E, G < VIL, W > VIH , and NE ≥ VIH; device is continuously selected. Note h: Measured + 200mV from steady state output voltage. SRAM READ CYCLE #1: Address Controlledf, g 2 tAVAV ADDRESS 3 tAVQV 5 tAXQX DQ (DATA OUT) DATA VALID SRAM READ CYCLE #2: E Controlledf 2 tAVAV ADDRESS 1 11 tELQV E tEHICCL 6 tELQX 7 tEHQZ G 9 tGHQZ 4 8 tGLQX tGLQV DQ (DATA OUT) DATA VALID 10 tELICCH ICC September 2003 ACTIVE STANDBY 3 Document Control # ML0006 rev 0.1 STK10C68 (VCC = 5.0V ± 10%) SRAM WRITE CYCLES #1 & #2 SYMBOLS NO. #1 #2 Alt. STK10C68-25 PARAMETER MIN MAX STK10C68-35 MIN MAX STK10C68-45 MIN MAX STK10C68-55 MIN MAX UNITS 12 tAVAV tAVAV tWC Write Cycle Time 25 35 45 55 ns 13 tWLWH tWLEH tWP Write Pulse Width 20 25 30 45 ns 14 tELWH tELEH tCW Chip Enable to End of Write 20 25 30 45 ns 15 tDVWH tDVEH tDW Data Set-up to End of Write 10 12 15 30 ns 16 tWHDX tEHDX tDH Data Hold after End of Write 0 0 0 0 ns 17 tAVWH tAVEH tAW Address Set-up to End of Write 20 25 30 45 ns 18 tAVWL tAVEL tAS Address Set-up to Start of Write 0 0 0 0 ns 19 tWHAX tEHAX tWR Address Hold after End of Write 0 20 tWLQZh, i tWZ Write Enable to Output Disable 21 tWHQX tOW Output Active after End of Write Note i: Note j: 0 10 5 0 0 13 5 14 5 ns 15 5 ns ns If W is low when E goes low, the outputs remain in the high-impedance state. E or W must be ≥ VIH during address transitions. NE ≥ VIH. SRAM WRITE CYCLE #1: W Controlledj 12 tAVAV ADDRESS 19 tWHAX 14 tELWH E 17 tAVWH 18 tAVWL 13 W tWLWH 16 tWHDX 15 tDVWH DATA IN DATA VALID 20 tWLQZ DATA OUT 21 tWHQX HIGH IMPEDANCE PREVIOUS DATA SRAM WRITE CYCLE #2: E Controlledj 12 tAVAV ADDRESS 18 19 14 tAVEL tEHAX tELEH E 17 tAVEH 13 W tWLEH 16 15 tEHDX tDVEH DATA IN DATA OUT September 2003 DATA VALID HIGH IMPEDANCE 4 Document Control # ML0006 rev 0.1 STK10C68 STORE INHIBIT/POWER-UP RECALL NO. SYMBOLS (VCC = 5.0V + 10%) STK10C68 PARAMETER Standard MIN MAX UNITS NOTES 22 tRESTORE Power-up RECALL Duration 550 µs 23 tSTORE STORE Cycle Duration 10 ms 24 VSWITCH Low Voltage Trigger Level 4.5 V 25 VRESET Low Voltage Reset Level 3.6 V Note k: 4.0 k tRESTORE starts from the time VCC rises above VSWITCH. STORE INHIBIT/POWER-UP RECALL VCC 5V 24 VSWITCH 25 VRESET STORE INHIBIT POWER-UP RECALL 22 tRESTORE DQ (DATA OUT) POWER-UP RECALL September 2003 BROWN OUT STORE INHIBIT BROWN OUT STORE INHIBIT BROWN OUT STORE INHIBIT NO RECALL (VCC DID NOT GO BELOW VRESET) NO RECALL (VCC DID NOT GO BELOW VRESET) RECALL WHEN VCC RETURNS ABOVE VSWITCH 5 Document Control # ML0006 rev 0.1 STK10C68 MODE SELECTION E Note l: W G NE MODE POWER H X L H X X Not Selected Standby L H Read SRAM L Active L X H Write SRAM Active L H L L Nonvolatile RECALLl Active L L H L Nonvolatile STORE ICC2 L L L H L H L X No Operation Active An automatic RECALL takes place at power up, starting when VCC exceeds 4.25V and taking tRESTORE. (VCC = 5.0V ± 10%) STORE CYCLES #1 & #2 NO. SYMBOLS #1 #2 PARAMETER Alt. 26 tWLQXm tELQX tSTORE STORE Cycle Time 27 tWLNHn tELNH tWC STORE Initiation Cycle Time 28 tGHNL 29 30 tNLWL 31 tELWL 32 MIN 20 MAX UNITS 10 ms ns Output Disable Set-up to NE Fall 0 ns tGHEL Output Disable Set-up to E Fall 0 ns tNLEL NE Set-up 0 ns Chip Enable Set-up 0 ns Write Enable Set-up 0 ns tWLEL Note m: Measured with W and NE both returned high, and G returned low. STORE cycles are inhibited below 4.0V. Note n: Once tWC has been satisfied by NE, G, W and E, the STORE cycle is completed automatically. Any of NE, G, W or E may be used to terminate the STORE initiation cycle. Note o: If E is low for any period of time in which W is high while G and NE are low, then a RECALL cycle may be initiated. STORE CYCLE #1: W Controlledo NE G 28 tGHNL 30 tNLWL 27 tWLNH W E DQ (DATA OUT) 31 tELWL 26 tWLQX HIGH IMPEDANCE STORE CYCLE #2: E Controlledo 30 tNLEL NE 29 tGHEL G W 32 tWLEL 27 tELNH E DQ (DATA OUT) September 2003 26 tELQX HIGH IMPEDANCE 6 Document Control # ML0006 rev 0.1 STK10C68 (VCC = 5.0V ± 10%) RECALL CYCLES #1, #2 & #3 NO. SYMBOLS #1 #2 PARAMETER #3 MIN MAX UNITS 20 µs 33 tNLQXp tELQXR tGLQXR RECALL Cycle Time 34 tNLNHq tELNHR tGLNH RECALL Initiation Cycle Time 20 ns tNLEL tNLGL NE Set-up 0 ns 35 36 tGLNL tGLEL Output Enable Set-up 0 ns 37 tWHNL tWHEL tWHGL Write Enable Set-up 0 ns 38 tELNL tGLEL tELGL Chip Enable Set-up 0 39 tNLQZ NE Fall to Outputs Inactive 20 ns 40 tRESTORE Power-up RECALL Duration 550 µs ns Note p: Measured with W and NE both high, and G and E low. Note q: Once tNLNH has been satisfied by NE, G, W and E, the RECALL cycle is completed automatically. Any of NE, G or E may be used to terminate the RECALL initiation cycle. Note r: If W is low at any point in which both E and NE are low and G is high, then a STORE cycle will be initiated instead of a RECALL. RECALL CYCLE #1: NE Controlledo 34 tNLNH NE 36 tGLNL G W 37 tWHNL E 38 tELNL 33 tNLQX 39 tNLQZ HIGH IMPEDANCE DQ (DATA OUT) RECALL CYCLE #2: E Controlledo 35 tNLEL NE G W E DQ (DATA OUT) 36 tGLEL 37 tWHEL 34 tELNHR 33 tELQXR HIGH IMPEDANCE RECALL CYCLE #3: G Controlledo, r 35 tNLGL NE G 34 tGLNH 37 tWHGL W E DQ (DATA OUT) September 2003 38 tELGL 33 tGLQXR HIGH IMPEDANCE 7 Document Control # ML0006 rev 0.1 STK10C68 DEVICE OPERATION NONVOLATILE STORE The STK10C68 has two modes of operation: SRAM mode and nonvolatile mode, determined by the state of the NE pin. When in SRAM mode, the memory operates as a standard fast static RAM. While in nonvolatile mode, data is transferred in parallel from SRAM to Nonvolatile Elements or from Nonvolatile Elements to SRAM. A STORE cycle is performed when NE, E and W and low and G is high. While any sequence that achieves this state will initiate a STORE, only W initiation (STORE cycle #1) and E initiation (STORE cycle #2) are practical without risking an unintentional SRAM WRITE that would disturb SRAM data. During a STORE cycle, previous nonvolatile data is erased and the SRAM contents are then programmed into nonvolatile elements. Once a STORE cycle is initiated, further input and output are disabled and the DQ0-7 pins are tri-stated until the cycle is complete. NOISE CONSIDERATIONS Note that the STK10C68 is a high-speed memory and so must have a high-frequency bypass capacitor of approximately 0.1µF connected between VCC and VSS, using leads and traces that are as short as possible. As with all high-speed CMOS ICs, normal careful routing of power, ground and signals will help prevent noise problems. If E and G are low and W and NE are high at the end of the cycle, a READ will be performed and the outputs will go active, signaling the end of the STORE. SRAM READ NONVOLATILE RECALL The STK10C68 performs a READ cycle whenever E and G are low and NE and W are high. The address specified on pins A0-12 determines which of the 8,192 data bytes will be accessed. When the READ is initiated by an address transition, the outputs will be valid after a delay of tAVQV (READ cycle #1). If the READ is initiated by E or G, the outputs will be valid at tELQV or at tGLQV, whichever is later (READ cycle #2). The data outputs will repeatedly respond to address changes within the tAVQV access time without the need for transitions on any control input pins, and will remain valid until another address change or until E or G is brought high or W or NE is brought low. A RECALL cycle is performed when E, G and NE are low and W is high. Like the STORE cycle, RECALL is initiated when the last of the four clock signals goes to the RECALL state. Once initiated, the RECALL cycle will take tNLQX to complete, during which all inputs are ignored. When the RECALL completes, any READ or WRITE state on the input pins will take effect. Internally, RECALL is a two-step procedure. First, the SRAM data is cleared, and second, the nonvolatile information is transferred into the SRAM cells. The RECALL operation in no way alters the data in the nonvolatile cells. The nonvolatile data can be recalled an unlimited number of times. SRAM WRITE As with the STORE cycle, a transition must occur on any one control pin to cause a RECALL, preventing inadvertent multi-triggering. On power up, once VCC exceeds the VCC sense voltage of 4.25V, a RECALL cycle is automatically initiated. Due to this automatic RECALL, SRAM operation cannot commence until tRESTORE after VCC exceeds approximately 4.25V. A WRITE cycle is performed whenever E and W are low and NE is high. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either E or W goes high at the end of the cycle. The data on pins DQ0-7 will be written into the memory if it is valid tDVWH before the end of a W controlled WRITE or tDVEH before the end of an E controlled WRITE. POWER-UP RECALL It is recommended that G be kept high during the entire WRITE cycle to avoid data bus contention on the common I/O lines. If G is left low, internal circuitry will turn off the output buffers tWLQZ after W goes low. September 2003 During power up, or after any low-power condition (VCC < 3.0V), an internal RECALL request will be latched. When VCC once again exceeds the sense voltage of 4.25V, a RECALL cycle will automatically be initiated and will take tRESTORE to complete. 8 Document Control # ML0006 rev 0.1 STK10C68 LOW AVERAGE ACTIVE POWER If the STK10C68 is in a WRITE state at the end of power-up RECALL, the SRAM data will be corrupted. To help avoid this situation, a 10K Ohm resistor should be connected either between W and system VCC or between E and system VCC. The STK10C68 draws significantly less current when it is cycled at times longer than 55ns. Figure 2 shows the relationship between ICC and READ cycle time. Worst-case current consumption is shown for both CMOS and TTL input levels (commercial temperature range, VCC = 5.5V, 100% duty cycle on chip enable). Figure 3 shows the same relationship for WRITE cycles. If the chip enable duty cycle is less than 100%, only standby current is drawn when the chip is disabled. The overall average current drawn by the STK10C68 depends on the following items: 1) CMOS vs. TTL input levels; 2) the duty cycle of chip enable; 3) the overall cycle rate for accesses; 4) the ratio of READs to WRITEs; 5) the operating temperature; 6) the VCC level; and 7) I/O loading. HARDWARE PROTECT 100 100 80 80 Average Active Current (mA) Average Active Current (mA) The STK10C68 offers two levels of protection to suppress inadvertent STORE cycles. If the control signals (E, G, W and NE) remain in the STORE condition at the end of a STORE cycle, a second STORE cycle will not be started. The STORE (or RECALL) will be initiated only after a transition on any one of these signals to the required state. In addition to multi-trigger protection, STOREs are inhibited when VCC is below 4.0V, protecting against inadvertent STOREs. 60 40 TTL 20 60 TTL 40 CMOS 20 CMOS 0 0 50 100 150 Cycle Time (ns) 200 50 Figure 2: ICC (max) Reads September 2003 100 150 Cycle Time (ns) 200 Figure 3: ICC (max) Writes 9 Document Control # ML0006 rev 0.1 STK10C68 ORDERING INFORMATION STK10C68 - 5 P F 45 I Temperature Range Blank = Commercial (0 to 70°C) I = Industrial (–40 to 85°C) M = Military (–55 to 125°C) Access Time 25 = 25ns 35 = 35ns 45 = 45ns 55 = 55ns (Military only) Lead Finish (Plastic only) Blank = 85%Sn/15%Pb F = 100% Sn (Matte Tin) Package P = Plastic 28-pin 300 mil DIP S = Plastic 28-pin 350 mil SOIC C = Ceramic 28-pin 300 mil DIP (gold lead finish) K = Ceramic 28-pin 300 mil DIP (solder dip finish) L = Ceramic 28 pin LCC Retention / Endurance Blank = Comm/Ind (100 years/106cycles) 5 = Military (10 years/105cycles) 5962-93056 04 MX X Lead Finish A = Solder DIP lead finish C = Gold lead DIP finish X = Lead finish “A” or “C” is acceptable Package MX = Ceramic 28 pin 300-mil DIP MY = Ceramic 28 pin LCC Access Time 04 = 55ns 05 = 45ns 06 = 35ns September 2003 10 Document Control # ML0006 rev 0.1 STK10C68 Document Revision History Date Revision Summary 0.0 December 2002 Combined commercial, industrial and military data sheets. Removed 20 nsec device. 0.1 September 2003 Added lead-free lead finish September 2003 11 Document Control # ML0006 rev 0.1 STK10C68 September 2003 12 Document Control # ML0006 rev 0.1