CS5828 28:4 LVDS Transmitter GENERAL DESCRIPTION FEATURES The CS5828 receives four sets of 7-bit data in CMOS logic level and converts them into four lowvoltage differential signaling (LVDS) serial channels. The 7-bit input data is referenced to the CKIN signal. The RF pin selects either rising or falling edge trigger of CKIN. Parallel to serial conversion is performed by a 7X internal generated clock reference using onchip PLL using CKIN. A copy of CKIN but phaselocked to the output serial streams, CLKOUT, is also converted to the fifth LVDS channel. The CS5828 offers a reliable communication media using LVDS signaling and provides low EMI dealing with wide, high-speed TTL interfaces. This is especially attractive for interfaces between GUI controller and display systems such as LCD panels for SVGA/XGA/SXGA applications. • Four 7-bit serial and one clock LVDS channels. • Compatible with ANSI TIA/EIA-644 LVDS standard. • Wide CKIN ranges from 31MHz to 85MHz. • Fully integrated on-chip PLL that provides 7X CKIN serial shift clock. • Pin selectable for rising or falling edge trigger. • Support power-down mode. • 5V/3.3V tolerant data input. • Single 3.3V supply operation. • CMOS low power consumption. • Functional compatible with DS90C385. • Available in 56-pin TSSOP package. BLOCK DIAGRAM D0,D1,D2,D3, D4,D6,D7 DIN PARALLEL-IN SERIAL-OUT 7-Bit SHIFT REGISTER SHIFT/LOAD_N CLK D8,D9,D12,D13, D14,D15,D18 DIN PARALLEL-IN SERIAL-OUT 7-Bit SHIFT REGISTER SHIFT/LOAD_N CLK D19,D20,D21,D22, D24,D25,D26 DIN DIN PARALLEL-IN SERIAL-OUT 7-Bit SHIFT REGISTER SHIFT/LOAD_N CLK RF CKIN 7xCLK PHASE LOCK LOOP SHIFT/LOAD_N R/F CLK SHTDN Y0N Y1P EN PARALLEL-IN SERIAL-OUT SHIFT/LOAD_N 7-Bit SHIFT REGISTER CLK D27,D5,D10,D11, D16,D17,D23 Y0P EN Y1N Y2P EN Y2N Y3P EN Y3N CKOP EN CKON CONTROL LOGIC CS5828 Myson Century, Inc. Taiwan: No. 2, Industry East Rd. III, Science-Based Industrial Park, Hsin-Chu, Taiwan Tel: 886-3-5784866 Fax: 886-3-5784349 USA: 4020 Moorpark Avenue Suite 115 San Jose, CA, 95117 Tel: 408-243-8388 Fax: 408-243-3188 [email protected] www.myson.com.tw Rev.1.4 August 2002 page 1 of 13 CS5828 PIN CONNECTION DIAGRAM VDD 1 56 D4 D5 2 55 D3 D6 3 54 D2 D7 4 53 VSS VSS 5 52 D1 D8 6 51 D0 D9 7 50 D27 D10 8 49 LVDS_VSS VDD 9 48 Y0M D11 10 47 Y0P D12 11 46 Y1M D13 12 45 Y1P VSS 13 44 LVDS_VDD D14 14 43 LVDS_VSS D15 15 42 Y2M D16 16 41 Y2P CS5828 RF 17 40 CKOM D17 18 39 CKOP D18 19 38 Y3M D19 20 37 Y3P VSS 21 36 LVDS_VSS D20 22 35 PLL_VSS D21 23 34 PLL_VDD D22 24 33 PLL_VSS D23 25 32 SHTDN VDD 26 31 CKIN D24 27 30 D26 D25 28 29 VSS Figure-1 56-pin TSSOP page 2 of 13 CS5828 PIN DESCRIPTION Name I/O Description D0,D1,D2,D3,D4, D6,D7 I Parallel data input for Y0 LVDS channel. D[0] is LSB and D[7] is MSB. MSB is shifted out first. D8,D9,D12,D13, D14,D15,D18 I Parallel data input for Y1 LVDS channel. D[8] is LSB and D[18] is MSB. D19,D20,D21,D22 ,D24,D25,D26 I Parallel data input for Y2 LVDS channel. D[19] is LSB and D[26] is MSB. D27,D5,D10,D11, D16,D17,D23 I Parallel data input for Y3 LVDS channel. D[27] is LSB and D[23] is MSB. CKIN I Parallel input clock.This clock signal is used for parallel data reference. It is also used by the on-chip PLL to generate the 7X shift clock for parallel to serial conversion. RF I Rise/fall select. This pin selects the polarity of the CKIN edge for data input. RF = 1 selects CKIN rise edge, and RF = 0 selects CKIN fall edge. SHTDN I Shutdown control (low active). When SHTDN is low, the internal PLL is put into inhibit mode and all LVDS output channels are shut off. This also resets all internal registers. For normal operation, SHTDN should be set to high. Y0P, Y0N O Y0 LVDS channel output. These are differential LVDS outputs for Y0 channel corresponds to D0, D1, D2, D3, D4, D6, D7. Y1P, Y1N O Y1 LVDS channel output. These are differential LVDS outputs for Y1 channel corresponds to D8, D9, D12, D13, D14, D15, D18. Y2P, Y2N O Y2 LVDS channel output. These are differential LVDS outputs for Y2 channel corresponds to D19, D20, D21,D22, D24, D25, D26. Y3P, Y3N O Y3 LVDS channel output. These are differential LVDS outputs for Y3 channel corresponds to D27, D5, D10, D11, D16, D17, D23. CKOP, CKON O Clock LVDS channel output. These are differential LVDS output for the replica of CKIN signal. CKOP and CKON are derived from the internal phase lock loop and phase aligned with the serial data output and can be used by the LVDS receiver for reference edge. PLL_VDD P Power supply for PLL circuit. PLL_VSS P Power ground for PLL circuit. LVDS_VDD P Power supply for output buffer circuits. LVDS_VSS P Power ground for output buffer circuits. VDD P Power supply for internal circuits. VSS P Power ground for internal circuits. page 3 of 13 CS5828 FUNCTIONAL DESCRIPTION Control logic There are two modes in this circuit. One is normal mode, and another is power down mode. Two modes are controlled by the control signal “SHTDN”. If SHTDN is high, the circuit is in the normal mode, else if low, the circuit is in the power down mode. In the power down mode, every block is off to make sure the least power consumption. 7 x CLK PLL 7 x CLK PLL, which is a phase lock loop, generates seven times clock of CKIN. The signal “RF” indicates that the input data (D0 ~ D27) is rising edge or falling edge trigger by CKIN. If RF=1, it is rising edge trigger, else if RF=0, it is falling trigger. This seven times clock of CKIN is used by the Parallel ~ LOAD 7 Bit shift Register. 7 x CLK PLL also generate the control signal “SHIFT/LOAD”. This signal is also used by the Parallel ~ LOAD 7 Bit Shift Register to indicate when to load data or shift data. Parallel ~ LOAD 7 Bit shift Register This block transfers 7 bits parallel data into one bit series data out. It is controlled by SHIFT/LOAD. If this control signal is low, the data are loaded into shift registers. Next, the SHIFT/LOAD turns high to shift data from shift register to output buffer seven times. One load and then seven shift. Ref: There are two properties in this block. One is that it supports reference voltage to fine the output’s common mode voltage. Another is that it generates about (4ns ~6ns) pulse width’s power on reset signal. When power on, all block would be reset by power on reset signal to make sure that the circuit would not stuck-at some situation we do not care. Output buffer There are four data output buffers and one clock output buffer. Output buffer generates differential pair output that swing is under 500 ~ 900mV, and common-mode voltage is under 1.125V ~ 1.375V. page 4 of 13 CS5828 RECOMMENDED OPERATING CONDITIONS Symbol Min Typ Max Unit VCC Supply voltage Parameter 3 3.3 3.6 V VIH High-level input voltage 2 - - V VIL Low-level input voltage - - 0.8 V ZL Differential load impedance 90 - 132 Ω TA Operating free-air temperature 0 - 70 °C Min Typ Max Unit TIMING REQUIREMENTS Symbol Parameter tC Input clock period 11.76 32.4 ns tW Pulse duration, high-level input clock 0.4tC 0.6tC ns tt Transition time, Input signal 5 ns tsu Setup time, data, D0~D27 valid before CKIN↓ (RF = 0) or CKIN↑(RF = 1) 3 ns th Hold time, data, D0~D27 valid after CKIN↓ (RF = 0) or CKIN↑(RF = 1) 1.5 ns page 5 of 13 CS5828 DC CHARACTERISTICS Symbol VIT Parameter Condition Input threshold voltage Typ Max Unit - 1.4 - V 247 340 454 mV - 10 50 mV VOD Differential steady-state output voltage magnitude ∆VOD Change in the steady-state differential output voltage magnitude between opposite binary states VOC(SS) Steady-state common-mode output voltage 1.125 - 1.375 V VOC(PP) Peak-to-peak common-mode output voltage - 80 150 mV VIH = VCC - - 20 µA IIH-SHTDN High level input current for SHTDN pin VIH = VCC - - 10 µA VIL = 0 - - ±10 µA VO(Yn) = 0 - - ±24 mA VOD = 0 - - ±12 mA IIH High-level input current RL = 100Ω Min IIL Low-level input current IOS Short-circuit output current IOZ High-impedance output current VO = 0 to VCC - - ±10 µA Quiescent supply current (average) Power down SHTDN = 0 - - 250 µA Enabled, RL = 100Ω (4 places) Gray_scale pattern VCC = 3.3V, tC = 11.76ns 40 60 mA Enabled, RL = 100Ω (4 places) Worst_case pattern tC = 11.76ns 50 75 mA 3 - pF ICC(AVG) CI Input capacitance - Note: All typical values are at VCC = 3.3V, TA = 25°C. page 6 of 13 CS5828 AC CHARACTERISTICS Symbol Parameter Condition Min Typ Max Unit -0.2 0 0.2 ns t0 CKO↑ to bit 0 t1 CKO↑ to bit 1 1/7tc-0.2 - 1/7tc+0.2 ns t2 CKO↑ to bit 2 2/7tc-0.2 - 2/7tc+0.2 ns t3 CKO↑ to bit 3 3/7tc-0.2 - 3/7tc+0.2 ns t4 CKO↑ to bit 4 4/7tc-0.2 - 4/7tc+0.2 ns t5 CKO↑ to bit 5 5/7tc-0.2 - 5/7tc+0.2 ns t6 CKO↑ to bit 6 6/7tc-0.2 - 6/7tc+0.2 ns tskew Output skew -0.2 - 0.2 ns ∆tc(o) Cycle time, Output clock jitter - ±100 - ps tw Pulse duration, high-level output clock - 4/7tc - ns tt Transition time, differential output voltage (tr or tf) 260 700 1500 ps Tc= 11.76 ns tenable Enable time, SHTDN↑ to phase lock (Yn valid) - 1 - ms tdisable Disable time, SHTDN↓ to off state (CKO low) - 250 - ns page 7 of 13 CS5828 tsu th Dn CKIN (RF=0) CKIN (RF=1) Note: Maximum value of tr, tf = 5ns Figure-2 Setup and Hold Time Definition 49.9Ω±1%(2 Places) YP VOD VOC YM CL=10pF Max (2 Places) (a) SCHEMATIC 100% 80% VOD(H) 0V VOD(L) tf 20% 0% tr VOC(PP) VOC(SS) VOC(SS) 0V (b) WAVEFORMS Figure-3 Test Load and Voltage Definitions for LVDS Outputs page 8 of 13 CS5828 TEST PATTERN CKIN D0, 8, 16 D1, 9, 17 D2, 10, 18 D3, 11, 19 D4-7, 12-15, 20-23 D24-27 Figure-4 16-Grayscale Testing Pattern Waveforms CKIN Even Dn Odd Dn Figure-5 The Worst-case Testing Pattern Waveforms CKO t0 Yn t1 t2 t3 t4 t5 t6 Figure-6 Timing Waveform’s Definitions page 9 of 13 CS5828 TYPICAL CHARACTERISTICS CKIN SHTDN tenable Yn valid valid valid Invalid Note: RF=1 Figure-7 Enabled Time Waveforms CKIN CKO tdisable SHTDN Note: RF=1 Figure-8 Disabled Time Waveforms page 10 of 13 CS5828 PACKAGE OUTLINE (56-pin TSSOP) D c E1 E L θ A2 A A1 e Symbol b Dimensions in Millimeters Dimensions in Inches MIN NOM MAX MIN NOM MAX A 1.05 - 1.20 0.041 - 0.047 A1 0.05 - 0.15 0.002 - 0.006 A2 - 0.90 - - 0.035 - b 0.17 0.20 0.27 0.007 0.008 0.010 c 0.09 0.15 0.20 0.004 0.006 0.008 D 13.90 14.00 14.10 0.547 0.551 0.555 E 7.80 8.10 8.40 0.307 0.319 0.330 E1 6.00 6.10 6.20 0.236 0.240 0.244 e - 0.50 - - 0.0197 - L 0.50 - 0.75 0.020 - 0.030 θ 0° - 7° 0° - 7° Note: The CS5828 products keep using the original Century logo. page 11 of 13 CS5828 PACKAGING SPECIFICATION P0 B T1 φ D0 B P2 A E F R0.3MAX 3.0 3.4 W B0 3.0 2.0 6.0 R0.1 6.8 Section A-A A φ D0 P1 R0.3 Typical 8.6 K1 T2 Chamfer Section B-B Dimension Symbol B0 φ D0 E F K1 P0 P1 P2 T1 T2 W Unit: mm 14.5 1.5 +0.1 -0 1.75 ±0.1 11.5 ±0.05 1.3 Max 4 ±0.2 12.0 ±0.1 2 ±0.05 0.3 ±0.05 1.8 Max 24.0 ±0.3 Standard Packing Quantity Carrier Tape Width Reel Size Pocket Pitch Leader No. of Pockets End No. of Pockets Quantity (Pcs/Reel) 24mm φ330mm 4mm 20 30 2500 Reel For Taping W1 D B E W2 C A Unit: mm A B C D E W1 W2 φ 330 +1 -4 φ100 ±0.1 13 +0.5 -0.2 20.2 ±0.8 2.0 ±0.5 24.8 +0.3 -0.2 30.2 Max page 12 of 13 CS5828 Leader Part And Taped End Leader Part Tape End 20 Vacant position 0 Top cover tape Pin1 30 Vacant position Unwinding Direction Approval Supplier For Packing Material Item Supplier Carrier Tape ADVANTEK Cover Tape ADVANTEK Plastic Reel ADVANTEK Ordering Information Part Number Prefix Part Type Package Type CS 5828 N:TSSOP page 13 of 13