SN65LVDS95 LVDS SERDES TRANSMITTER SLLS297F – MAY 1998 – REVISED FEBRUARY 2000 D D D D D D D D D D D D D D DGG PACKAGE (TOP VIEW) 21:3 Data Channel Compression at up to 1.36 Gigabits per Second Throughput Suited for Point-to-Point Subsystem Communication With Very Low EMI 21 Data Channels Plus Clock in Low-Voltage TTL and 3 Data Channels Plus Clock Out Low-Voltage Differential Operates From a Single 3.3-V Supply and 250 mW (Typ) 5-V Tolerant Data Inputs ’LVDS95 Has Rising Clock Edge Triggered Inputs Bus Pins Tolerate 6-kV HBM ESD Packaged in Thin Shrink Small-Outline Package With 20 Mil Terminal Pitch Consumes <1 mW When Disabled Wide Phase-Lock Input Frequency Range 20 MHz to 65 MHz No External Components Required for PLL Inputs Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard Industrial Temperature Qualified TA = – 40°C to 85°C Replacement for the National DS90CR215 D4 VCC D5 D6 GND D7 D8 VCC D9 D10 GND D11 D12 VCC D13 D14 GND D15 D16 D17 VCC D18 D19 GND 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 D3 D2 GND D1 D0 NC LVDSGND Y0M Y0P Y1M Y1P LVDSVCC LVDSGND Y2M Y2P CLKOUTM CLKOUTP LVDSGND PLLGND PLLVCC PLLGND SHTDN CLKIN D20 description The SN65LVDS95 LVDS serdes (serializer/deserializer) transmitter contains three 7-bit parallel-load serial-out shift registers, a 7× clock synthesizer, and four low-voltage differential signaling (LVDS) line drivers in a single integrated circuit. These functions allow 21 bits of single-ended LVTTL data to be synchronously transmitted over 4 balanced-pair conductors for receipt by a compatible receiver, such as the SN65LVDS96. When transmitting, data bits D0 through D20 are each loaded into registers of the SN65LVDS95 on the rising edge of the input clock signal (CLKIN). The frequency of CLKIN is multiplied seven times and then used to serially unload the data registers in 7-bit slices. The three serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN. The SN65LVDS95 requires no external components and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with data transmission transparent to the user(s). The only user intervention is the possible use of the shutdown/clear (SHTDN) active-low input to inhibit the clock and shut off the LVDS output drivers for lower power consumption. A low level on this signal clears all internal registers to a low level. The SN65LVDS95 is characterized for operation over ambient air temperatures of – 40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2000, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN65LVDS95 LVDS SERDES TRANSMITTER SLLS297F – MAY 1998 – REVISED FEBRUARY 2000 functional block diagram D0–6 D7–13 D14–20 7 7 7 Parallel-Load 7-Bit Shift Register A,B, ...G Serial/LOAD CLK Parallel-Load 7-Bit Shift Register A,B, ...G Serial/LOAD CLK Parallel-Load 7-Bit Shift Register A,B, ...G Serial/LOAD CLK Y0P Y0M Y1P Y1M Y2P Y2M Control Logic SHTDN CLKIN 2 7× Clock/PLL 7×CLK CLK CLKINH POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CLKOUTP CLKOUTM SN65LVDS95 LVDS SERDES TRANSMITTER SLLS297F – MAY 1998 – REVISED FEBRUARY 2000 Dn CLKIN ’LVDS95 CLKOUT Previous Cycle Current Cycle Y0 Next D6 D5 D4 D3 D2 D1 D0 D6+1 D13 D12 D11 D10 D9 D8 D7 D13+1 D20 D19 D18 D17 D16 D15 D14 D20+1 D0-1 Y1 D7-1 Y2 D14-1 Figure 1. ’LVDS95 Load and Shift Sequences equivalent input and output schematic diagrams VCC VCC D or SHTDN 50 Ω 10 kΩ 50 Ω YnP or YnM 7V 7V 300 kΩ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN65LVDS95 LVDS SERDES TRANSMITTER SLLS297F – MAY 1998 – REVISED FEBRUARY 2000 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4 V Voltage range at any output terminal, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Voltage range at any input terminal, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V Electrostatic discharge (see Note 2): Bus pins (Class 3A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 KV Bus pins (Class 2B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 V All pins (Class 3A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 KV All pins (Class 2B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 V Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (see Dissipation Rating Table) Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to the GND terminals. 2. This rating is measured using MIL-STD-883C Method, 3015.7. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR‡ ABOVE TA = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING DGG 1316 mW 13.1 mW/°C 724 mW 526 mW ‡ This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. recommended operating conditions MIN NOM MAX Supply voltage, VCC 3 3.3 3.6 High-level input voltage, VIH 2 Low-level input voltage, VIL Operating free-air temperature, TA 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 V V 0.8 Differential load impedance, ZL UNIT V 90 132 Ω – 40 85 °C SN65LVDS95 LVDS SERDES TRANSMITTER SLLS297F – MAY 1998 – REVISED FEBRUARY 2000 electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS VIT |VOD| Input voltage threshold ∆|VOD| Change in the steady-state differential output voltage magnitude between opposite binary states VOC(SS) VOC(PP) Steady-state common-mode output voltage IIH IIL High-level input current IOS Short circuit output current Short-circuit IOZ High-impedance state output current ICC(AVG) MIN TYP† MAX 1.4 Differential steady-state output voltage magnitude Peak-to-peak common-mode output voltage 247 RL = 100 Ω, 50 1.125 1.375 80 V mV 20 µA ±10 µA VOY = 0 V VOD = 0 V ±24 mA ±12 mA VO = 0 V to VCC ±10 µA Disabled, all inputs at GND 280 µA 110 mA Enabled, RL = 100 Ω (4 places), Worst-case pattern (see Figure 4), tc = 15.38 ns Quiescent current (average) mV 150 VIH = VCC VIL = 0 V Low-level input current V 454 See Figure 3 See Figure 3 UNIT 85 Ci Input capacitance † All typical values are VCC = 3.3 V, TA = 25°C. 3 pF timing requirements MIN NOM tc tc tw Input clock period 15.4 High-level input clock pulse width duration 0.4tc tt tsu Input signal transition time th Data hold time, D0 through D27 after CLKIN↑ (’95) (see Figure 2) Data setup time, D0 through D27 before CLKIN↑ (’95) (see Figure 2) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MAX UNIT 50 ns 0.6tc 5 ns ns 3 ns 1.5 ns 5 SN65LVDS95 LVDS SERDES TRANSMITTER SLLS297F – MAY 1998 – REVISED FEBRUARY 2000 switching characteristics over recommended operating conditions (unless otherwise noted) PARAMETER Delay time, CLKOUT serial bit position 0 t2 t3 Delay time, CLKOUT↑ serial bit position 2 t4 t5 Delay time, CLKOUT↑ serial bit position 4 t6 tsk(o) Delay time, CLKOUT↑ serial bit position 6 Delay time, CLKOUT↑ serial bit position 1 Delay time, CLKOUT↑ serial bit position 3 tc = 15.38 ns (±0.2%), |Input clock jitter| < 50 ps‡, See Figure 5 Delay time, CLKOUT↑ serial bit position 5 TYP† MAX UNIT 0 0.20 ns 1/7tc–0.20 2/7tc–0.20 1/7tc+0.20 2/7tc+0.20 ns 3/7tc–0.20 4/7tc–0.20 3/7tc+0.20 4/7tc+0.20 ns 5/7tc–0.20 6/7tc–0.20 5/7tc+0.20 6/7tc+0.20 ns –0.20 0.20 ns Output skew, tn –n/7 tc t7 Delay time, CLKIN↑ to CLKOUT↑ ∆tC(O) tw tt MIN –0.20 TEST CONDITIONS t0 t1 Output clock cycle-to-cycle cycle to cycle jitter§ ns ns tc = 15.38 ns (±0.2%), |Input clock jitter| < 50 ps‡, See Figure 5 4.2 ns tc = 15.38 ns + 0.75 sin(2π500E3t) ±0.05 ns, See Figure 6 ±80 ps ±300 ps tc = 15.38 ns + 0.75 sin(2π2E6t) ±0.05 ns, See Figure 6 High-level output clock pulse duration 4/7 tc Differential output voltage transition time (tr or tf) ns See Figure 3 260 ns 700 1500 ten Enable time, SHTDN↑ to phase lock (Yn valid) See Figure 7 1 tdis Disable time, SHTDN↓ to off-state (CLKOUT low) See Figure 8 250 † All typical values are VCC = 3.3 V, TA = 25°C. ‡ |Input clock jitter| is the magnitude of the change in the input clock period. § The output clock jitter is the change in the output clock period from one cycle to the next cycle observed over 15,000 cycles. ps ms ns PARAMETER MEASUREMENT INFORMATION Dn ÉÉÉÉÉÉ ÉÉÉÉÉÉ tsu th ÉÉÉÉ ÉÉÉÉ CLKIN CLKSEL HIGH NOTE: All input timing is defined at 1.4 V on an input signal with a 10% to 90% rise or fall time of less than 5 ns. Figure 2. Setup and Hold Time Definition 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN65LVDS95 LVDS SERDES TRANSMITTER SLLS297F – MAY 1998 – REVISED FEBRUARY 2000 PARAMETER MEASUREMENT INFORMATION 49.9 Ω ±1% (2 Places) YP VID YM CL = 10 pF MAX (2 Places) VOC NOTE: The lumped instrumentation capacitance for any single ended voltage measurement is less than or equal to 10 pF. When making measurements at YP or YM, the complementary output shall be similarly loaded. 100% 80% VOD(H) 0V VOD(L) 20% 0% tr tf VOC(PP) VOC(SS) VOC(SS) 0V Figure 3. Test Load and Voltage Definitions for LVDS Outputs VIH = 2 V and VIL = 0.8 V T CLKIN EVEN Dn ODD Dn Figure 4. Worst-Case‡ Power Test Pattern ‡ The worst-case test pattern produces nearly the maximum switching frequency for all of the LV-TTL outputs. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN65LVDS95 LVDS SERDES TRANSMITTER SLLS297F – MAY 1998 – REVISED FEBRUARY 2000 PARAMETER MEASUREMENT INFORMATION t7 CLKIN CLKOUT t6 t5 t4 t3 t2 t1 t0 Yn t7 VOD(H) CLKIN 1.4 V 0V CLKOUT or Xn VOD(L) t0–t6 Figure 5. Timing Definitions Reference + Σ Device Under Test VCO + Modulation v(t) = A sin(2πfmodt) HP8656B Signal Generator, 0.1 MHz–990 MHz RF Output HP8665A Synthesized Signal Generator, 0.1 MHz–4200 MHz Modulation Input Output Device Under Test CLKIN CLKOUT Figure 6. Clock Jitter Test Setup 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DTS2070C Digital Time Scope Input SN65LVDS95 LVDS SERDES TRANSMITTER SLLS297F – MAY 1998 – REVISED FEBRUARY 2000 PARAMETER MEASUREMENT INFORMATION CLKIN Dn ten SHTDN Invalid Yn Valid Figure 7. Enable Time Measurement Definition CLKIN tdis SHTDN CLKOUT Figure 8. Disable Time Measurement Definition TYPICAL CHARACTERISTICS WORST-CASE SUPPLY CURRENT vs FREQUENCY 100 I CC – Supply Current – mA VCC = 3.6 V ÁÁ ÁÁ 80 60 VCC = 3 V VCC = 3.3 V 40 20 0 30 40 50 60 f – Frequency – MHz 70 Figure 9 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SN65LVDS95 LVDS SERDES TRANSMITTER SLLS297F – MAY 1998 – REVISED FEBRUARY 2000 APPLICATION INFORMATION 16-bit bus extension In a 16-bit bus application (Figure 10), TTL data and clock coming from bus transceivers that interface the backplane bus arrive at the Tx parallel inputs of the LVDS serdes transmitter. The clock associated with the bus is also connected to the device. The on-chip PLL synchronizes this clock with the parallel data at the input. The data is then multiplexed into three different line drivers which perform the TTL to LVDS conversion. The clock is also converted to LVDS and presented to a separate driver. This synchronized LVDS data and clock at the receiver, which recovers the LVDS data and clock, performs a conversion back to TTL. Data is then demultiplexed into a parallel format. An on-chip PLL synchronizes the received clock with the parallel data, and then all are presented to the parallel output port of the receiver. 16-Bit BTL Bus Interface SN74FB2032 SN74FB2032 CLK TTL Interface LVDS Interface 0 To 10 Meters (Media Dependent) SN65LVDS95 SN65LVDS96 TTL Interface D0–D7 8 8 D8–D15 8 8 D8–D15 D0–D7 16-Bit BTL Bus Interface SN74FB2032 SN74FB2032 XMIT Clock RCV Clock CLK Backplane Bus Backplane Bus Figure 10. 16-Bit Bus Extension 16-bit bus extension with parity In the previous application we did not have a checking bit that would provide assurance that the data crosses the link. If we add a parity bit to the previous example, we would have a diagram similar to the one in Figure 11. The device following the SN74FB2032 is a low cost parity generator. Each transmit-side transceiver/parity generator takes the LVTTL data from the corresponding transceiver, performs a parity calculation over the byte, and then passes the bits with its calculated parity value on the parallel input of the LVDS serdes transmitter. Again, the on-chip PLL synchronizes this transmit clock with the eighteen parallel bits (16 data + 2 parity) at the input. The synchronized LVDS data/parity and clock arrive at the receiver. The receiver performs the conversion from LVDS to LVTTL and the transceiver/parity generator performs the parity calculations. These devices compare their corresponding input bytes with the value received on the parity bit. The transceiver/parity generator will assert its parity error output if a mismatch is detected. 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN65LVDS95 LVDS SERDES TRANSMITTER SLLS297F – MAY 1998 – REVISED FEBRUARY 2000 APPLICATION INFORMATION 16-Bit BTL Bus Interface LVDS Interface 0 To 10 Meters (Media Dependent) TTL Interface W/Parity TTL Interface SN65LVDS95 SN74FB2032 9 Bit Latchable Transceiver/ With Parity Generator 8 Parity Parity 8 D8–D15 SN74FB2032 9 Bit Latchable Transceiver/ With Parity Generator TTL Interface 16-Bit BTL Bus Interface SN65LVDS96 8 D0–D7 TTL Interface W/Parity D0–D7 9 Bit Latchable Transceiver/ With Parity Generator 8 Parity Parity SN74FB2032 D8–D15 9 Bit Latchable Transceiver/ With Parity Generator SN74FB2032 Parity Error CLK XMIT Clock CLK RCV Clock Backplane Bus Backplane Bus Figure 11. 16-Bit Bus Extension With Parity low cost virtual backplane transceiver Figure 12 represents LVDS serdes in an application as a virtual backplane transceiver (VBT). The concept of a VBT can be achieved by implementing individual LVDS serdes chipsets in both directions of subsystem serialized links. Depending on the application, the designer will face varying choices when implementing a VBT. In addition to the devices shown in Figure 12, functions such as parity and delay lines for control signals could be included. Using additional circuitry, half-duplex or full-duplex operation can be achieved by configuring the clock and control lines properly. The designer may choose to implement an independent clock oscillator at each end of the link and then use a PLL to synchronize LVDS serdes’s parallel I/O to the backplane bus. Resynchronizing FIFOs may also be required. Bus Transceivers LVDS Serdes Transmitter TTL Inputs Up To 21 or 28 Bits Backplane Bus Bus Transceivers LVDS Serdes Receiver TTL Outputs Up To 21 or 28 Bits LVDS Serial Links 4 or 5 Pairs LVDS Serdes Transmitter Bus Transceivers LVDS Serdes Receiver Backplane Bus Bus Transceivers Figure 12. Virtual Backplane Transceiver POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 SN65LVDS95 LVDS SERDES TRANSMITTER SLLS297F – MAY 1998 – REVISED FEBRUARY 2000 MECHANICAL DATA DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PIN SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. 12 All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold protrusion not to exceed 0,15. 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