Agilent HCPL-5120 & HCPL-5121 DSCC SMD 5962-04204 2.0 Amp Output Current IGBT Gate Drive Optocoupler Data Sheet Description The HCPL- 5120 contains a GaAsP LED optically coupled to an integrated circuit with a power output stage. The device is ideally suited for driving power IGBTs and MOSFETs used in motor control inverter applications. The high operating voltage range of the output stage provides the drive voltages required by gate controlled devices. The voltage and current supplied by this optocoupler makes it ideally suited for directly driving IGBTs with ratings up to 1200 V/100 A. For IGBTs with higher ratings, the HCPL- 5120 can be used to drive a discrete power stage, which drives the IGBT gate. The products are capable of operation and storage over the full military temperature range and can be purchased as either commercial products, with full MIL- PRF- 38534 Class H testing, or from Defense Supply Center Columbus (DSCC) Standard Microcircuit Drawing (SMD) 5962- 04204. All devices are manufactured and tested on a MIL- PRF- 38534 certified line and are included in the DSCC Qualified Manufacturers List, QML- 38534 for Hybrid Microcircuits. Features Schematic Diagram • Hermetically Sealed Packages N/C 1 8 VCC ANODE 2 7 VO CATHODE 3 6 VO • Performance Guaranteed over Full Military Temperature Range: -55°C to +125°C • Manufactured and Tested on a MILPRF-38534 Certified Line • Dual Marked with Device Part Number and DSCC Drawing Number • QML-38534 N/C 4 SHIELD 5 VEE Applications • Industrial and Military Environments • High Reliability Systems • Harsh Industrial Environments • Transportation, Medical, and Life Critical Systems • Uninterruptible Power Supplies (UPS) • HCPL-3120 Function Compatibility • 2.0 A Minimum Peak Output Current • 0.5V Maximum Low Level Output Voltage (VOL) Eliminates Need for Negative Gate Drive • 10 kV/µs Minimum Common Mode Rejection (CMR) at VCM = 1000V • ICC = 5 mA Maximum Supply Current • Under Voltage Lock-Out Protection (UVLO) with Hysteresis • Wide Operating VCC Range: 15 to 30 Volts • 500 ns Maximum Propagation Delay • Isolated IGBT/MOSFET Gate Drive • AC and Brushless DC Motor Drives • ± 0.35µs Maximun Delay Between Devices • Industrial Inverters • Switch Mode Power Supplies (SMPS) CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. Selection Guide − Package Styles and Lead Configuration Options Truth Table VCC − VEE “POSITIVE GOING” (i.e., TURN-ON) VCC − VEE “NEGATIVE GOING” (i.e., TURN-OFF) VO OFF 0 − 30 V 0 − 30 V LOW ON 0 − 11 V 0 − 9.5 V LOW ON 11 − 13.5 V 9.5 − 12 V TRANSITION ON 13.5 − 30 V 12 − 30 V HIGH LED Agilent Part Number and Options Commercial HCPL-5120 MIL-PRF-38534, Class H HCPL-5121 A 0.1 µF bypass capacitor must be connected between pins 5 and 8. Standard Lead Finish Gold Plate Solder Dipped Option −200 Butt Cut/Gold Plate Option −100 Gull Wing/Soldered Option −300 SMD Part Number Device Marking Agilent DESIGNATOR Agilent P/N DSCC SMD* DSCC SMD* PIN ONE/ ESD IDENT A QYYWWZ HCPL-512x 5962-04204 SGP 01Hxx 50434 COMPLIANCE INDICATOR,* DATE CODE, SUFFIX (IF NEEDED) COUNTRY OF MFR. Agilent CAGE CODE* * QUALIFIED PARTS ONLY Outline Drawing 9.40 (0.370) 9.91 (0.390) 0.76 (0.030) 1.27 (0.050) 8.13 (0.320) MAX. 7.16 (0.282) 7.57 (0.298) 4.32 (0.170) MAX. 0.51 (0.020) MIN. 2.29 (0.090) 2.79 (0.110) 3.81 (0.150) MIN. 0.51 (0.020) MAX. NOTE: DIMENSIONS IN MILLIMETERS (INCHES). 2 0.20 (0.008) 0.33 (0.013) 7.36 (0.290) 7.87 (0.310) Prescript for all below 5962- Either Gold or Solder 0420401HPX Gold Plate 0420401HPC Solder Dipped 0420401HPA Butt Cut/Gold Plate 0420401HYC Butt Cut/Soldered 0420401HYA Gull Wing/Soldered 0420401HXA Hermetic Optocoupler Options Option Description 100 Surface mountable hermetic optocoupler with leads trimmed for butt joint assembly. This option is available on commercial and hi-rel product (see drawings below for details). 4.32 (0.170) MAX. 0.51 (0.020) MIN. 1.14 (0.045) 1.40 (0.055) 2.29 (0.090) 2.79 (0.110) 0.20 (0.008) 0.33 (0.013) 0.51 (0.020) MAX. 7.36 (0.290) 7.87 (0.310) NOTE: DIMENSIONS IN MILLIMETERS (INCHES). 200 Lead finish is solder dipped rather than gold plated. This option is available on commercial and hi-rel product. DSCC Drawing part numbers contain provisions for lead finish. 300 Surface mountable hermetic optocoupler with leads cut and bent for gull wing assembly. This option is available on commercial and hi-rel product (see drawings below for details). This option has solder dipped leads. 4.57 (0.180) MAX. 0.51 (0.020) MIN. 2.29 (0.090) 2.79 (0.110) 1.40 (0.055) 1.65 (0.065) 4.57 (0.180) MAX. 5° MAX. 0.51 (0.020) MAX. 0.20 (0.008) 0.33 (0.013) 9.65 (0.380) 9.91 (0.390) NOTE: DIMENSIONS IN MILLIMETERS (INCHES). 3 Absolute Maximum Ratings Parameter Symbol Min. Max. Units Storage Temperature TS -65 +150 °C Operating Temperature TA -55 +125 °C Case Temperature TC +145 °C Junction Temperature TJ +150 °C 260 for 10s °C Lead Solder Temperature Note Average Input Current IF AVG 25 mA 1 Peak Transient Input Current (<1 µs pulse width, 300 pps) IF PK 1.0 A Reverse Input Voltage VR 5 V “High” Peak Output Current IOH (PEAK) 2.5 A 2 “Low” Peak Output Current IOL (PEAK) 2.5 A 2 Supply Voltage (VCC-VEE) 0 35 V Output Voltage VO (PEAK) 0 VCC V Emitter Power Dissipation PE 45 mW 1 Output Power Dissipation PO 250 mW 3 Total Power Dissipation PT 295 mW 4 Notes: 1. No derating required for typical case-to-ambient thermal resistance (θCA=140°C/W). Refer to Figure 35. 2. Maximum pulse width = 10µs, maximum duty cycle = 0.2%. This value is intended to allow for component tolerances for designs with IO peak minimum = 2.0A. See Applications section for additional details on limiting IOH peak. 3. Derate linearly above 102°C free air temperature at a rate of 6mW/°C for typical case-to-ambient thermal resistance (θCA=140°C/W). Refer to Figure 36. 4. Derate linearly above 102°C free air temperature at a rate of 6mW/°C for typical case-to-ambient thermal resistance (θCA=140°C/W). Refer to Figure 35 and 36. ESD Classification MIL-STD-883, Method 3015 (▲), Class 1 Recommended Operating Conditions Parameter Symbol Min. Max. Units Power Supply Voltage (VCC – VEE) 15 30 Volts Input Current (ON) IF (ON) 10 18 mA Input Voltage (OFF) VF (OFF) -3.0 0.8 Volts Operating Temperature TA -55 125 °C 4 Electrical Specifications (DC) Over recommended operating conditions (TA = -55 to +125°C, IF(ON) = 10 to 18 mA, VF(OFF) = -3.0 to 0.8V, VCC = 15 to 30 V, VEE = Ground), unless otherwise specified. Parameter Symbol High Level Output Current IOH Low Level Output Current IOL High Level Output Voltage VOH Low Level Output Voltage VOL High Level Supply Current ICCH Low Level Supply Current ICCL Test Conditions VO = (VCC − 4 V) VO = (VCC − 15 V) 1, 2, 3 VO = (VEE + 2.5 V) VO = (VEE + 15 V) Limits Min. Typ.* 0.5 1.5 2.0 0.5 1, 2, 3 Fig Note A 2, 3, 17 2 A 2.0 A 2.0 1 5, 6, 18 A (VCC - 4) (VCC − 3) IO = -100 mA Units Max. 2 1 V 1, 3, 19 3, 4 1, 2, 3 IO = 100 mA 0.1 0.5 V 4, 6, 20 2.5 5.0 mA 7, 8 2.5 5.0 mA 3.5 9.0 mA 1, 2, 3 Threshold Input Cur- IFLH rent Low to High Output Open, IF = 10 to 18 mA 1, 2, 3 Output Open, VF = -3.0 to +0.8V 1, 2, 3 IO = 0 mA, VO > 5 V 1, 2, 3 Threshold Input VFHL Voltage High to Low Input Forward Voltage VF Temperature Coefficient of Forward Voltage ∆VF/∆TA 0.8 9, 15, 21 V 1, 2, 3 IF = 10 mA 1.2 1.5 1.8 V 16 1, 2, 3 IF = 10 mA Input Reverse BVR Breakdown Voltage IR = 10 µA Input Capacitance CIN f = 1 MHz, VF = 0 V UVLO Threshold VUVLO+ VO > 5 V, IF = 10 mA VUVLOUVLO Hysteresis Group A Subgroups (13) mV/°C -1.6 5 V 1, 2, 3 80 pF 1, 2, 3 11.0 12.3 13.5 1, 2, 3 9.5 10.7 12.0 UVLOHYS V 22, 37 1.6 *All typical values at TA = 25°C and VCC − VEE = 30 V, unless otherwise noted. 5 Switching Specifications (AC) Over recommended operating conditions (TA = -55 to +125°C, IF(ON) = 10 to 18 mA, VF(OFF) = -3.0 to 0.8V, VCC = 15 to 30 V, VEE = Ground), unless otherwise specified. Parameter Propagation Delay Time to High Output Level Symbol tPLH Propagation Delay tPHL Time to Low Output Level Pulse Width Distortion Test Conditions Rg = 10 Ω, Cg = 10 nF, f = 10 kHz, Duty Cycle = 50% Group A Subgroups (13) Limits Units Fig Note 0.50 µs 10, 11, 12, 13, 14, 23 11 0.50 µs 0.3 µs 0.35 µs 33, 34 23 Min. Typ.* Max. 0.10 0.30 0.10 0.30 9, 10, 11 9, 10, 11 PWD 9, 10, 11 Propagation Delay PDD Difference Between (tPHL − tPLH) Any Two Parts -0.35 12 Rise Time tr 0.1 µs Fall Time tf 0.1 µs µs 22 10 kV/µs 24 10 kV/µs UVLO Turn On Delay tUVLO ON VO > 5 V, IF = 10 mA 0.8 UVLO Turn Off Delay tUVLO OFF VO < 5 V, IF = 10 mA 0.6 Output High Level |CMH| Common Mode Transient Immunity IF = 10mA, VCM = 1000 V, VCC = 30 V TA = 25°C Output Low Level |CML| Common Mode Transient Immunity VCM = 1000 V, VF = 0 V, VCC = 30 V TA = 25°C 9 9 *All typical values at TA = 25°C and VCC − VEE = 30 V, unless otherwise noted. 6 7 9, 10, 11 8, 9, 14 8, 10, 14 Package Characteristics Over recommended operating conditions (TA = -55 to +125°C) unless otherwise specified. Parameter Symbol Test Conditions Input-Output Leakage Current II-O VI-O = 1500Vdc RH = 45%, t = 5 sec., TA = 25°C Resistance (Input-Output) RI-O VI-O = 500 VDC Capacitance (Input-Output) CI-O f = 1 MHz Group A Subgroups (13) Limits Units Min. Typ.* Fig Note Max. µA 5, 6 1010 Ω 6 2.5 pF 6 1 1.0 *All typicals at TA = 25°C. Notes: 1. Maximum pulse width = 10 µs, maximum duty cycle = 0.2%. This value is intended to allow for component tolerances for designs with IO peak minimum = 2.0 A. See Applications section for additional details on limiting IOH peak. 2. Maximum pulse width = 50 µs, maximum duty cycle = 0.5%. 3. In this test VOH is measured with a dc load current. When driving capacitive loads VOH will approach VCC as IOH approaches zero amps. 4. Maximum pulse width = 1 ms, maximum duty cycle = 20%. 5. This is a momentary withstand test, not an operating condition. 6. Device considered a two-terminal device: pins on input side shorted together and pins on output side shorted together. 7. The difference between tPHL and tPLH between any two HCPL-5120 parts under the same test condition. 8. Pins 1 and 4 need to be connected to LED common. 9. Common mode transient immunity in the high state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the output will remain in the high state (i.e., VO > 15.0 V). 10. Common mode transient immunity in a low state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the output will remain in a low state (i.e., VO < 1.0 V). 11. This load condition approximates the gate load of a 1200 V/75A IGBT. 12. Pulse Width Distortion (PWD) is defined as |tPHL-tPLH| for any given device. 13. Standard parts receive 100% testing at 25°C (Subgroups 1 and 9). SMD and Class H parts receive 100% testing at 25, 125, and -55°C (Subgroups 1 and 9, 2 and 10, 3 and 11, respectively). 14. Parameters are tested as part of device initial characterization and after design and process changes. Parameters are guaranteed to limits specified for all lots not specifically tested. 7 1 2 3 IF = 10mA to 18mA VOUT = (VCC - 4V) VCC = 15 to 30V VEE = 0V 2.2 2.0 1.8 1.6 1.4 4 -55 -35 -15 5 25 45 65 85 TA - TEMPERATURE - oC -55 105 125 -35 -15 5 25 45 65 85 -2 -3 -4 -6 0.0 0.10 0.05 -55 -35 -15 5 25 45 65 85 3 2 1 105 125 -3 5 -15 5 25 45 65 VCC = 30V VEE = 0V IF = 10mA for ICCH IF = 0mA for ICCL 3.5 3.0 2.5 IF = 10mA for ICCH IF = 0mA for ICCL o TA = 25 C VEE = 0V 2.0 1.5 1.5 25 45 65 85 o TA - TEMPERATURE - C Figure 7. ICC vs. Temperature 105 125 15 20 25 VCC - SUPPLY VOLTAGE - V Figure 8. ICC vs. VCC 30 IFLH - LOW TO HIGH CURRENT THRESHOLD - mA 2.5 5 4 125 oC o 25 C o -5 C 3 2 1 0.5 1.0 1.5 2.0 IOL - OUTPUT LOW CURRENT - A 2.5 5.0 ICCH ICCL ICC - SUPPLY CURRENT - mA 3.0 -55 -35 -15 5 0.0 4.0 3.5 2.5 Figure 6. VOL vs. IOL ICCH ICCL 2.0 6 8 5 10 5 125 Figure 5. IOL vs. Temperature 4.0 2.0 VF(OFF) = -3.0 to 0.8V VCC = 15 to 30V VEE = 0V 7 o TA - TEMPERATURE - C o TA - TEMPERATURE - C Figure 4. VOL vs. Temperature 1.5 0 0 -55 0.00 1.0 8 VF(OFF) = -3.0 to 0.8V VOUT = 2.5V VCC = 15 to 30V VEE = 0V VOL - OUTPUT LOW VOLTAGE - V ILOW - OUTPUT LOW CURRENT - A 0.15 0.5 Figure 3. VOH vs. IOH 4 0.20 IF = 10 to 18mA VCC = 15 to 30V VEE = 0V -5 IOH - OUTPUT HIGH CURRENT - A Figure 2. IOH vs. Temperature VF(OFF) = -3.0 to 0.8V IOUT = 100mA VCC = 15 to 30V VEE = 0V 0.25 ICC - SUPPLY CURRENT - mA 125 125 oC 25 oC -5 oC TA - TEMPERATURE - C 0.30 8 105 -1 o Figure 1. VOH vs. Temperature VOL - OUTPUT LOW VOLTAGE - V (VOH - VCC) - OUTPUT HIGH VOLTAGE DROP - V 2.4 IF = 10mA to 18mA IOUT = -100mA VCC = 15 to 30V VEE = 0V IOH - OUTPUT HIGH CURRENT - A (VOH - VCC) - HIGH OUTPUT VOLTAGE DROP - V 0 4.5 4.0 VCC = 15 to 30V VEE = 0V OUTPUT = OPEN 3.5 3.0 2.5 2.0 1.5 -55 -35 -15 5 25 45 65 85 105 125 o TA - TEMPERATURE - C Figure 9. IFLH vs. Temperature 400 300 200 VCC = 30V, VEE = 0V Rg = 10 Ω, Cg = 10 nF o TA = 25 C Duty Cycle = 50% f = 10khz 400 TP - PROPAGATION DELAY- ns IF = 10mA VCC = 30V, VEE = 0V Rg = 10 Ω, Cg = 10 nF Duty Cycle = 50% o TA = 25 C, f = 10khz TP - PROPAGATION DELAY - ns TP - PROPAGATION DELAY - ns 500 500 500 300 200 6 30 Figure 10. Propagation Delay vs. VCC 100 -55 26 200 TPLH TPHL 10 20 30 40 50 Figure 13. Propagation Delay vs. Rg 5 25 45 65 85 TA - TEMPERATURE - oC 105 125 400 o TA = 25 C 25 300 200 20 15 10 5 TPLH TPHL 0 0 20 40 60 80 Cg - LOAD CAPACITANCE - nF Rg - SERIES LOAD RESISTANCE - Ω -15 30 VCC = 30V, VEE = 0V o TA = 25 C, IF = 10mA Rg = 10 Ω Duty Cycle = 50% f = 10khz 100 0 -35 Figure 12. Propagation Delay vs. Temperature VO - OUTPUT VOLTAGE - V TP - PROPAGATION DELAY -ns TP - PROPAGATION DELAY -ns 10 12 14 16 18 20 22 24 IF - FORWARD LED CURRENT - mA 500 VCC = 30V, VEE = 0V o TA = 25 C, IF = 10mA Cg = 10 nF Duty Cycle = 50% f = 10khz 300 100 8 Figure 11. Propagation Delay vs. IF 500 400 200 TPLH TPHL 100 100 20 25 VCC - SUPPLY VOLTAGE - V 300 TPLH TPHL TPLH TPHL 15 400 IF = 10mA VCC = 30V, VEE = 0V Rg = 10 Ω, Cg = 10 nF Duty Cycle = 50% f = 10khz Figure 14. Propagation Delay vs. Cg 100 0 1 2 3 4 IF - FORWARD LED CURRENT - mA 5 Figure 15. Transfer Characteristics 1000 IF - FORWARD CURRENT - mA TA = 25oC 100 10 1 0.1 0.01 0.001 1.10 1.20 1.30 1.40 1.50 1.60 VF - FORWARD VOLTAGE - V Figure 16. Input Current vs. Forward Voltage 9 1 8 0.1 µF 2 + _ 4V 7 IF = 10 to 18 mA + V CC = 15 _ to 30 V 3 6 IOH 4 1 8 0.1 µF 5 2 IOL 7 3 6 4 5 2.5 V + _ VCC = 15 to 30 V + _ VCC = 15 to 30 V + _ Figure 17. IOH Test Circuit 1 8 2 7 0.1 µF IF = 10 to 18 mA Figure 18. IOL Test Circuit VOH VCC = 15 to 30 V + _ 3 6 1 100 mA 0.1 µF 5 4 8 2 3 6 4 5 Figure 19. VOH Test Circuit 1 8 0.1 µF 2 Figure 20. VOL Test Circuit 7 IF VO > 5 V 3 6 4 5 + _ VCC = 15 to 30 V Figure 21. IFLH Test Circuit 1 8 0.1 µF IF = 10 mA 2 7 VO > 5 V 3 6 4 5 Figure 22. UVLO Test Circuit 10 + _ VCC 100 mA 7 VOL 1 8 + _ 500 Ω IF 0.1 µF IF = 10 to 18 mA 2 + _ 7 V CC = 15 to 30 V tr tf VO 10 KHz 50% DUTY CYCLE 3 6 90% 10 Ω 50% V OUT 10 nF 4 10% 5 t PLH Tr = T f < _ 10 ns t PHL Figure 23. tPLH, tPHL, tr, and tf Test Circuit and Waveforms V CM 1 IF B δt 0.1 µF A 5V δV 8 2 7 + _ 6 + _ 5 ∆t V OH SWITCH AT A: IF = 10 mA VO + _ ∆t V CC = 30 V VO 4 V CM 0V VO 3 = V OL SWITCH AT B: IF = 0 mA V CM = 1000 V Figure 24. CMR Test Circuit and Waveforms 11 Applications Information Eliminating Negative IGBT Gate Drive To keep the IGBT firmly off, the HCPL- 5120 has a very low maximum VOL specification of 0.5 V. The HCPL- 5120 realizes this very low VOL by using a DMOS transistor with 1 Ω (typical) on resistance in its pull down circuit. When the HCPL- 5120 is in the low state, the IGBT gate is shorted to the emitter by Rg + 1 Ω. Minimizing Rg and the lead inductance from the HCPL- 5120 to the IGBT gate and emitter (possibly by mounting the HCPL- 5120 on a small PC board directly above the IGBT) can eliminate the need for negative IGBT gate drive in many applications as shown in Figure 25. Care should be taken with such a PC board design to avoid routing the IGBT collector or emitter traces close to the HCPL- 5120 input as this can result in unwanted coupling of transient signals into the HCPL- 5120 and degrade performance. (If the IGBT drain must be routed near the HCPL- 5120 input, then the LED should be reverse- biased when in the off state, to prevent the transient signals coupled from the IGBT drain from turning on the HCPL- 5120.) Selecting the Gate Resistor (Rg) to Minimize IGBT Switching Losses. Step 1: Calculate Rg Minimum from the IOL Peak Specification. The IGBT and Rg in Figure 26 can be analyzed as a simple RC circuit with a voltage supplied by the HCPL- 5120. (VCC - VEE - VOL) Rg = ––––––––––––––––– IOLPEAK (VCC – VEE – 2V) = –––––––––––––––––– IOLPEAK (15 V + 5 V – 2V) = ––––––––––––––––––– 2.5 A Step 2: Check the HCPL-5120 Power Dissipation and Increase Rg if Necessary. The HCPL- 5120 total power dissipation (PT) is equal to the sum of the emitter power (PE) and the output power (PO): PT = PE + PO PE = IF • VF •Duty Cycle PO = PO(BIAS) + PO (SWITCHING) = ICC • (VCC - VEE) + ESW(Rg, Qg) • f For the circuit in Figure 26 with IF (worst case) = 18 mA, Rg = 8 Ω, Max Duty Cycle = 80%, Qg = 500 nC, f = 20 kHz and TA max = 125°C: PE = 18 mA•1.8 V•0.8 = 26 mW = 7.2Ω ≈ 8 Ω The VOL value of 2 V in the previous equation is a conservative value of VOL at the peak current of 2.5A (see Figure 6). At lower Rg values the voltage supplied by the HCPL5120 is not an ideal voltage step. This results in lower peak currents (more margin) than predicted by this analysis. When negative gate drive is not used VEE in the previous equation is equal to zero volts PO = 4.25 mA•20 V + 1.0 µJ • 20 kHz = 85 mW + 20 mW = 105 mW < 112 mW (PO(MAX) @ 125°C = 250 mW - 23°C • 6 mW/°C) The value of 4.25 mA for ICC in the previous equation was obtained by derating the ICC max of 5 mA (which occurs at 55°C) to ICC max at 125°C. Since PO for this case is less than PO(MAX), Rg of 8 Ω is appropriate. +5 V 1 270 Ω 8 0.1 µF 2 + _ V CC = 18 V + HVDC 7 Rg CONTROL INPUT 74XXX OPEN COLLECTOR 3 6 4 5 Figure 25. Recommended LED Drive and Application Circuit 12 Q1 3-PHASE AC Q2 - HVDC +5 V 1 8 270 Ω 0.1 µF 2 + _ V CC = 15 V + HVDC 7 Rg Q1 CONTROL INPUT 74XXX OPEN COLLECTOR 3 6 4 5 3-PHASE AC _ V EE = -5 V + Q2 - HVDC Figure 26. Typical Application Circuit with Negative IGBT Gate Drive LED Drive Circuit Considerations for Ultra High CMR Performance. PE Parameter Description IF 1 LED Current VF LED On Voltage Duty Cycle Maximum LED Duty Cycle PO Parameter Description ICC Supply Current VCC Positive Supply Voltage VEE Negative Supply Voltage ESW (Rg, Qg) Energy Dissipation in the HCPL-5120 for each IGBT Switching Cycle (See Figure 27) f Switching Frequency Esw - ENERGY PER SWITCHING CYCLE - µJ 7 Qg = 100 nC 6 Qg = 250 nC Qg = 500 nC 5 VCC = 19 V VEE = -9 V 4 3 2 1 0 0 20 40 60 80 100 Rg - GATE RESISTANCE - Ω Without a detector shield, the dominant cause of optocoupler CMR failure is capacitive coupling from the input side of the optocoupler, through the package, to the detector IC as shown in Figure 28. The HCPL5120 improves CMR performance by using a detector IC with an optically transparent Faraday shield, which diverts the capacitively coupled current away from the sensitive IC circuitry. However, this shield does not eliminate the capacitive coupling between the LED and optocoupler pins 5- 8 as shown in Figure 29. This capacitive coupling causes perturbations in the LED current during common mode transients and becomes the major source of CMR failures for a shielded optocoupler. The main design objective of a high CMR LED drive circuit becomes keeping the LED in the proper state (on or off) during common mode transients. For example, the recommended application circuit (Figure 25), can achieve 10 kV/µs CMR while minimizing component complexity. Techniques to keep the LED in the proper state are discussed in the next two sections. 8 CLEDP 2 7 3 6 CLEDN 4 5 Figure 28. Optocoupler Input to Output Capacitance Model for Unshielded Optocouplers. CLEDO1 1 8 CLEDP 2 7 CLEDO2 3 4 6 CLEDN SHIELD 5 Figure 29. Optocoupler Input to Output Capacitance Model for Shielded Optocouplers. Figure 27. Energy Dissipated in the HCPL-5120 for Each IGBT Switching Cycle 13 CMR with the LED On (CMRH). CMR with the LED Off (CMRL). A high CMR LED drive circuit must keep the LED on during common mode transients. This is achieved by overdriving the LED current beyond the input threshold so that it is not pulled below the threshold during a transient. A minimum LED current of 10 mA provides adequate margin over the maximum IFLH of 7 mA to achieve 10 kV/µs CMR. A high CMR LED drive circuit must keep the LED off (VF ≤ VF(OFF)) during common mode transients. For example, during a - dVcm/dt transient in Figure 30, the current flowing through CLEDP also flows through the RSAT and VSAT of the logic gate. As long as the low state voltage developed across the logic gate is less than VF(OFF), the LED will remain off and no common mode failure will occur. +5 V 1 8 1 0.1 µF CLEDP + VSAT _ The open collector drive circuit, shown in Figure 31, cannot keep the LED off during a +dVcm/dt transient, since all the current flowing through CLEDN must be supplied by the LED, and it is not recommended for applications requiring ultra high CMRL performance. Figure 32 is an alternative drive circuit which, like the recommended application circuit (Figure 25), does achieve ultra high CMR performance by shunting the LED in the off state. 7 2 + _ V CC = 18 V CLEDP 2 ILEDP 3 6 CLEDN 8 +5 V *** Rg 3 Q1 7 6 CLEDN ILEDN 4 5 SHIELD * THE ARROWS INDICATE THE DIRECTION OF CURRENT FLOW DURING ∆dVCM/dt + _ *** 4 5 SHIELD Figure 31. Not Recommended Open Collector Drive Circuit V CM Figure 30. Equivalent Circuit for Figure 25 During Common Mode Transient. 8 1 +5 V CLEDP 7 2 3 4 6 CLEDN SHIELD Figure 32. Recommended LED Drive Circuit for Ultra-High CMR 14 5 To minimize dead time in a given design, the turn on of LED2 should be delayed (relative to the turn off of LED1) so that under worst- case conditions, transistor Q1 has just turned off when transistor Q2 turns on, as shown in Figure 33. The amount of delay necessary to achieve this conditions is equal to the maximum value of the propagation delay difference specification, PDDMAX, which is specified to be 350 ns over the operating temperature range of - 55°C to 125°C. Delaying the LED signal by the maximum propagation delay difference ensures that the minimum dead time is zero, but it does not tell a designer what the maximum dead time will be. The maximum dead time is equivalent to the difference between the maximum and minimum propagation delay difference specifications as shown in Figure 34. The maximum dead time for the HCPL- 5120 is 700 ns (= 350 ns - (- 350 ns)) over an operating temperature range of - 55°C to 125°C. optocouplers under consideration are typically mounted in close proximity to each other and are switching identical IGBTs. ILED1 *PDD = PROPAGATION DELAY DIFFERENCE V OUT1 Q1 ON Q1 OFF Q2 ON Q2 OFF V OUT2 NOTE: FOR PDD CALCULATIONS THE PROPAGATION DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS. ILED2 tPHL MAX tPLH MIN PDD* MAX = (tPHL - tPLH)MAX = tPHL MAX - tPLH MIN Figure 33. Minimum LED Skew for Zero Dead Time ILED1 *PDD = PROPAGATION DELAY DIFFERENCE VOUT1 Q1 ON Q1 OFF Q2 ON VOUT2 Q2 OFF NOTE: FOR DEAD TIME AND PDD CALCULATIONS ALL PROPAGATION DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS. ILED2 tPHL MIN tPHL MAX tPLH MIN tPLH MAX (tPHL - tPLH) MAX = PDD* MAX MAXIMUM DEAD TIME (DUE TO OPTOCOUPLER) = (tPHL MAX - tPHL MIN) + (tPLH MAX - tPLH MIN) = (tPHL MAX - tPLH MIN) - (tPHL MIN - tPLH MAX) = PDD* MAX - PDD* MIN Figure 34. Waveforms for Dead Time Calculations 50 300 250 40 PO - OUTPUT POWER - mW The HCPL- 5120 includes a Propagation Delay Difference (PDD) specification intended to help designers minimize “dead time” in their power inverter designs. Dead time is the time period during which both the high and low side power transistors (Q1 and Q2 in Figure 25) are off. Any overlap in Q1 and Q2 conduction will result in large currents flowing through the power devices between the high and low voltage motor rail Note that the propagation delays used to calculate PDD and dead time are taken at equal temperatures and test conditions since the PE - INPUT POWER - mW IPM Dead Time and Propagation Delay Specifications. 30 20 10 0 -55 case-to-ambient thermal resistance = 70 oC/W o = 140 C/W o = 210 C/W -25 5 35 95 65 o TA - AMBIENT TEMPERATURE - C Figure 35. Input Thermal Derating Curve, Dependence of case-to-ambient Thermal Resistance 200 150 100 50 0 -55 125 case-to-ambient thermal resistance o = 70 C/W o = 140 C/W o = 210 C/W -25 5 35 65 95 o TA - AMBIENT TEMPERATURE - C 125 Figure 36. Output Thermal Derating Curve, Dependence of case-to-ambient Thermal Resistance 15 Under Voltage Lockout Feature. MIL-PRF-38534 Class H and DSCC SMD Test Program 7 14 When the HCPL-5120 output is in the low state and the supply voltage rises above the HCPL-5120 VUVLO+ threshold (11.0 < VUVLO+ < 13.5) the optocoupler output will go into the high state (assuming LED is “ON”) with a typical delay, UVLO Turn On Delay of 0.8 µs. www.agilent.com/ semiconductors For product information and a complete list of distributors, please go to our web site. For technical assistance call: Americas/Canada: +1 (800) 235-0312 or (916) 788-6763 Europe: +49 (0) 6441 92460 China: 10800 650 0017 Hong Kong: (+65) 6756 2394 India, Australia, New Zealand: (+65) 6755 1939 Japan: (+81 3) 3335-8152 (Domestic/International) or 0120-61-1280 (Domestic Only) Korea: (+65) 6755 1989 Singapore, Malaysia, Vietnam, Thailand, Philippines, Indonesia: (+65) 6755 2044 Taiwan: (+65) 6755 1843 Data subject to change. Copyright2004 Agilent Technologies, Inc. June 28, 2004 5989-0942EN 12 VO - OUTPUT VOLTAGE - V The HCPL-5120 contains an under voltage lockout (UVLO) feature that is designed to protect the IGBT under fault conditions which cause the HCPL-5120 supply voltage (equivalent to the fully-charged IGBT gate voltage) to drop below a level necessary to keep the IGBT in a low resistance state. When the HCPL5120 output is in the high state and the supply voltage drops below the HCPL-5120 VUVLO– threshold (9.5 < VUVLO– < 12.0) the optocoupler output will go into the low state with a typical delay, UVLO Turn Off Delay, of 0.6 µs. Agilent Technologies’ Hi- Rel Optocouplers are in compliance with MIL- PRF- 38534 Class H. Class H devices are also in compliance with DSCC drawing 5962- 04204. (12.3, 10.8) 10 (10.7, 9.2) 8 6 4 2 (10.7, 0.1) 0 0 5 (12.3, 0.1) 10 15 (VCC - VEE) - SUPPLY VOLTAGE - V Figure 37. Under Voltage Lock Out 20 Testing consists of 100% screening and quality conformance inspection to MILPRF- 38534.