NT256D64SH8B0GM 256MB : 32M x 64 PC2100 Unbuffered DDR SO-DIMM 200pin Unbuffered DDR SO-DIMM Based on DDR266 16Mx16 SDRAM Features • JEDEC Standard 200-Pin Small Outline Dual In-Line Memory • Data is read or written on both clock edges Module (SO-DIMM) • DRAM DLL aligns DQ and DQS transitions with clock • 32Mx64 Double Unbuffered DDR SO-DIMM based on 16Mx16 transitions. DDR SDRAM. • Address and control signals are fully synchronous to positive • Performance: clock edge • Programmable Operation: PC2100 Speed Sort -75B DIMM CAS Latency 2.5 - DIMM CAS Latency: 2, 2.5 Unit - Burst Type: Sequential or Interleave f CK Clock Frequency 133 MHz t CK Clock Cycle 7.5 ns f DQ DQ Burst Frequency 266 MHz - Burst Length: 2, 4, 8 - Operation: Burst Read and Write • Auto Refresh (CBR) and Self Refresh Modes • Intended for 133 MHz applications • Automatic and controlled precharge commands • Inputs and outputs are SSTL-2 compatible • 13/9/2 Addressing (row/column/bank) • VDD = 2.5Volt ± 0.2, VDDQ = 2.5Volt ± 0.2 • 7.8 µs Max. Average Periodic Refresh Interval • SDRAMs have 4 internal banks for concurrent operation • Serial Presence Detect • Module has two physical banks • Gold contacts • Differential clock inputs • SDRAMs in 66-pin TSOP Type II Package Description NT256D64SH8B0GM is an unbuffered 200-Pin Double Data Rate (DDR) Synchronous DRAM Small Outline Dual In-Line Memory Module (SO-DIMM), organized as a two-bank 32Mx64 high-speed memory array. The module uses eight 16Mx16 DDR SDRAMs in 400 mil TSOP II packages. These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these common design files minimizes electrical variation between suppliers. All NANYA DDR SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 2.66” long space-saving footprint. The DIMM is intended for use in applications operating up to 133 MHz clock speeds and achieves high-speed data transfer rates of up to 266 MHz. Prior to any access operation, the device CAS latency and burst type/ length/operation type must be programmed into the DIMM by address inputs A0-A12 and I/O inputs BA0 and BA1 using the mode register set cycle. The DIMM uses serial presence-detect implemented via a serial 2,048-bit EEPROM using a standard IIC protocol. The first 128 bytes of serial PD data are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer. Ordering Information Part Number Speed Organization Leads Power 32Mx64 Gold 2.5V 133MHz (7.5ns @ CL = 2.5) NT256D64SH8B0GM-75B DDR266B PC2100 100MHz (10ns @ CL = 2) REV 1.3 01/2003 1 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT256D64SH8B0GM 256MB : 32M x 64 PC2100 Unbuffered DDR SO-DIMM Pin Description CK0, CK1, CK2, Differential Clock Inputs DQ0-DQ63 Data input/output Clock Enable DQS0-DQS7 Bi-directional data strobes RAS Row Address Strobe DM0-DM7 Data Masks CAS Column Address Strobe VDD Power (2.5V) CK0, CK1, CK2 CKE0, CKE1 WE Write Enable VDDQ Supply voltage for DQs(2.5V) S0, S1 Chip Selects VSS Ground A0-A9, A11, A12 Address Inputs NC No Connect A10/AP Address Input/Autoprecharge SCL Serial Presence Detect Clock Input BA0, BA1 SDRAM Bank Address Inputs SDA Serial Presence Detect Data input/output VREF Ref. Voltage for SSTL_2 inputs SA0-2 Serial Presence Detect Address Inputs VDDID VDD Identification flag. VDDSPD Serial EEPROM positive power supply (2.5V) Pinout Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back 1 VREF 2 VREF 51 VSS 52 VSS 101 A9 102 A8 151 DQ42 152 DQ46 3 VSS 4 VSS 53 DQ19 54 DQ23 103 VSS 104 VSS 153 DQ43 154 DQ47 5 DQ0 6 DQ4 55 DQ24 56 DQ28 105 A7 106 A6 155 VDD 156 VDD 7 DQ1 8 DQ5 57 VDD 58 VDD 107 A5 108 A4 157 VDD 158 CK1 9 VDD 10 VDD 59 DQ25 60 DQ29 109 A3 110 A2 159 VSS 160 CK1 11 DQS0 12 DM0 61 DQS3 62 DM3 111 A1 112 A0 161 VSS 162 VSS 13 DQ2 14 DQ6 63 VSS 64 VSS 113 VDD 114 VDD 163 DQ48 164 DQ52 15 VSS 16 VSS 65 DQ26 66 DQ30 115 A10/AP 116 BA1 165 DQ49 166 DQ53 17 DQ3 18 DQ7 67 DQ27 68 DQ31 117 VDD 118 RAS 167 VDD 168 VDD 19 DQ8 20 DQ12 69 VDD 70 VDD 119 WE 120 CAS 169 DQS6 170 DM6 21 VDD 22 VDD 71 NC 72 NC 121 S0 122 S1 171 DQ50 172 DQ54 23 DQ9 24 DQ13 73 NC 74 NC 123 DU 124 DU 173 VSS 174 VSS 25 DQS1 26 DM1 75 VSS 76 VSS 125 VSS 126 VSS 175 DQ51 176 DQ55 27 VSS 28 VSS 77 DQS8 78 NC 127 DQ32 128 DQ36 177 DQ56 178 DQ60 29 DQ10 30 DQ14 79 NC 80 NC 129 DQ33 130 DQ37 179 VDD 180 VDD 31 DQ11 32 DQ15 81 VDD 82 VDD 131 VDD 132 VDD 181 DQ57 182 DQ61 33 VDD 34 VDD 83 NC 84 NC 133 DQS4 134 DM4 183 DQS7 184 DM7 35 CK0 36 VDD 85 DU 86 DU 135 DQ34 136 DQ38 185 VSS 186 VSS 37 CK0 38 VSS 87 VSS 88 VSS 137 VSS 138 VSS 187 DQ58 188 DQ62 39 VSS 40 VSS 89 CK2 90 VSS 139 DQ35 140 DQ39 189 DQ59 190 DQ63 41 DQ16 42 DQ20 91 CK2 92 VDD 141 DQ40 142 DQ44 191 VDD 192 VDD 43 DQ17 44 DQ21 93 VDD 94 VDD 143 VDD 144 VDD 193 SDA 194 SA0 45 VDD 46 VDD 95 CKE1 96 CKE0 145 DQ41 146 DQ45 195 SCL 196 SA1 47 DQS2 48 DM2 97 DU 98 DU 147 DQS5 148 DM5 197 VDDSPD 198 SA2 49 DQ18 50 DQ22 99 A12 100 A11 149 VSS 150 VSS 199 VDDID 200 DU Note: All pin assignments are consistent for all 8-byte unbuffered versions. REV 1.3 01/2003 2 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT256D64SH8B0GM 256MB : 32M x 64 PC2100 Unbuffered DDR SO-DIMM Input/Output Functional Description Symbol Type CK0, CK1, CK2, CK0, CK1, CK2 CKE0, CKE1 (SSTL) (SSTL) Polarity Cross point Active High Function The system clock inputs. All address and command lines are sampled on the cross point of the rising edge of CK and falling edge of CK. A Delay Locked Loop (DLL) circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock. Activates the DDR SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh mode. Enables the associated DDR SDRAM command decoder when low and disables the (SSTL) Active Low command decoder when high. When the command decoder is disabled, new commands RAS, CAS, WE (SSTL) Active Low When sampled at the positive rising edge of the clock, RAS, CAS, WE define the operation VREF Supply VDDQ Supply BA0, BA1 (SSTL) S0, S1 are ignored but previous operations continue. Physical Bank 0 is selected by S0; Bank 1 is selected by S1. to be executed by the SDRAM. Reference voltage for SSTL-2 inputs Isolated power supply for the DDR SDRAM output buffers to provide improved noise immunity - Selects which SDRAM bank is to be active. During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12) when sampled at the rising clock edge. During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9) when sampled at the rising clock edge. In addition to the column address, AP is used to A0 - A9 A10/AP A11, A12 (SSTL) - invoke autoprecharge operation at the end of the Burst Read or Write cycle. If AP is high, autoprecharge is selected and BA0/BA1 define the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge. DQ0 - DQ63 (SSTL) - DQS0 - DQS7 (SSTL) Active High DM0 – DM7 Input Active High VDD, VSS Supply Data and Check Bit input/output pins operate in the same manner as on conventional DRAMs. Data strobes: Output with read data, input with write data. Edge aligned with read data, centered on write data. Used to capture write data. The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect. DM8 is associated with check bits CB0-CB7, and is not used on x64 modules. Power and ground for the DDR SDRAM input buffers and core logic SA0 – SA2 - SDA - SCL - VDDSPD REV 1.3 01/2003 Supply Address inputs. Connected to either VDD or VSS on the system board to configure the Serial Presence Detect EEPROM address. This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA bus line to V DD to act as a pullup. This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time to V DD to act as a pullup. Serial EEPROM positive power supply. 3 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT256D64SH8B0GM 256MB : 32M x 64 PC2100 Unbuffered DDR SO-DIMM Functional Block Diagram (2 Bank, 16Mx16 DDR SDRAMs) S1 S0 DQS0 DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 LDQS DQS1 DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 UDQS DQS3 DM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 UDQS CS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D1 UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 LDQS UDQS CAS : SDRAMs D0-D7 CKE : SDRAMs D0-D3 CKE1 CKE : SDRAMs D4-D7 WE : SDRAMs D0-D7 LDQS DQS5 DM5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 UDQS CS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 LDQS DQS7 DM7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 UDQS D2 UDQS D6 UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 CS LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D3 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 SPD D0-D7 D0-D7 D0-D7 CS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 LDQS VDDSPD VDD/VDDQ VREF VSS VDDID CS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS6 DM6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 D5 BA0-BA1 : SDRAMs D0-D7 CAS DQS4 DM4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 D4 A0-A12 : SDRAMs D0-D7 CKE0 REV 1.3 UDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 RAS : SDRAMs D0-D7 Notes : 1. 2. 3. 4. CS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 RAS WE 01/2003 D0 UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 LDQS A0-A12 LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 BA0-BA1 CS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D7 UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 CK0 CK0 4 loads CK1 CK1 4 loads Serial PD CK2 SCL WP A0 A1 A2 SA0 SA1 SA2 SDA CK2 0 loads DQ wiring may differ from that described in this drawing. DQ/DQS/DM/CKE/S relationships are maintained as shown. DQ/DQS/DM/DQS resistors are 22+/- 5% Ohms. VDDID strap connections (for memory device VDD, VDDQ): STRAP OUT (OPEN): VDD = VDDQ STRAP IN (VSS): VDD is not equal to VDDQ. 4 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT256D64SH8B0GM 256MB : 32M x 64 PC2100 Unbuffered DDR SO-DIMM Serial Presence Detect -- Part 1 of 2 32Mx64 SDRAM DIMM based on 16Mx16, 4Banks, 8K Refresh, 2.5V DDR SDRAMs with SPD SPD Entry Value Byte Description Serial PD Data Entry (Hexadecimal) DDR266B DDR266B -75B -75B 0 Number of Serial PD Bytes Written during Production 128 80 1 Total Number of Bytes in Serial PD device 256 08 2 Fundamental Memory Type 3 SDRAM DDR 07 Number of Row Addresses on Assembly 13 0D 4 Number of Column Addresses on Assembly 9 09 5 Number of DIMM Bank 2 02 6 Data Width of Assembly X64 40 X64 00 7 Data Width of Assembly (cont’) 8 Voltage Interface Level of this Assembly 9 DDR SDRAM Device Cycle Time at CL=2.5 10 DDR SDRAM Device Access Time from Clock at CL=2.5 11 DIMM Configuration Type 12 Refresh Rate/Type SSTL 2.5V 04 7.5ns 75 0.75ns 75 Non-Parity 00 SR/1x(7.8us) 82 13 Primary DDR SDRAM Width X16 10 14 Error Checking DDR SDRAM Device Width N/A 00 1 Clock 01 0E 15 DDR SDRAM Device Attr: Min CLK Delay, Random Col Access 16 DDR SDRAM Device Attributes: Burst Length Supported 2,4,8 17 DDR SDRAM Device Attributes: Number of Device Banks 4 04 18 DDR SDRAM Device Attributes: CAS Latencies Supported 2/2.5 0C 19 DDR SDRAM Device Attributes: CS Latency 0 01 20 DDR SDRAM Device Attributes: WE Latency 1 02 Differential Clock 20 21 DDR SDRAM Device Attributes: 22 DDR SDRAM Device Attributes: General 23 Minimum Clock Cycle at CL=2 24 Maximum Data Access Time from Clock at CL=2 25 Minimum Clock Cycle Time at CL=1 +/-0.2V Voltage Tolerance 00 10ns A0 0.75ns 75 N/A 00 26 Maximum Data Access Time from Clock at CL=1 N/A 00 27 Minimum Row Precharge Time (tRP) 20ns 50 28 Minimum Row Active to Row Active delay (tRRD) 15ns 3C 29 Minimum RAS to CAS delay (tRCD) 20ns 50 30 Minimum RAS Pulse Width (tRAS) 45ns 2D 31 Module Bank Density 128MB 20 32 Address and Command Setup Time Before Clock 0.9ns 90 33 Address and Command Hold Time After Clock 0.9ns 90 34 Data Input Setup Time Before Clock 0.5ns 50 35 Data Input Hold Time After Clock 0.5ns 50 Undefined 00 36-61 Reserved 62 SPD Revision 63 Checksum Data REV 1.3 01/2003 Initial Note 00 A7 5 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT256D64SH8B0GM 256MB : 32M x 64 PC2100 Unbuffered DDR SO-DIMM Serial Presence Detect -- Part 2 of 2 32Mx64 SDRAM DIMM based on 16Mx16, 4Banks, 8K Refresh, 2.5V DDR SDRAMs with SPD SPD Entry Value Byte Description DDR266B 64-71 Manufacturer’s JEDEC ID Code 72 Module Manufacturing Location Serial PD Data Entry (Hexadecimal) DDR266B -75B -75B NANYA 7F7F7F0B00000000 N/A 00 73-90 Module Part number N/A 00 91-92 Module Revision Code N/A 00 Year/Week Code yy/ww Serial Number 00 Undefined 00 93-94 Module Manufacturing Data 95-98 Module Serial Number 99-255 Reserved 1. yy= Binary coded decimal year code, 0-99(Decimal), 00-63(Hex) 2. ww= Binary coded decimal year code, 01-52(Decimal), 01-34(Hex) REV 1.3 01/2003 Note 1, 2 6 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT256D64SH8B0GM 256MB : 32M x 64 PC2100 Unbuffered DDR SO-DIMM Absolute Maximum Ratings Symbol VIN, VOUT Voltage on I/O pins relative to Vss Rating Units -0.5 to VDDQ+0.5 V VIN Voltage on Input relative to Vss -0.5 to +3.6 V VDD Voltage on VDD supply relative to Vss -0.5 to +3.6 V Voltage on VDDQ supply relative to Vss -0.5 to +3.6 V 0 to+70 °C -55 to +150 °C Power Dissipation 8 W Short Circuit Output Current 50 mA VDDQ TA TSTG PD IOUT Note: Parameter Operating Temperature (Ambient) Storage Temperature (Plastic) Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Capacitance Symbol Max. Units Notes Input Capacitance: CK0, CK0, CK1, CK1, CK2, CK2 CI1 12 pF 1 Input Capacitance: A0-A11, BA0, BA1, WE, RAS, CAS, CKE0, S0 CI2 30 pF 1 Input Capacitance: SA0-SA2, SCL CI4 9 pF 1 CIO1 7 pF 1, 2 Parameter Input/Output Capacitance DQ0-63; DQS0-7 CIO3 pF Input/Output Capacitance: SDA 11 1. VDDQ = VDD = 2.5V ± 0.2V, f = 100 MHz, TA = 25 °C, VOUT (DC) = VDDQ/2, VOUT (Peak to Peak) = 0.2V. 2. DQS inputs are grouped with I/O pins reflecting the fact that they are matched in loading to DQ and DQS to facilitate trace matching at the board level. REV 1.3 01/2003 7 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT256D64SH8B0GM 256MB : 32M x 64 PC2100 Unbuffered DDR SO-DIMM DC Electrical Characteristics and Operating Conditions (TA = 0 °C ~ 70 °C; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics) Symbol Min Max Units Notes Supply Voltage 2.3 2.7 V 1 I/O Supply Voltage 2.3 2.7 V 1 0 0 V I/O Reference Voltage 0.49 x VDDQ 0.51 x VDDQ V 1, 2 I/O Termination Voltage (System) VREF – 0.04 VREF + 0.04 V 1, 3 VIH (DC) Input High (Logic1) Voltage VREF + 0.15 VDDQ + 0.3 V 1 VIL (DC) Input Low (Logic0) Voltage -0.3 VREF- 0.15 V 1 VIN (DC) Input Voltage Level, CK and CK Inputs -0.3 VDDQ + 0.3 V 1 VID (DC) Input Differential Voltage, CK and CK Inputs 0.30 V DDQ + 0.6 V 1, 4 -5 5 uA 1 -5 5 uA 1 -16.8 - mA 1 16.8 - mA 1 VDD VDDQ VSS, VSSQ VREF VTT Parameter Supply Voltage, I/O Supply Voltage Input Leakage Current II Any input 0V ≤ VIN ≤ VDD; (All other pins not under test = 0V) Output Leakage Current IOZ (DQs are disabled; 0V ≤ Vout ≤ VDDQ Output High Current IOH (VOUT = VDDQ -0.373V, min VREF, min VTT) Output Low Current IOL (VOUT = 0.373, max VREF, max VTT) 1. Inputs are not recognized as valid until V REF stabilizes. 2. VREF is expected to be equal to 0.5 V DDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed 2% of the DC value. 3. VTT is not applied directly to the DIMM. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of V REF. 4. VID is the magnitude of the difference between the input level on CK and the input level on CK. REV 1.3 01/2003 8 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT256D64SH8B0GM 256MB : 32M x 64 PC2100 Unbuffered DDR SO-DIMM AC Characteristics (Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating Conditions, Operating, Standby, and Refresh Currents, and Electrical Characteristics and AC Timing.) 1. All voltages referenced to VSS. 2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Outputs measured with equivalent load. Refer to the AC Output Load Circuit below. 4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK, CK), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals is 1V/ns in the range between VIL (AC) and VIH (AC) unless otherwise specified. 5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively switches as a result of the signal crossing the AC input level, and remains in that state as long as the signal does not ring back above (below) the DC input LOW (HIGH) level. AC Output Load Circuits VTT 50 ohms Output Timing Reference Point VOUT 30 pF AC Operating Conditions (TA = 0 °C ~ 70 °C; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics) Symbol Parameter/Condition VIH (AC) Input High (Logic 1) Voltage. Min Max V REF + 0.31 VIL (AC) Input Low (Logic 0) Voltage. VID (AC) Input Differential Voltage, CK and CK Inputs VIX (AC) Input Differential Pair Cross Point Voltage, CK and CK Inputs Unit Notes V 1, 2 V REF - 0.31 V 1, 2 0.62 V DDQ + 0.6 V 1, 2, 3 (0.5*VDDQ) - 0.2 (0.5*VDDQ) + 0.2 V 1, 2, 4 1. Input slew rate = 1V/ ns. 2. Inputs are not recognized as valid until V REF stabilizes. 3. V ID is the magnitude of the difference between the input level on CK and the input level on CK. 4. The value of V IX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same. REV 1.3 01/2003 9 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT256D64SH8B0GM 256MB : 32M x 64 PC2100 Unbuffered DDR SO-DIMM Operating, Standby, and Refresh Currents (TA = 0 °C ~ 70 °C; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics) Symbol Parameter/Condition PC2100 Unit Notes 500 mA 1, 2 620 mA 1, 2 80 mA 1, 2 200 mA 1, 2 160 mA 1, 2 400 mA 1, 2 1100 mA 1, 2 800 mA 1, 2 1200 mA 1, 2, 4 24 mA 1, 2 1500 mA 1, 2 (-75B) Operating Current: one bank; active/precharge; tRC = tRC (MIN); tCK = tCK I DD0 (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle Operating Current: one bank; active/read/precharge; Burst = 2; tRC = tRC I DD1 (MIN); CL=2.5; tCK = tCK (MIN); IOUT = 0mA; address and control inputs changing once per clock cycle I DD2P I DD2N I DD3P Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE ≤ VIL (MAX); tCK = tCK (MIN) Idle Standby Current: CS ≥ VIH (MIN); all banks idle; CKE ≥ VIH (MIN); tCK = tCK (MIN); address and control inputs changing once per clock cycle Active Power-Down Standby Current: one bank active; power-down mode; CKE ≤ VIL (MAX); tCK = tCK (MIN) Active Standby Current: one bank; active/precharge; CS ≥ VIH (MIN); CKE ≥ I DD3N VIH (MIN); tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle Operating Current: one bank; Burst = 2; reads; continuous burst; address I DD4R and control inputs changing once per clock cycle; DQ and DQS outputs changing twice per clock cycle; CL = 2.5; tCK = tCK (MIN); IOUT = 0mA Operating Current: one bank; Burst = 2; writes; continuous burst; address I DD4W and control inputs changing once per clock cycle; DQ and DQS inputs changing twice per clock cycle; CL=2.5; tCK = tCK (MIN) I DD5 Auto-Refresh Current: tRC = tRFC (MIN) I DD6 Self-Refresh Current: CKE ≤ 0.2V Operating Current: four bank; four bank interleaving with BL = 4, address I DD7 and control inputs randomly changing; 50% of data changing at every transfer; tRC = tRC (min); IOUT = 0mA. 1. I DD specifications are tested after the device is properly initialized. 2. Input slew rate = 1V/ ns. 3. Enables on-chip refresh and address counters. 4. Current at 7.8 µs is time averaged value of IDD5 at tRFC (MIN) and IDD2P over 7.8 µs. REV 1.3 01/2003 10 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT256D64SH8B0GM 256MB : 32M x 64 PC2100 Unbuffered DDR SO-DIMM AC Timing Specifications for DDR SDRAM Devices Used on Module (TA = 0 °C ~ 70 °C; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics) (Part 1 of 2) Symbol tAC tDQSCK -75B Parameter Min. Max. DQ output access time from CK/CK -0.75 +0.75 Unit Notes ns 1-4 DQS output access time from CK/CK -0.75 +0.75 ns 1-4 tCH CK high-level width 0.45 0.55 tCK 1-4 tCL CK low-level width 0.45 0.55 tCK 1-4 CL=2.5 7.5 12 ns 1-4 CL=2 10 12 ns 1-4 tCK tCK Clock cycle time 1-4, tDH DQ and DM input hold time 0.5 ns tDS DQ and DM input setup time 0.5 ns tDIPW DQ and DM input pulse width (each input) 1.75 ns 1-4 tHZ Data-out high-impedance time from CK/CK -0.75 +0.75 ns 1-4, 5 tLZ Data-out low-impedance time from CK/CK -0.75 +0.75 ns 1-4, 5 0.5 ns 1-4 tCK 1-4 tCK 1-4 0.75ns tCK 1-4 1.25 tCK 1-4 0.35 tCK 1-4 0.2 tCK 1-4 0.2 tCK 1-4 Mode register set command cycle time 2 tCK 1-4 Write preamble setup time 0 ns 1-4, 7 tDQSQ tHP DQS-DQ skew (DQS & associated DQ signals) Minimum half clk period for any given cycle; defined by clk high (tCH) or clk low (tCL) time tQH Data output hold time from DQS tQHS Data hold Skew Factor tDQSS Write command to 1st DQS latching transition tDQSL,H tDSS tDSH tMRD tWPRES DQS input low (high) pulse width (write cycle) DQS falling edge to CK setup time (write cycle) DQS falling edge hold time from CK (write cycle) 15, 16 1-4, 15, 16 tCH or tCL tHP tQHS 0.75 tWPST Write postamble 0.40 tCK 1-4, 6 tWPRE Write preamble 0.25 tCK 1-4 0.9 ns 0.9 ns 1.0 ns tIH tIS tIH REV 1.3 01/2003 Address and control input hold time (fast slew rate) Address and control input setup time (fast slew rate) Address and control input hold time (slow slew rate) 0.60 2-4, 9, 11, 12 2-4, 9, 11, 12 2-4, 10, 11, 12, 14 11 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT256D64SH8B0GM 256MB : 32M x 64 PC2100 Unbuffered DDR SO-DIMM AC Timing Specifications for DDR SDRAM Devices Used on Module (TA = 0 °C ~ 70 °C; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics) (Part 2 of 2) Symbol Parameter -75B Min. Max. Unit Notes ns 10-12, 2-4, Address and control input setup time tIS 1.0 (slow slewrate) 14 ns 2-4, 12 1.1 tCK 1-4 0.40 0.60 tCK 1-4 Active to Precharge command 45 120,000 ns 1-4 Active to Active/Auto-refresh command period 65 ns 1-4 75 ns 1-4 tIPW Input pulse width 2.2 tRPRE Read preamble 0.9 tRPST Read postamble tRAS tRC Auto-refresh to Active/Auto-refresh command tRFC period tRCD Active to Read or Write delay 20 ns 1-4 tRAP Active to Read Command with Autoprecharge 20 ns 1-4 tRP Precharge command period 20 ns 1-4 tRRD Active bank A to Active bank B command 15 ns 1-4 tWR Write recovery time ns 1-4 tDAL Auto precharge write recovery + precharge time 15 (tWR/tCK ) + (tRP/tCK ) tCK 1-4, 13 tWTR Internal write to read command delay 1 tCK 1-4 tPDEX Power down exit time 7.5 ns 1-4 tXSNR Exit self-refresh to non-read command 75 ns 1-4 tXSRD Exit self-refresh to read command 200 tCK 1-4 tREFI Average Periodic Refresh Interval µs 1-4, 8 REV 1.3 01/2003 7.8 12 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT256D64SH8B0GM 256MB : 32M x 64 PC2100 Unbuffered DDR SO-DIMM AC Timing Specification Notes 1. Input slew rate = 1V/ns. 2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals other than CK/CK is VREF. 3. Inputs are not recognized as valid until VREF stabilizes. 4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is VTT. 5. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). 6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 7. The specific requirement is that DQS be valid (high, low, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from high to low at this time, depending on tDQSS. 8. A maximum of eight Auto refresh commands can be posted to any given DDR SDRAM device. 9. For command/address input slew rate >= 1.0 V/ns. Slew rate is measured between VOH (AC) and VOL (AC). 10. For command/address input slew rate >= 0.5 V/ns and < 1.0 V/ns. Slew rate is measured between VOH (AC) and VOL (AC). 11. CK/CK slew rates are >= 1.0 V/ns. 12. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by design or tester characterization. 13. For each of the terms in parentheses, if not already an integer, round to the next highest integer. t CK is equal to the actual system clock cycle time. For example, for PC2100 at CL= 2.5, t DAL = (15ns/7.5ns) +(20ns/7.0ns) = 2 + 3 = 5. 14. An input setup and hold time derating table is used to increase t IS and t IH in the case where the input slew rate is below 0.5 V/ns. Input Slew Rate 1. 2. Delta (tIH) Delta (tIS) Unit Note 0.5 V/ns 0 0 ps 1, 2 0.4 V/ns +50 0 ps 1, 2 0.3 V/ns +100 0 ps 1, 2 Input slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC), similarly for rising transitions. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device. 15. An input setup and hold time derating table is used to increase t DS and t DH in the case where the I/O slew rate is below 0.5 V/ns. 1. 2. Input Slew Rate Delta (tDS) Delta (tDH) Unit 0.5 V/ns 0 0 ps 1, 2 0.4 V/ns +75 +75 ps 1, 2 0.3 V/ns +150 +150 ps 1, 2 Note I/O slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC), similarly for rising transitions. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device. 16. An I/O Delta Rise, Fall Derating table is used to increase t DS and t DH in the case where DQ, DM, and DQS slew rates differ. 1. 2. 3. 4. Delta Rise and Fall Rate Delta (tDS) Delta (tDH) Unit Note 0.0 ns/V 0 0 ps 1-4 0.25 ns/V +50 +50 ps 1-4 0.5 ns/V +100 +100 ps 1-4 Input slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC), similarly for rising transitions. Input slew rate is based on the larger of AC to AC delta rise, fall rate and DC to DC delta rise, fall rate. The delta rise, fall rate is calculated as: [1/(slew rate 1)] - [1/(slew rate 2)] For example: slew rate 1 = 0.5 V/ns; slew rate 2 = 0.4 V/ns. Delta rise, fall = (1/0.5) - (1/0.4) [ns/V] = -0.5 ns/V Using the table above, this would result in an increase in t DS and t DH of 100 ps. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device. REV 1.3 01/2003 13 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT256D64SH8B0GM 256MB : 32M x 64 PC2100 Unbuffered DDR SO-DIMM Package Dimensions FRONT 67.60 (2X)Θ 1.80 1 2.15 39 41 31.75 20.00 6.00 4.00 63.60 199 11.40 Detail A Detail B 4.20 47.40 1.80 2.45 BACK SIDE 3.80 MAX 2 40 42 200 1.00+/- 0.10 Detail A 0.45 0.60 1.00+/- 0.1 2.55 4.00+/-0.10 0.25 MAX Detail B Note: All dimensions are typical with tolerances of +/- 0.15 unless otherwise stated. Units: Millimeters (Inches) REV 1.3 01/2003 14 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT256D64SH8B0GM 256MB : 32M x 64 PC2100 Unbuffered DDR SO-DIMM Revision Log Rev Date 0.1 08/2002 0.2 09/2002 Modification Preliminary Release Added tPDEX (Power down exit time) to AC Timing Table Updated IDD values for PC2100 in Operating, Standby, and Refresh Currents Table 1.0 09/2002 Official Release 1.1 10/2002 Updated IDD7 value to 1500 mA in Operating, Standby, and Refresh Currents Table 1.2 11/2002 Updated IDD6 value to 16 mA in Operating, Standby, and Refresh Currents Table 1.3 01/2003 Updated IDD6 value to 24 mA in Operating, Standby, and Refresh Currents Table Removed DDR333 (-6K) speed grade REV 1.3 01/2003 15 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.